An Evolutionary Approach for VLSI Standard Cell Design

Anil Bahuman
Artificial Intelligence Center University of Georgia Athens, GA 30602 abahuman@ai.uga.edu

Khaled Rasheed
Dept. of Computer Science University of Georgia Athens, GA 30602 khlaed@cs.uga.edu

Benjamin Bishop
Dept. of Computer Science University of Georgia Athens, GA 30602 bishop@cs.uga.edu

Abstract
Standard cell design is a challenging task faced by VLSI chip designers. Traditional methods of standard cell design automation rely on a schematic representation supplied by a design engineer. We have demonstrated the possibility of applying a genetic algorithm (GADO) to design a cell given only a behavioral description (truth table). A working inverter is designed as a proof of concept.

I. INTRODUCTION There is a need for heuristic automation methods that can suggest engineering designs allowing human designers to add only the final touches. An example of the need for design automation techniques is the design of integrated circuits. The field poses one of the toughest challenges to the evolutionary computation community (and others interested in design optimization) since large-scale, coupled optimization problems commonly arise. Mazumder and Rudnick [12] provide a good survey of problems faced by the VLSI community and demonstrate some genetic algorithm based solutions. We demonstrate the possibility of one such tool [3,4] that can assist engineers to build standard cells (the lowest level of logic where a designer is working at the transistor level; designers use them as building blocks to synthesize higher level logic functions) on-the-fly customized to ad-hoc constraints that they need to address in their design. Our method is an example of design by evolution using genetic algorithms. Standard cell methodology is widely used in IC design. Considerable effort [1,11,12,15,16] has been invested in attempting to automate the design of a standard cell. Automation of standard cell layout generation (1) significantly improves turnaround time for creating new standard cell libraries, (2) provides a test bed for evaluating new process technologies by rapidly synthesizing cells and (3) enables rapid migration of designs to new process technologies. Most existing methods for cell synthesis start with a schematic specifying how all transistors are connected (netlist) and automate the processes of (1) placing the transistors (placement), followed by (2) figuring out the connecting wires between transistor terminals (routing) and

finally (3) minimizing the area occupied by the circuit (compaction). Our implementation combines all these three steps and attempts to evolve circuits on-the-fly given only a behavioral (truth-table like) description. The input specification consists of: (labels and cell templates are defined in Section II B) 1. A truth table description of the input and output with as many possible transitions (more on this ahead). 2. A set of building blocks consisting of geometries of objects such as transistors, piece of polysilicon, piece of polycontact etc (see Figure 2). 3. A classification of labels used (as inputs and outputs). 4. A cell template specifying the placement of fixed ports (if any). A design rule checker (MAGIC) and circuit simulator (SPICE) are used by the genetic algorithm to evaluate and validate designs. MAGIC [17] is one of the layout editors used by designers to create cells. Figure 3 is a snapshot of a cell design as it appears in MAGIC. It is essentially a smart tool that allows the designer to place colored polygons that represent physical layers that form the complex circuitry on a chip. The tool is aware of the electrical characteristics of the materials and has been programmed with a set of design rules for a given technology. Design rules are constraints on the placement and shapes of polygons that reflect the practical constraints (such as tolerance levels) that the foundry which eventually etches the electronic copy of the design onto silicon has to deal with. SPICE [18] is a circuit simulation tool that can take a layout extracted from MAGIC and check to see if the circuit is behaving as intended and also conduct analyses of various performance parameters such as circuit delay, power dissipation etc. The genetic algorithm uses these external simulators to evaluate its designs and attach the final fitness value to a candidate design (Figure 10). A. Our Research Goal Given the goal of automating phases 1, 2 and 3 above into a single phase, we set out to explore the possibility of accomplishing this for a very simple standard cell the CMOS inverter without a schematic and without incorporating any design heuristics for transistor sizing,

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splitting, ordering, placement, routing or compaction. The tools we decided to work with were MAGIC a layout schematic editor, SPICE a circuit simulator and a modified version of GADO [4] a design optimization engine (Section II A). Our goal was to start from a behavioral description for an inverter, an optimization criterion and a set of building blocks (different types/clusters of transistors, piece of poly, piece of metal1, piece of ndcontact etc.) and attempt to automate the process of finding a working inverter optimized for the given criterion as a proof of concept. The behavioral description consisted of a truth table of inputs and outputs with all possible input transitions (0 to 1 and 1 to 0). This is because certain designs may fail on some transitions. Table 1 lists all the input transitions used for the inverter with corresponding outputs.
TABLE 1: BEHAVIORAL DESCRIPTION INPUT OUTPUT 0 1 1 0 0 1

A steady state GA model is used, in which operators are applied to two parents selected from the elements of the population via some selection scheme, one offspring point is produced, then an existing point in the population is replaced by the newly generated point via some replacement strategy. Here selection was performed by rank because of the wide range of fitness values. The replacement strategy used here is a crowding technique, which takes into consideration both the fitness and the proximity of the points in the GA population. The GA stops when either the maximum number of evaluations has been exhausted or the population loses diversity and practically converges to a single point in the search space. Several crossover and mutation operators are used [4], most of which were designed specifically for the target domain type. GADO also uses a search-control method [4] that saves time by avoiding the evaluation of points that are unlikely to correspond to good designs. B. Representation We use integers to encode a layout. Each design is represented in the algorithm as a string (Figure 1) of Objects corresponding to each component in the physical layout:

But what about testing different input sequences? There are an infinite number of input sequences and it is possible that a design with unnecessary states fails at a certain input sequence. Our own experience with this algorithm is that it tends to find the simplest design and hence the correct design. This is because complicated designs that have more components also occupy more area and hence receive higher penalties than simple designs. (The penalty scheme used in the fitness function is discussed in 2.3). Another question that needs to be addressed is the justification for using a behavioral description as opposed to the traditional schematic description. We believe that this added degree of freedom creates more room for innovation. The algorithm simultaneously searches for the optimal layout as well as the optimal schematic. II. AN EVOLUTIONARY APPROACH A. Genetic Algorithms for Design Optimization Genetic Algorithms (GAs) are a class of heuristic algorithms that can search for a solution by a process similar to natural selection i.e. the desired characteristics of the solution are enhanced by continued breeding [14]. We use GADO, which is a steady state Genetic Algorithm for Design Optimization tool developed by Khaled Rasheed for his PhD dissertation [4], for applications in engineering design optimization where search spaces are very difficult to search and evaluating fitness using external simulators can be quite time consuming. GADO maintains a population of potential designs (standard cell designs in our case). The design of the schematic and the optimization of the layout happen in parallel at both logical (schematic/connectivity) and physical (layout) levels as opposed to traditional methods.

Object Type

Stretch

Orientation

Figure 1: Coding Scheme

An object is a member of a pre-defined set of building blocks including various types of transistors, piece of polysilicon, piece of ploycontact etc. Figure 2 is a snapshot of a MAGIC file with all the blocks placed in a single file.

Figure 2: Building Blocks

It may be noted that there are 15 object types that consist of symmetrical and asymmetrical transistors of different types (single, dual and triple). Three other blocks are pieces of polycontact, polysilicon and metal1 (extreme right, top to bottom in Figure 2). The user may easily add other building blocks as and when required.

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Each object is further defined by its type, X and Y coordinates, stretch and orientation (Figure 1). Cell limits refer to the size of the grid of the maximum allowable cell size (as defined by the user). This forces the GA to place components only within the grid. The orientation refers to a number (0, 1, 2 or 3) that decides the rotation applied to a block (0, 180, 90 or 270 degrees respectively). The stretch factor is a number corresponding to the number of units by which a block is scaled. The scaling is evenly distributed along the direction of orientation. The maximum scale is limited by the maximum allowable cell size X and Y refer to the coordinates of the center of the object and are thus also constrained to be within the maximum allowable cell area.

C. Fitness Function The fitness function checks a candidate design against a list of constraints and penalizes it for every violation encountered. The penalty values vary for each constraint depending on their importance. This way the GA fixes the most serious violations first and progresses to make smaller fixes. In the first phase the GA tries to weed out incorrect designs such as those with overlapping transistors. After succeeding in that venture it goes on to check connectivity of individual transistors and tries to encourage connections (more details ahead). Simultaneously, the design rule checker is invoked so that the GA tries to minimize both design rule violations as well as broken connections. After the GA has succeeded in creating designs with no broken connections it passes on to the next phase where the design rule check is made in conjunction with a circuit simulation. In this stage, the GA is trying to simultaneously satisfy the requirements of zero design errors and zero simulation errors. Once the GA has come up with a working circuit it proceeds to optimize the design for a given criterion (i.e. search in the space of correct designs), which could be minimizing area, delay or power dissipation. One of the most challenging aspects of the project was developing the transistor connectivity check module that encourages broken connections. A directed graph was used to capture connectivity information. To illustrate the concept of nodes and connections here is an example of a circuit layout abutted by the graph used to capture connectivity information:

Figure 3: Example Cells. (b) shows the same object stretched and turned

TABLE 2 PARAMETERS IN THE CODING SCHEME PARAMETER VALUE Fig 3 (a) Fig 3 (b) Object Type 1-15 11 11 Orientation 0-3 0 2 Stretch Factor Cell limits 0 5 X Cell limits 0 15 Y Cell limits 0 14

Table 2 summarizes the parameters of each object (column 1), the range of values that they may have (column 2) and illustrates the values corresponding to the objects shown in figures 3 (a) and (b). Note the effects of moving, stretching and rotating the same object. Figure 3 also demonstrates the use of templates. The 3 pieces of metal and the 4 labels (Vdd, Gnd, in and out) are part of a user-defined template over which the other objects are superimposed. A repair method was used to reduce the effects of aliasing. The objects in the string (chromosome) are sorted before crossover and mutation in a way that maps the order of objects in the cell.

Figure 4: A cell and its connectivity graph

The graph is used to penalize nodes that do not influence nodes that they ought to. We also need to formally define influence (arrows in the graph). Node A influences node B if there is (1) a direct electrical connection, or (2) a uni-directional electrical influence such as the control of the gate over the source and drain of a transistor. In Figure 5, nodes 1 and 2 influence

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one another by property (1); the bi-directional nature of influence in represented by solid lines. Also nodes 3 and 4 exhibit property (2); an arrow going from node 4 to node 3 represents the unidirectional nature of influence. It may be also noted that all labels were classified as inputs or outputs. Vdd and Gnd were treated as inputs. The rules that the influence check tests are: 1. 2. 3. 4. 5. None of the labels should be shorted Every input must influence at least one output Every output must be influenced by at least one input Every transistor gate must be influenced by at least one input Both source/drain terminals of a transistor must be influenced by at least one input or influence at least one output

Thus the layout in Figure 4 violates rules 2 and 4 above as may be seen in the graph. Let us consider another case where there is a violation, say in rule 3 above (not shown in figures). It is more useful to know how bad the violation is than a binary yes/no. This is accomplished by a distance check function that in case of a violation in rule 3 will do a breadth-first graph traversal starting from the floating output to determine all the nodes that may influence it creating an O-list. Similarly another graph traversal is made from each input to create their respective I-list of nodes that they influence. Once created, the distance function finds the shortest Manhattan distance between nodes in the I-lists and the nodes in the O-list and returns a penalty based on this distance. Note that many of these nodes may be in different layers. We use a look up table with values preset by a domain expert to calculate distances between nodes in different layers. Since designs in which a node in the I-lists is closer to a node in the O-lists receive lower penalties, the GA favors these designs and in conjunction with the other 4 rules above it has the holistic effect of encouraging connections between inputs and outputs via transistors without shorting inputs. This idea lies at the heart of the GAs success. To summarize: If you have some terminal that is not being influenced by any other terminal, we want to know how close it is to some terminal that can influence it. (terminals include labels and transistor terminals) The idea that information about the degree of the violation is more useful than just knowing whether there is a violation is another key ingredient to the GAs success and is used in the next 2 stages too. In the design rule check stage, a script is fed to MAGIC and the number of tiles (MAGIC draws tiles to show regions violating design rule errors; more tiles imply more errors) that are involved in the design rule errors is summed to arrive at a penalty. In the circuit simulation step, a SPICE simulation is made and a penalty is arrived at by dividing the total number of entries in the truth table simulated incorrectly divided by the total number of entries in the truth table.

D. Smart Diversity Function A distance function takes 2 designs as arguments and returns a measure of `how different" they are. This is used by a diversity module within GADO to weed out duplicates and designs that are very similar in order to encourage diversity in the population of potential designs. This helps the GA maintain a much thorough representation of the search space as well as allowing it to escape from local optima. In the earlier runs, while the fitness function was under construction a simple diversity function based on the Euclidean distance between 2 strings was used. An example with 2 hypothetical strings of 4 alleles (numbers in the string) each illustrates the idea: e.g. If the 2 individuals are A and B: A: 11 3 0 1 B: 9 3 1 0 The 4-dimensional Euclidean distance is calculated as the square root of (Ai Bi) 2 where i =1 to 4. _____________________________ = (11-9) 2 + (3-3) 2 + (0-1) 2 + (1-0) 2 = 6 The problem with this simple distance function is that it is not sensitive to the objects in the design since distance between each allele is calculated on the same scale. After preliminary success with the GA, we set out to fix this. The idea was to use a weighted scheme corresponding to what each allele represented and how distinguishing a feature it was in the context of the entire circuit. In the above example the sum might be: Sum = a|11-9| + b|3-3| + c|0-1| + d|1-0| where a, b, c and d are weights that reflect the importance of each allele in its contribution to the total distance between the given designs. The | | brackets here represent the absolute difference. This is the scheme we ended up using. Our scheme still does not fix the problem of apparent diversity. There are many physical realizations of a given transistor schematic each of which may have its own unique sequence of alleles. The function needs to be smart enough to say that these designs are more similar than designs that may have smaller distances but represent a totally different schematic. This is because in this domain, small changes in the location, size or orientation of the objects can cause large changes in their logical equivalents. Such a function would have to be schematic sensitive by computing the distance between the graphs of the schematics. We are now investigating this and also a different representation scheme [7] that can make distance computations easier. III.
EXPERIMENTAL RESULTS

These are the results from our attempts to build an inverter. Figures 5,6 and 7 show MAGIC layout editor screenshots of the inverters designed by the GA for three different templates with different label configurations. The complete snapshots from the evolution of these circuits may be viewed at our website [19].

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The process we followed to test these templates was to (1) plan a template (2) hand design the inverter using the templateand (3) modify the template if necessary to eliminate design rule errors. Once we were confident that a handcrafted solution existed for a given template, the GA was designated the task of finding it. Figures 8 and 9 illustrate the highlights in the evolution of the design of the inverter shown in Figure 5.

evolution of the cell. The run lasted 3 hours (the next section discusses how this may be reduced) on a 1.2 GHz machine. The first snapshot (Figure 8a) is that of a random placement of 6 (or as defined by user) objects from the building-block library (Figure 2). Subsequent snapshots show the improvement of the circuit over time. The GA first weeds out overlapping transistors seen in Figure 8b and arrives at a simple design with a few objects and a lot of broken connections (Figure 8c). It then attempts to fix these connections by reducing the distance between nodes that could influence one another (Figures 9d9g). On succeeding to fix all connections (Figure 9g) it attacks the final hurdle of coming up with a working circuit with zero design rule errors (Figure 8h). It then goes on to minimize the area (user defined criterion) occupied by this circuit and arrives at the final design shown in Figure 5.

Figure 5: An Inverter Cell

Figure 6: An Inverter cell with arbitrary label placement (1)

Figure 8: Highlights in the Evolution of the Cell (1)

IV.

CONCLUSION

An evolutionary approach (using GADO, a genetic algorithm) for standard cell design automation was proposed.
Figure 7: An Inverter cell with arbitrary label placement (2)

The C code ran on a Linux box over several iterations. As the GA progressed it placed the designs that were best so far (individuals that were evaluated with the highest fitness) on our web page [19] so that we could monitor its progress. The screenshots you see here are some of the highlights in the
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A. LIMITATIONS The GA can currently design cells with a small number of transistors. The search space becomes intractable as more and more objects are added. Plenty of optimizations can also be made within GADO. A better representation scheme is needed to tackle the combinatorial challenges of cells such as a full adder. As may be seen at our website, all runs of the GA do not converge at the best design. Different random

seeds that the GA started with would converge at different designs. This means that the GA does not always find the global optima. B. ADVANTAGES GADO explores the space of all possible configurations (of a set of building blocks) given only a behavioral description of the circuit. The search space includes all possible electrical connectivity and layout and is accomplished in a reasonable time frame for an inverter (3 hours on a single processor). The same result may be obtained in a fraction of the time by adding multiple processors since genetic algorithms are easily implemented on parallel architectures or a network of workstations [5,6,12]. Figure 10 summarizes our architecture implemented on a single processor. This approach has the flexibility of generating cells on the fly to address the ad-hoc constraints faced by the designer when she is considering a candidate design in a larger context such as choosing a cell. This was demonstrated by the design of inverters with arbitrary label placements. C. FUTURE WORK We are working on an alternative representation in an attempt to make the search space more tractable for more complex cells such as a full adder. We are also working on a better distance function that will avoid problems due to aliasing and apparent diversity. We also plan to test the algorithm on a network of workstations to reduce the run time of the algorithm and compare it to other approaches such as simulated annealing.

V.
[1] [2] [3] [4] [5]

REFERENCES

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[10]

[11] [12] [13] [14] [15] [16] [17] [18] [19]

M. Lefebvre, D. Marple and C. Sechen, "The Future of Custom Cell Generation in Physical Synthesis", IEEE 34th Design Automation Conference, July 1997, pp. 446-451. J. Burns and J. Feldman, C5M A Control Logic Layout Synthesis System for High-Performance Microprocessors, IEEE Trans. On CAD, 17(1), January 1998, pp. 14-23. B. Bishop, K. Rasheed and A. Bahuman, VLSI Standard Cell Design Using Genetic Algorithms", 39th Annual ACM Southeast Conference, March 2001,pp. K. Rasheed, GADO A Genetic Algorithm for Design Optimization, PhD. Thesis. http://www.cs.uga.edu/~khaled Goodman E. D., An Introduction to GALOPPS the Genetic Algorithm Optimized for Portability and Parallelism System, CASE Center Technical Report #940401, Michigan State University, 1994, pp. 58. Gerald Carrier, Doyle Knight, Khaled Rasheed, and Xavier Montazel. "Multi-criteria Design Optimization of a Two dimensional Supersonic Inlet", 39th AIAA Aerospace Sciences Meeting and Exhibit, 2001. H. Murata, K. Fujiyoushi, S. Nakatake, and Y. Kajitani, Rectangle packing based module placement, Proceedings IEEE International Conference on Computer-Aided Design, pp. 472--479, 1995. D.G. Baltus, T. Varga and R.C. Armstrong , Developing a concurrent methodology for standard-cell library generation, IEEE 34th Design Automation Conference, July 1997, pp. 333-336. MA Riepe and KA Sakallah, "Transistor Level Micro-Placement and Routing for Two-Dimensional Digital VLSI Cell Synthesis", International Symposium on Physical Design, April 12-14, 1999, pp. 74-81. K. Rasheed and B. Davison, Effect of Global Parallelism on the Behavior of a Steady State Genetic Algorithm for Design Optimization", Congress on Evolutionary Computation, 1999, pp. 534--541. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout, Chichester, England: Wiley 1990. P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design, Layout & Test Automation, Prentice Hall, 1999, pp. 264-265. J. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 1996. D.E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Reading, MA:Addison-Wesley, 1989. C. Edwards, EDA Vendors Rethink Standard-Cell Libraries, Electronics Times, June 2000. D. Pietromonaco, Automating Cost-Effective Library Creation, Integrated System Design, November 2000. http://www.research.compaq.com/wrl/projects/magic/ http://bwrc.eecs.berkeley.edu/Classes/IcBook/SPICE http://james.cs.uga.edu

Figure 10: Architecture Figure 9: Highlights in the Evolution of the Cell (2)

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