Workpackage 4: Optimization

One of the major activities of COMSON is to contribute to scientic innovation by optimizing a realistic, medium size coupled problem of industrial relevance. This implies that optimization will be done in a multiple domain space with a large number of design objectives and restrictions, and will work in a very complex parameter space. As far as manufacturability requirements are concerned, optimization will have to deal with discrete as well as continuous variables. In COMSON, academia and industry join their efforts to validate the scientic results by addressing industrys problems such as the Power MOSFET design and future coupled circuit problems. New issues are arising in the design and fabrication of power devices due to the industries high demand for high-frequency power devices. During unclamped inductive switching turn-off, the current focusing [1,2] could compromise the integrity of the entire device. The optimization of a power MOSFET layout is aimed to reduce the current density overshoots, referred to as hotspots. Moreover, changing the geometry within the layout of the device has proven reductions in hotspot areas. Therefore, a CAD tool in its preliminary stages is in development using sophisticated optimization evolutionary algorithms to resolve this problem. The optimization framework is comprised of genetic and non genetic algorithms fully integrated within the innovative PAN (PowerMos Analyzer) modeling ow. As required by the COMSON methodology, the rst testcase is the benchmark example, a High-Voltage discrete silicon power MOSFET.

Distributed Modelling Approach

ly one metal layer which helps keeps fabrication costs low. Therefore, both gate and source contacts are on top of the wafer where bond wires are soldered. Since the source contacts cover most of the die surface, the internal gate connections must be shaped using a less conductive poly-silicon layer beneath the metal connected to the gate through branching metal ngers [4,5]. Hence, each row and single cell is powered by a gate metal path that branches from the gate pad across the entire device. At high switching frequencies the time required by the gate signal to reach the farthest elementary cell may be comparable to the switching times of the input signal. Therefore, this provides fast switching times for cells nearest to the gate pad and increasing delays for those located furthest away. The fast turn off for only portions of the device forces the remainder to drive large amounts of current during switching [3]. The result is a dramatic current density increase in the slowest parts of the device causing the hot spots. The internal behavior of power devices during switching transient at the elementary cell level in terms of carried currents or power developed by the elementary cells is not a task that is commonly performed or done by the commercial customer. A Power MOS Analyzer1 (PAN) has been developed to analyze, at the cell level, the behavior of each single cell composing the entire layout. The tool can extract from a device layout a 2D spice-like netlist that includes the active area modeling and parasitics. This netlist represents the whole device which can be simulated with a spice-like simulator for the given working condition. It also evaluates different electrical signals such as drain current, gate-source voltage and temperature information supplying a 2D map, waveforms and numerical data for easier evaluation of the results. The data results produced by the tool could be postprocessed and supplied as input for an optimization platform for integrated circuits based on optimization algorithms such as evolutionary algorithms that is able to automatically change the layout information in order to reproduce new optimal results. Hence, the integration of the optimization platform into the PAN ow provides a new innovated technique that allows the automatic reduction or virtually the elimination of the issues arising in high switching power devices.

Evolutionary algorithms
The term evolutionary algorithm stands for a class of stochastic optimization methods that simulate the process of natural evolution. Their origins can be traced back to the late 1950s, and since the 1970s sever-

A custom tool developed by the R&D department at ST Microelectronics

al evolutionary methodologies, such as genetic algorithms, evolutionary programming and evolution strategies, have been proposed. Evolutionary Algorithms (EAs) are closely linked to AI techniques, especially search procedures. EAs can be dened as populationbased stochastic generate-and-test algorithms working on a set of candidate solutions, which is subsequently modied by the two basic mechanisms: selection and variation. While selection operator mimics the competition for reproduction and resources among living beings, variation operator imitates the natural capability of creating new living beings by means of recombination and mutation. Although the underlying mechanisms are simple, these algorithms have proven themselves as a general, robust and powerful search mechanism. In particular, they possess several characteristics that are desirable for problems involving multiple conicting objectives and intractably-large and highlycomplex search spaces [9]. As a result, numerous algorithmic variants have been proposed and applied to various problem domains since the mid 1980s. Classical optimization methods use a point-to-point approach, where one solution in each iteration is modied to a different (hopefully better) solution, the outcome is a single optimized solution in a single simulation runs. One of the most striking differences to classical optimization algorithms is that EAs, use a population of solutions each iteration, instead of a single solution, the outcome is a population of solutions. An EA, hence, can be used to capture multiple optimal solutions in its nal population [8, 10]. In evolutionary computing there is no restriction on the objective (tness) function, it can be non-differentiable or even discontinuous, there is no need to know the exact form of the objective function, and simulation can be used to derive a tness value. The initial population does not have to be generated randomly; it can be initialized by means ad hoc population. The representation of candidate solutions does not have to be binary coding (integer, real, discrete, mixed, etc.). Each individual of the population is a candidate solution encoding integer/discrete/continuous variables [7]. One difcult matter in constrained optimization problems is nding a feasible set. In the rst steps it could represent a true challenge. One of the possible reasons is that feasible regions could be a very small subset in the search space. This method uses binary tournament selection, that is, two individuals of the population are chosen and compared and the ttest is copied in the following population. When a problem presents constraints, two solutions can be feasible or unfeasible. Just one of the following cases is possible:

(i) both are feasible; (ii) one solution is feasible and the other is not; (iii) both are unfeasible. Case (i) is solved using a Pareto dominance relation which takes in account the constraint violation. In case (ii) only the feasible solution is chosen and in case (iii) a penalty function is used. The optimization process ends when a maximum number of runs is reached. Based on the above considerations, the faced optimization problem can in general be treated as a constrained optimization problem dened in a mixed continuous/discrete domain. In addition, the large size and high complexity of the search domain of realworld problems makes global optimization a mandatory choice while limiting the use of local optimization to post-global-optimization renement purposes. This idea has fostered the development of algorithms and techniques that make use of random-based search to avoid local minima trapping and preserve diversity in the set of feasible solutions. Introducing a random component in the search process also increases algorithm exibility because no assumptions have to be made on the continuity, differentiability, or convexity of objective and constraint functions that are necessary for most deterministic approaches. Due to the complexity of state-of-the-art analog circuits, global and/or local optimization algorithms have to be extensively employed to nd a feasible solution (or a set of feasible solutions) that satises all objectives and constraints required by a given application.

Optimization ow

The methodology is based on the possibility to modify the structure of the devices layout simply by modifying the contents of the matrix stored in an ASCII le. The matrix before being used in the optimization ow must be translated into a text description format through a custom language named DES based on a series of parameters that describes the matrix contents in an exhaustive way. 2

vative CAD tools that allows investigating problematic until now little afforded due to the lack of means. These innovated techniques can be applied to new industrial multi coupled test cases with modications and reuse of optimization algorithms and integrated into new design ows. The designed evolutionary algorithm was shown to produce acceptable solutions in most cases, where classical techniques failed. The above procedure reveals that apart of improving simulation techniques (like new coupled simulation techniques) in industry also improving the design ow is important. For future optimized circuits methodologies, one may need technique and algorithms developed from other work packages, for example, Model Order Reduction (MOR) functionality. This is referring to the COMSON work package 3 example, the highfrequency phase-locked-loop (PLL) design. MOR may be performed before circuit optimization in order to provide a reduced circuit which can reduce circuit simulation computation run time and (hopefully) also make optimization simpler (clearly this will need parameterized MOR). This shows that several modules in the COMSON Demonstrator Platform should be available as a function that can be called separately. Depending on the optimization techniques also other DP-facilities may have to become separately available.

Figure 1: IO Optimization Flow That DES2 le, automatically created by custom software from the matrix, allows a better denition of the constraints that the optimizer must take into account. For each parameters or constraints it is possible to setup a minimum and maximum range of variation within which to nd a better solution in terms of layout topology. The optimization ow works as follows and shown in Figure 1. Firstly, the designer has to write the layout constrains (Fig 1: DES Constr.) in terms of ranges for the parameters in DES format. Once this operation is completed, a reference "Starting Layout" is taken as input and translated in DES format (Layout > Pan > Matrix > MTX2DES > DES > Matrix). Both, DES constraints and DES matrix description are taken as input by the Optimization Framework in order to produce a population of netlists. The generated netlists will be simulated with a spice-like simulator and the nal results will be stored and evaluated. Following the genetics algorithms criterions described in the previous paragraph, when the simulation of the generated population is completed, the better solution found is given as optimum. The better solution will be delivered in DES le format, then converted into matrix format, and hence in an optimized layout view.3

References
[1] A. Consoli, F. Gennaro, A Testa, G. Consentino, F. Frisina, R. Letor, and A. Magri. Thermal instability of low voltage power-mosfets. IEEE Trans. on Power Electr, 15:575581, 2000. [2] R. Kraus and H.J. Mattausch. Status and trends of power semiconductor device models for circuit simulation. IEEE Trans. on Power Electr, 13:452 465, 1998. [3] T. Biondi, G. Greco, G. Bazzano, and S. Rinaudo. Analysis of the internal current distribution in power mosfets operated at high switching frequency. Proceedings of MSED,Workshop on Modeling and Simulation of Electron Devices, Pisa, Italy, 15:45, July 2005. [4] T. Biondi, G. Greco, G. Bazzano, and S. Rinaudo. Effect of layout parasitics on the current distribu-

Conclusion
An innovative methodology (design ow) based on evolutionary computing for the power MOSFET design aimed to improve robustness and performances has been developed. This methodology opens new spaces in power device designing giving to the designers new inno2 3

Acronym name used to describe description of the matrix. All the software tools mentioned in this ow, with the exception of Eldo simulator[6], have been developed and are property of STMicroelectronics.

tion of power mosfets operated at high switching frequency. Journal of Computational Electronics, 5(2-3):149153, July 2006. [5] T. Biondi, G. Greco, G. Bazzano, and S. Rinaudo. Method for modeling large-area transistor devices, and computer program product therefore. U.S. Patent N. 11/770,578 deposited in, June 2007. [6] Eldo users manual. Mentor Graphics Corporation. [7] V. Cutello, G. Narzisi, G. Nicosia, and M. Pavone. Real coded clonal selection algorithm for global numerical optimization using a new inversely proportional hypermutation operator. SAC 2006, ACM Press, pages 2:950954, 2006. [8] A. M. Anile, V. Cutello, G. Nicosia, R. Rascun, and S. Spinella. Comparison among evolutionary algorithms and classical optimization methods for circuit designproblems. IEEE Congress on Evo. Comp., CEC 2005, IEEE Press, 1:765772, 2005. [9] T. Biondi, V. Cutello C. Ciccazzo, S. DAntona, G. Nicosia, and S. Spinella. Multi-objective evolutionary algorithms and pattern search methods for circuit design problems. J. of Universal Computer Science, 12(4):432449, 2006. [10] V. Cutello, G. Nicosia, R. Rascun, and S. Spinella. Inductor circuit and two-stage operational transconductance amplier by means evolutionary and classical algorithms. Int. J. of Comp. Sc. and Engi., 1(2/3):158169, 2006. [11] T. Biondi, G. Greco, G. Bazzano, S. Rinaudo, M.C. Allia, and S.F. Liotta. Distributed modeling of layout parasites in large-area high-speed silicon power devices. IEEE Transactions on Power Electronics, 22(5), 2007. Contacts: Franco Fiorante, Giuliana Gangemi, Salvatore Rinaudo STMicroelectronics, R&D CAD and Design Solution Group Stradale Primosole 50, 95121, Catania, Italy
[franco.fiorante, guiliana.gangemi, salvatore.rinaudo]@st.com

Giuseppe Nicosia, Giovanni Stracquadanio Department of Matematics and Computer Science University of Catania Viale A. Doria 6, 95125, Catania, Italy
[nicosia, stracquadanio]@dmi.unict.it