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    Pseudo-Instructions: Assembler Psedudo-Instruction

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    Yen Binh
    Pseudo-instructions are assembly instructions that do not directly correspond to machine language instructions. The assembler translates pseudo-instructions into one or more machine language instructions. Examples of MIPS pseudo-instructions include move to copy registers and slt to set a register to 1 if one value is less than another. Pseudo-instructions allow MIPS assembly to have a richer instruction set than the underlying machine language.

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    Pseudo-Instructions: Assembler Psedudo-Instruction

    Uploaded by

    Yen Binh
    197 views9 pages
    Pseudo-instructions are assembly instructions that do not directly correspond to machine language instructions. The assembler translates pseudo-instructions into one or more machine language instructions. Examples of MIPS pseudo-instructions include move to copy registers and slt to set a register to 1 if one value is less than another. Pseudo-instructions allow MIPS assembly to have a richer instruction set than the underlying machine language.

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    2-2-10

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    Pseudo-instructions are assembly instructions that do not directly correspond to machine language instructions. The assembler translates pseudo-instructions into one or more machine language instructions. Examples of MIPS pseudo-instructions include move to copy registers and slt to set a register to 1 if one value is less than another. Pseudo-instructions allow MIPS assembly to have a richer instruction set than the underlying machine language.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    197 views9 pages

    Pseudo-Instructions: Assembler Psedudo-Instruction

    Uploaded by

    Yen Binh
    Pseudo-instructions are assembly instructions that do not directly correspond to machine language instructions. The assembler translates pseudo-instructions into one or more machine language instructions. Examples of MIPS pseudo-instructions include move to copy registers and slt to set a register to 1 if one value is less than another. Pseudo-instructions allow MIPS assembly to have a richer instruction set than the underlying machine language.

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    Attribution Non-Commercial (BY-NC)
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    of 9

    Pseudo-instructions

    These are simple assembly language instructions that do not have a direct machine language equivalent. During assembly, the assembler translates each psedudoinstruction into one or more machine language instructions.

    Example move $t0, $t1 # $t0 ! $t1

    The assembler will translate it to add $t0, $zer0, $t1 We will see more of these soon.

    slt $t0, $s0, $s1 bne $t0, $zero, label

    # if $s0 < $s1 then $t0 =1 else $t0 = 0 # if $t0 " 0 then goto label

    Pseudo-instructions give MIPS a richer set of assembly language instructions.

    Loading a 32-bit constant into a register

    Quite often, we would like to load a constant value into a register (or a memory location)

    lui $s0, 42

    # load upper-half immediate

    ori $s0, $s0, 18 # (one can also use andi)

    What is the end result?

    Compiling a switch statement


    switch (k) { case 0: case 1: case 2: case 3: } f = i + j; break; f = g + h; break; f = g h; break; f = i j; break;

    New instruction

    slt $s1, $s2, $s3

    (set less than)

    (if $s2 < $s3 then set $s1 to 1)

    Assume, $s0-$s5 contain f, g, h, i, j, k. Let $t2 contain 4.

    slt $t3, $s5, $zero bne $t3, $zero, Exit slt $t3, $s5, $t2 beq $t3, $zero, Exit

    # if k < 0 then $t3 = 1 else $t3=0 # if k<0 then Exit # if k<4 then $t3 = 1 else $t3=0 # if k# 4 the Exit

    What next? Jump to the right case!

    32-bit address L0 32-bit address L1 32-bit address L2 32-bit address L3

    Base address of the jumptable

    jumptable register $t4

    L0

    f=i+j J Exit

    L1

    f = g+h j Exit

    Exit

    MEMORY

    Here is the remainder of the program;

    add $t1, $s5, $s5 add $t1, $t1, $t1 add $t1, $t1, $t4 lw $t0, 0($t1) jr $t0 L0: add $s0, $s3, $s4 J Exit L1: add $s0, $s1, $s2 J Exit L2: sub $s0, $s1, $s2 J Exit L3: sub $s0, $s3, $s4 Exit: <next instruction>

    # t1 = 2*k # t1 = 4*k # t1 = base address + 4*k # load the address pointed # by t1 into register t0 # jump to addr pointed by t0 #f=i+j

    # f = g+h

    # f = g-h

    #f=i-j

    The instruction formats for jump and branch

    10000

    is represented as

    2500

    6-bits

    26 bits

    This is the J-type format of MIPS instructions.

    Conditional branch is represented using I-type format:

    bne $s0, $s1, Label

    is represented as

    16

    17

    16-bit offset

    Current PC + (4 * offset) determines the branch target Label

    This is called PC-relative addressing.

    Revisiting machine language of MIPS


    # starts from 80000 Loop: add $t1, $s3, $s3 add $t1, $t1, $t1 add $t1, $t1, $s6 lw $t0, 0($t1)

    What does this program do?

    bne $t0, $s5, Exit add $s3, $s3, $s4 j Exit: 6 80000 80004 80008 80012 80016 80020 80024 80028 0 0 0 35 5 0 2 5 19 9 9 9 8 19 5 19 9 22 8 21 20 19 5 9 9 9 5 0 0 0 0 2 (why?) 0 32 6 32 32 32 Loop

    Machine language version


    R-type R-type R-type I-type I-type R-type J-type

    20000 (why?)

    Addressing Modes

    What are the different ways to access an operand?

    Register addressing Operand is in register add $s1, $s2, $s3 means $s1 ! $s2 + $s3

    Base addressing Operand is in memory. The address is the sum of a register and a constant. lw $s1, 32($s3) means $s1 ! M[s3 + 32]

    As special cases, you can implement

    Direct addressing

    $s1 ! M[32]

    Indirect addressing

    $s1 ! M[s3]

    Which helps implement pointers.

    Immediate addressing The operand is a constant. How can you execute $s1 ! 7?

    addi $s1, $zero, 7 means $s1 ! 0 + 7 (add immediate, uses the I-type format)

    PC-relative addressing The operand address = PC + an offset Implements position-independent codes. A small offset is adequate for short loops.

    Pseudo-direct addressing Used in the J format. The target address is the concatenation of the 4 MSBs of the PC with the 28-bit offset. This is a minor variation of the PC-relative addressing format.

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