International Journal of Advanced Research Research in Engineering International Journal of Advanced in Engineering and Technology (IJARET) ISSN 0976

6480(Print), ISSN 0976 6499(Online) Volume 1, Number 1, May - June (2010), IAEME and Technology (IJARET), ISSN 0976 6480(Print) ISSN 0976 6499(Online) Volume 1 Number 1, May - June (2010), pp. 96-104 IAEME IAEME, http://www.iaeme.com/ijaret.html

IJARET

COMPARISON OF 100 TORR AND 200 TORR BPSG LAYER DEPOSITED USING SUB ATMOSPHERIC CHEMICAL VAPOUR DEPOSITION (SACVD) PROCESS.
Jagadeesha T Department of Mechanical Engineering National Institute of Technology,Calicut E-Mail: Jagdishsg@nitc.ac.in Louis Kim Thin Film Division Chartered Semiconductor Manufacturing Woodlands, Singpaore Thammaiah Gowda Department of Industrial & Production Engineering AIT,Chikmagalur

ABSTRACT:
Borophosphosilicate glass (BPSG) is most commonly used as poly-metal interlevel dielectric film. BPSG layer is obtained by doping silicon dioxide with phosphorous and boron. Phosphorous can trap mobile ions. Silicon dioxide with higher phosphorus concentration will facilitate the reflow smoothing but is detrimental to the metallization, because of aluminium corrosion. Adding boron can reduce the reflow temperature further. Present work focuses on a new low pressure BPSG process that can be used for Flash memory and Logic devices. It is shown that films with phosphorus and boron concentrations in the range of 1.85-9.15 elemental wt% are deposited with film thickness 6000 /14000 BPSG and 100 Torr process has been found to achieve more stable film thickness. Decreasing the deposition pressure from 200 to 100 Torr results in a 50% increase in the deposition rate of twin-wafer SACVD BPSG and has zero effect on film properties. Throughput has been improved by 20% on SACVD PMD BPSG application.

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International Journal of Advanced Research in Engineering and Technology (IJARET) ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 1, Number 1, May - June (2010), IAEME

Keywords: BPSG, PSG, Low pressure BPSG, SACVD

1. INTRODUCTION
Advances in integrated circuit fabrication technology over the past two decades have resulted in integrated circuits with smaller device dimensions, larger area and complexity. Many integrated circuits now have features, such as traces or trenches that are significantly less than a micron across. While the reduction in feature size has allowed higher device density, more complex circuits, lower operating power consumption and lower cost, the smaller geometries have also given rise to new problems, or have resurrected problems that were once solved for larger geometries (Haruhisa Kinoshita et al., 2004). One example of a manufacturing challenge presented by submicron devices is the ability to completely fill a narrow trench in a void-free manner while keeping the thermal budget of the trench-filling process at a minimum. For example, in order to meet the manufacturing requirements of 0.18 micron geometry devices and below, a BPSG layer may be required to fill 0.1 micron wide and narrower gaps having an aspect ratio of up to 6:1. At the same time, these manufacturing requirements demands minimum thermal budget (Arbinda Das et al., 2008). Borophosphosilicate glass (BPSG) is used in the semiconductor industry as separation layers between the polysilicon gate/interconnect layer and the first metal layer of MOS transistors. Such a separation layer is often referred to as pre-metal dielectric (PMD) layer because it is deposited before metal layers. PMD is used to electrically isolate portions of the first deposited metal layer from the semiconductor substrate. It is important for PMD layers to have good planarization and gap-fill characteristics (Chi Wen Liu et al., 1995). BPSG deposition methods have been developed to meet these characteristics and often include planarizing of the layer by heating it above its reflow temperature so that it flows as a liquid. The reflow process enables the BPSG to fill trenches of small width with high-aspect ratio (Werner K et al., 1991). Osorio et al. (1993) have demonstrated that the heating necessary to reflow a BPSG layer can be achieved using either the rapid thermal pulse (RTP) method or a conventional furnace in either a dry (e.g., N2 or O2) or wet (e.g., steam H2 /O2) ambient. Standard BPSG films

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International Journal of Advanced Research in Engineering and Technology (IJARET) ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 1, Number 1, May - June (2010), IAEME

are formed by introducing a phosphorus-containing source and a boron-containing source into a processing chamber along with silicon-and oxygen-containing sources. Triethylphosphate (TEPO), triethylphosphite (TEPi), trimethylphosphate (TMOP), trimethylphosphite (TMPi), and similar compounds contain phosphorus as dopant constituent. Similarly, Trietbylborate (TEB), trimethylborate (TMB), and similar compounds contain boron as dopant constituent. Figure 1 shows the device application of BPSG layer.

Figure 1 Device application of BPSG layer In general, doped oxides used for the reflow process contain 6 to 9 wt % phosphorus (Adam et al., 1981). Silicon dioxide with higher phosphorous concentration will facilitate the reflow smoothing but is detrimental to the metallization, because of aluminium corrosion. After the doped silicon oxide is deposited, a subsequent heating is necessary until the oxide softens and flows. In addition to the phosphorous concentration, the reflow morphology of the doped silicon dioxide can also be determined by heating temperature, heating time, heating rate, and heating ambient. Sometimes, boron dopants are added to the phosphorous doped silicon dioxide to further reduce the softening temperature by decreasing the glass viscosity (Levy and Nassau, 1981).

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International Journal of Advanced Research in Engineering and Technology (IJARET) ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 1, Number 1, May - June (2010), IAEME

2. EXPERIMENTAL DETAILS
Experimental work has been conducted using commercially available SACVD system known as ProducerTM. Figure 2 shows the Producer platform that combines the productivity benefits of twin wafer handling with the advantages of single wafer processing. Twin process chambers permit simultaneous processing of two wafers side by side in separate environments, resulting in ultra high productivity. Up to three twin chambers can be mounted on the platform, allowing for simultaneous processing of six wafers. The gas inlets, chamber pressure and pumping capability are shared within a twin chamber, providing reliability, ease of maintenance and reduced capital expenses. However; spacing, RF power and processing time can be optimized for the two chambers separately. Producer also utilizes remote plasma clean technology to address environmental concerns reduces wear on the process kit and also minimizes the processing time.

Figure 2 Producer Tool used for deposition process This work provides a new and improved process for filling small-width, highaspect ratio gaps with a BPSG layer. The present invention deposits a low pressure BPSG layer over a small-width, high-aspect ratio gap that requires filling with a dielectric material and reflows the layer in a rapid thermal pulse (RTP) furnace. It is shown that by changing the process pressure from standard 200 Torr to 100 Torr, deposition rate can be increased. The relation between the pressure versus deposition rate was first established

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International Journal of Advanced Research in Engineering and Technology (IJARET) ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 1, Number 1, May - June (2010), IAEME

using the producer tool equipped with PLIS (Precision Liquid Injection System).The effect of the other parameters were also studied and found that pressure had greater influence on the deposition rate and Figure 3 shows the other parameters considered and Figure 4 shows the effect of varying the pressure of process.

Figure 3 Process parameters studied to optimize the BPSG parameters

5000 Deposition Rate (A/min) Dep Rate (A/min) 4000 3000 2000 1000 0 50 70 100 150 200 250 300 Pressure (Torr)

Figure 4 Effect of pressure on deposition rate in BPSG process.

3. RESULTS AND DISCUSSION 3.1 Deposition rate

In order to improve device characteristics and to use the deposited dielectric and polysilicon films in various applications, the properties of these films are important. Deposition rate is a critical parameter which affects the throughput of wafers and is a good indicator of wafer fabrication units performance.Other parameters such as refractive index, film stress, dielectric strength, and leakage current , all significantly

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International Journal of Advanced Research in Engineering and Technology (IJARET) ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 1, Number 1, May - June (2010), IAEME

determine the film properties and even the applications of these deposited oxide films.The stress in silicon dioxide can change the film quality. Tensile stress in silicon dioxide may induce crack in the films. Stress in silcion dioxide depends on the deposition rate, deposition temperature , post annealing cycle, dopant concentration, film porosity, and water content. Hence, the processing of silicon dioxide should be carefully controlled. Table 1 shows the comparison between 100 Torr and 200 Torr processes. Process parameters indicated in the Table 1 are the average values of measurement taken over 240 wafers and for various technology nodes ranging from 0.13 micron to 0.1 micron devices. It is clear from the experimental results that 100 Torr gives lowest processing time. Range difference up to 500 is observed between chamber 1 and chamber 2. This difference is due to heater and other hardware settings. The range can be further reduced by fine tuning of hardware. 100 Torr 200 Torr Chamber Chamber Chamber 1 Chamber 1 2 2 Thickness (A) 14494 14538 14561 14523 Deposition rate (A/min) 3370 3391 2342 2336 Deposition time (s) 258 386 Range (A) 164 535 297 825 Uniformity (%) 0.80 0.65 1.29 0.96 Refractive Index 1.4849 1.4852 1.4888 1.4689 Stress as deposited MPa 46.8 43.9 42.1 39.1 Stress after RTA MPa -18 -19 -16 -19.6 B dopant Concentration (wt %) 1.83 1.84 1.87 1.86 B dopant Concentration (wt %) 0.04 0.07 0.06 0.05 range P dopant Concentration (wt %) 9.113 9.117 9.129 9.134 P dopant Concentration (wt %) 0.081 0.24 0.066 0.05 range Particle adder @0.2 <50 <50 <50 <50 micron for 6000 A thickness Throughput WPM 7875 6550 TEOS consumption mgm 850 850 TEPO consumption mgm 110 151 CMP removal rate (A/min) 3092 3109 3083 3113 WEER 19.35 19.13 19.78 19.75 Table 1 Comparison of 100 Torr and 200 Torr BPSG Processes Process parameter Unit

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3.2 Thicknes Range Improvement and TEPO usage reduction

The step coverage of deposited oxides can be improved by planarization. Lower thickness range is better for planarization operation like Chemical mechanical polishing. Summary of four important performance parameters are indicated in Table 2. Range mprovement of 54.2 % is seen for 100 Torr process compared to 200 Torr process. Wafer output from one twin chamber of Producer system for 100 Torr process is 7875 WPM (wafers per month) whereas, it is only 6550 WPM for 200 Torr process. In other words, cost per wafer using 100 Torr process is less compared to 200 Torr process. In addition, 100 Torr process gives 37.2% saving in TEPO usage. Process parameter Unit 100 Torr 200 Torr Saving/Improvement Deposition time (s) 49.6% 258 386 Thickness Range (A) 535 825 54.2% TEPO usage mgm 110 151 37.2% Wafer output WPM 7875 6550 20.1% Table 2 Comparison of 100 Torr and 200 Torr processes in terms of performance parameters.

3.3 Yield results

For use in ULSI devices the reliability of silicon dioxide is important. Hence , the time for failure and charge to breakdown under constant voltage or constant current stress are analysed to determine the oxide quality. The stress in silicon dioxide can change the film quality. Table 3 and Table 4 shows the yield results of the 100 Torr and 200 Torr processes. Experiments were conducted on different devices using different technology nodes. Yield results are quite comparable and the 100 Torr processes give better yield , which is desirable from the productivity point of view.It can also be observed that the 100 Torr processes are technology node and device independent. Lot ID Technology Node Device CP1(%) CP2(%) S1 1 D1 87 87.6 S2 1 D2 87.6 84.3 S3 1 D3 86.6 85.5 S4 1 D4 75.5 75.6 S5 2 D5 84.3 83.3 S6 2 D6 80.32 78.91 S7 2 D7 80.67 77.25 Table 3 Yield results obtained using 100 Torr for different technology nodes and devices 102

International Journal of Advanced Research in Engineering and Technology (IJARET) ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 1, Number 1, May - June (2010), IAEME

Lot ID S1 S2 S3 S4 S5 S6 S7

Technology Node Device CP1 (%) CP2(%) 1 D1 84.0 85.3 1 D2 61.8 60 1 D3 87.2 86.2 1 D4 74.8 74.7 2 D5 81.8 78.8 2 D6 75.4 72.9 2 D7 82.9 80.3

Table 4 Yield results obtained using 200 Torr for different technology nodes and devices

3.4 Gap filling capability

Figure 5 shows step coverage for 100 Torr BPSG and 200 Torr BPSG processes. Both processes give completely uniform or conformed step coverage. The film thickness along the walls and at the bottom of step are constant. As the reactants or reactive intermediates adsorb on the surface and then rapidly migrate along the surface before reaction, the resulting films will have a uniform surface concentration on the substrate and constant thickness. It is important to avoid cusp formation, it will be unfavorable for subsequent metal deposition.

Figure 5 Gap filling capability of 100 Torr BPSG layer and 200 Torr BPSG layers

4. CONCLUSIONS
In this paper, a new and improved process for filling small-width, high-aspect ratio gaps with a Borophosphosilicate glass (BPSG) layer has been presented. The present invention deposits low pressure BPSG layer over a small-width, high-aspect ratio gap that requires filling with a dielectric material and reflows the layer in a rapid thermal

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International Journal of Advanced Research in Engineering and Technology (IJARET) ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 1, Number 1, May - June (2010), IAEME

pulse (RTP) furnace. It is shown that by changing the process pressure from standard 200 Torr to 100 Torr, deposition rate can be increased. Range improvement of 54.2 % is seen for 100 Torr process compared to 200 Torr process. Cost per wafer using 100 Torr process is less compared to 200 Torr process due to high deposition rate and low TEPO usage.100 Torr process gives 37.2% saving in TEPO usage. Yield results and gap filling capabilities of both processes are comparable. The feasibility of the new fabrication process has been demonstrated with production wafers and found to be technology node and device independent.

REFERENCES
1. Adams A.C., et al., 1981. Planarization of Phosphorous doped silicon dioxide. J. Electrochemical Society. 128, 423-429 2. Arbinda Das, et al., 2008. Phosphorous doped as a pre-metal-dielectric for sub 50 nm technology nodes. J. of Microelectronic Engineering. 85, 2085-2088 3. Chi Wen Liu, et al., 1995. Chemical mechanical polishing of PSG and BPSG dielectric films: The effect of phosphorous and boron concentration, Journal of Thin Solid Films. Volume 270, 1995, Pages 607-611. 4. Haruhisa Kinoshita, et al., 2004. Chemical vapour deposition of SiO2 films by TEOS/O2 supermagnetron plasma, J. of Surface Engineering, Instrumentation and Vacuum Technology. 76, 19-22. 5. Levy, R.A., et al., 1986. Reflow mechanism of contact bias in VLSI processing. J. Electrochemical Society. 133, 1417-1428
6.

Surface

Osorio, S. P. A., et al., 1993. Effect of annealing on the composition of PECVD borosilicate and borophosphosilicate glasses, J. of applied surface science. 70, 772-776.

7. Voulgaris, et al., 2005. RF power effect on TEOS/O2 PECVD of silicon oxide thin films, J. of Surface coating and technology. 200, 351-354. 8. Werner K., et al., 1991. Simultaneous deposition and fusion flow planarization of borophosphosilicate glass in a new chemical vapour deposition reactor, J. of Thin Solid Films. 206, 64-69.

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