Datasheet 555
Datasheet 555
Datasheet 555
GENERAL DESCRIPTION The ALD555 timer is a high performance monolithic timing circuit built with advanced silicon gate CMOS technology. It offers the benefits of high input impedance, thereby allowing smaller timing capacitors and longer timing cycle; high speed, with typical cycle time of 500ns; low power dissipation for battery operated environment; reduced supply current spikes, allowing smaller and lower cost decoupling capacitors. It is capable of producing accurate time delays and oscillations in both monostable and astable operation. It operates in the one-shot (monostable) mode or 50% duty cycle free running oscillation mode with a single resistor and one capacitor. The inputs and outputs are fully compatible with CMOS, NMOS or TTL logic. There are three matched internal resistors (approximately 200K each) that set the threshold and trigger levels at two-thirds and one-third respectively of V +. These levels can be adjusted by using the control terminal (pin 5). When the trigger input is below the trigger level, the output is in the high state and sourcing 2mA. When threshold input is above the threshold level at the same time the trigger input is above the trigger level, the internal flip-flop is reset, the output goes to the low state and sinks up to 10mA. The reset input overrides all other inputs and when it is active (reset voltage less than 1V), the output is in the low state. FEATURES Functional equivalent to NE555 with greatly expanded high and low frequency ranges High speed, low power, monolithic CMOS technology Low supply current 100A typical Extremely low trigger, threshold and reset currents -- 1pA typical High speed operation -- 2MHz oscillation Low operating supply voltage 2 to 12V Operates in both monostable and astable modes Fixed 50% duty cycle or adjustable duty cycle CMOS, NMOS and TTL compatible input/output High discharge sinking current (80mA) Low supply current spikes ORDERING INFORMATION
Operating Temperature Range * -55C to +125C 0C to +70C 0C to +70C 8-Pin CERDIP Package ALD555 DA 8-Pin Small Outline Package (SOIC) ALD555 SA 8-Pin Plastic Dip Package ALD555 PA
APPLICATIONS
High speed one-shot (monostable)
pulse generation Precision timing Sequential timing Long delay timer Pulse width and pulse position modulation Missing pulse detector Frequency divider
PIN CONFIGURATION
1 2 3 4
8 7 6 5
BLOCK DIAGRAM
V+ (8)
RESET (4)
TRIGGER (2) R
GND (1)
1998 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089 -1706 Tel: (408) 747-1155 Fax: (408) 747-1286 http://www.aldinc.com
Symbol
V+ IS
Min
2
Typ
Max
12
Unit
V A
Test Conditions
100
180
Outputs Unloaded
terr t/T t/V+ VTH VTRIG ITRIG VRST IRST ITH VCONT VOL VOH tr tf IDL 3.273 0.4 3.273 1.607
1.0 10.0 0.1 3.333 1.667 .001 0.7 .001 .001 3.333 0.2
2.2
% ppm/C %/V
C = 0.1F RA = 1K RB = 1K
15 10 .01
30 20
VDISC
0.5 0.2
1.0 0.4
V V
fMAX
1.4
MHz
Notes:
Sample tested parameters. Consists of junction leakage currents with strong temperature dependence.
ALD555
9-2
TA = 25C
V+ = 12V
V+ = 5V V+ = 2V
TA = 25C
V+ = 2V V+ = 5V V+= 12V
0.02
0.05
0.1
0.2
0.5
1.0
10
20
30
40
100 F
( RA - 2RB )
1 mF
TA = 25C
+3 +2 +1 0 -1 -2 -3 -4
CAPACITANCE
10 F 1 F 100 nF 10 nF 1 nF 100 pF 0.1 1.0 10 100 1K 10K 100K 1M 10M 100M FREQUENCY (Hz)
10
10
0M
1M
10
10
0K
1K
10
12
TA = 25C
RA
CAPACITANCE
1K K 0K
10 F 1 F 100 nF 10 nF 1 nF 100 pF
10
10
M 0M
1G
1M
10
10
10s
100s
10
12
TIME DELAY
ALD555
9-3
100
OUTPUT SINK CURRENT (mA)
V+ = 5V
TYPICAL APPLICATIONS
1 2 R 3 V+ 4
8 0.1F 7 6 C 5
1 2 3 V+ 4
8 RA 7 RB 6 C 5 0.1F
8 R 7 6 C 5
0.1F
ALD555
9-4