Beyond CMOS computing

1. CMOS Scaling

Dmitri Nikonov
Thanks to Kelin Kuhn
Dmitri.e.nikonov@intel.com

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Outline

 Moore’s law = scaling

 Performance improvement with scaling
 Latest: tri-gate transistors
 Fundamental limits to scaling

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Moore’s Law

Transistor size becoming smaller

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Moore’s Law

Gordon Moore becoming wiser

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Scaling Falsifies Predictions

IEDM Plenary Session 1980 (Broers)

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How Far Scaling Went
1980 SRAM Cell: 1700 um2 22nm SRAM Cell: 0.092 um2

10000X

Small enough that a 2011 22nm SRAM cell is

dwarfed by a 1980 SRAM cell CONTACT
K. Kuhn, MIT invited seminar (MTL), 45nm High-k + Metal Gate Logic Technology,
5-19-08 (images from archives Mark Bohr, 2007)

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Metal Interconnects

9 levels of metal

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 Contacted Gate Pitch

Transistor gate pitch continues to scale 0.7x every 2 years.

Proves to be 4*F. F is the label for process generations.
M. Bohr, ISCC, 2009.

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Economics of Moore’s Law
1010
10
100 As the 109
number of
10-1 transistors 108
10-2 goes UP
$ per 107 Transistors
Transistor 10-3 Price per per Chip
106
10-4 transistor
goes DOWN 105
10-5
10-6 104

10-7 103
’70 ’80 ’90 ’00 ’10
Year
“Doubling of number of transistors per chip every 2 years”.
Lowers cost per transistor.
Self-fulfilling prophesy.
Original paper: G.E. Moore, Electronics 19, 114 (1965)

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Classic Scaling

Device or Circuit Parameter Scaling Factor

Device dimension tox, L, W 1/κ
Doping concentration Na κ
Voltage V 1/κ
Current I 1/κ
Capacitance εA/t 1/κ
Delay time/circuit VC/I 1/κ
Power dissipation/circuit VI 1/κ2
Power density VI/A 1

R. Dennard, IEEE JSSC, 1974

Classical MOSFET scaling

was first described by Dennard in 1974
Dennard, IEEE JSSC, 1974

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Process Evolution

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 Inflection in Scaling
THEN NOW
Scaling drove down cost Scaling drives down cost
Scaling drove performance Materials drive performance
Performance constrained Power constrained
Active power dominates Standby power dominates
Independent design-process Collaborative design-process

65nm 45nm 32nm 22nm

Images from Bai, Mistry, Natarajan, Auth IEDM/VLSI, 2004/7/8/12
(see course required reading)

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Short Channel Effects (SCE)

Degradation of
~ 1 / Subthreshold short channel effects
Slope (mV/dec)

V2 > V1
~DIBL (mV/V) ID

Decreasing L

VG

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 Electrostatics Benefits

“On”
Poor Current
SCE
Reduced Threshold
Channel Voltage
Current
(normalized)
Good
SCE

“Off”
Current

Gate Voltage (V)

Basic ID-VG
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Threshold Voltage

~Subthreshold
Slope (mV/dec)

~VTlin
~DIBL (mV/V)

http://en.wikipedia.org/wiki/Threshold_voltage

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On Current, Off Current

~Subthreshold
Slope (mV/dec)

Ioff
IDsat

~VTlin
~DIBL (mV/V)
Idsat (=Ion)

Ioff IDsat
IDsat

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Performance from Scaling

Natarajan, Intel, IEDM, 2008

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Where Performance Comes From
4.5

PMOS Ieff @ 0.7V (Normalized)

4 Tri-gate
3.5 HK-MG
3 Strain
2.5 Classic

2
1.5
1
0.5
0
90 65 45 32 22
Generation (nm)
Strain and High-k + metal gate are key
enablers past the 90nm node
K.J. Kuhn, Moore's Law past 32nm: Future Challenges in Device Scaling,
Solid State Devices and materials conference, plenary, October 2009

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Intel Announced First Tri-Gate (2011)

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Close-Up on Tri-gate Transistors

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Nomenclature of Non-Planar Devices

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Where Non-Planar Can Go?

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Working With Atomic Dimensions

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International Technology Roadmap for Semiconductors

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 Limits of Computing
Transistor Limits Interconnect Limits

14nm inverter

neuron

Moving from fundamental limits given by the laws of

physics to practical limitations. These limits tend to Fundamental limits
be broken.
Meindl, Proc. IEEE 83, 619 (1995). Material limits
Meindl, Chen, Davis, Science 293, 2044 (2001).
Meindl, J. Vac. Sci. Technol. B 14(1), 192 (1996). Device limits
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Equations for Fundamental Limits

Thermodynamics: if energy is less

Relativity: Signal no faster than the
than thermal – bit errors
speed of light
Esw  4kT L /   c0
Quantum Mechanics: energy time uncertainty

Eswtsw  h
Meindl, Proc. IEEE 83, 619 (1995).

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 Better Fundamental Limits
Thermodynamic limit on bit error ratio OFF
Esw  3kT source gate drain
Higher energy = faster switching

Eswtsw   electron

Energy of electron in a transistor

a
is limited by quantum confinement a
3 2 2 a a a
E sw  ON
2ma 2
Gate raised = confined in the source.
Gate lowered = can travel to drain.

electron
Solving equations together gives
limits

a  3.8nm tsw  27fs E sw  1.2  10 20 J  78meV

* Zhirnov et al., Proc. IEEE 91, 1934 (2003) and Nikonov and Bourianoff, JSNM 21, 497 (2008).

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 MOSFET Scales Towards the Limit

100 100
10

10 1

Gate Switching 0.1

Delay 1 Energy 0.01
(ps) (fJ)
0.001

0.1 0.0001
0.00001

0.01 0.000001
0.001 0.01 0.1 1 0.001 0.01 0.1 1
LGATE (mm) LGATE (mm)

Current CMOS device scaling close to the ideal limits

* Data courtesy of Robert Chau (Intel)

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How long is left for Moore’s law

Intel’s generation to HVM

2013 14nm
2017 7nm
2021 3.5nm
ITRS start of production
2012 32nm
2018 15nm
2024 7.5nm
2030 3.8nm
Scaling might end between 2021 and 2030
But it is NOT the end of Moore’s law:
better architectures, 3D circuits.

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Summary

 Moore’s law = 0.7 size every 2 years

 Despite trends, Intel developers manage to
improve performance
 Tri-gate transistors = major advance
 Fundamental laws limit size scaling to ~4nm

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