Preface

SystemVerilog Assertions
nd
Handbook, 2 edition
for Dynamic and Formal Verification

Ben Cohen
Srinivasan Venkataramanan
Ajeetha Kumari
...and Lisa Piper

VhdlCohen Publishing
Los Angeles, California
http://www.SystemVerilog.us/

SystemVerilog Assertions Handbook, 2nd Edition

ii

SystemVerilog Assertions
nd
Handbook, 2 Edition
for Dynamic and Formal Verification
Published by:
VhdlCohen Publishing
P.O. 2362
Palos Verdes Peninsula CA 90274-2362
ben@SystemVerilog.us
http://www. SystemVerilog.us/

Library of Congress Cataloging-in-Publication Data

A C.I.P. Catalog record for this book is available from the Library of Congress
SystemVerilog Assertions Handbook, 2nd Edition
for Dynamic and Formal Verification
ISBN 878-0-9705394-8-7

[1] Reprinted with permission from IEEE Std. IEEE P1800/D9-prelim Standard for
SystemVerilog Unified Hardware Design,Specification, and Verification Language,
Copyright 2009, by IEEE. The IEEE disclaims any responsibility or liability resulting from
the placement and use in the described manner.
Items reprinted from the above referenced IEEE document are identified with a prefix [1]
and are shown in italic font.

Copyright 2010 by VhdlCohen Publishing

All rights reserved. No part of this publication may be reproduced or transmitted in
any form or by any means, electronic or mechanical, including photocopying,
recording, or by any information storage and retrieval system, without the prior
written permission from the author, except for the inclusion of brief quotations in a
review.
Printed on acid-free paper
Printed in the United States of America

Preface

iii

Contents
1

Assertions In a Verification Methodology ............................................................................................. 1

1.1
DESIGN VERIFICATION METHODOLOGIES ................................................................................................ 2
1.1.1 SystemVerilog Assertions in Verification Strategy ................................................................... 5
1.1.2 Are Assertions Independent from Systemverilog Structures? ................................................... 5
1.1.3 Are Assertions Useful for the Definition and Verification of Designs? ..................................... 6
1.1.3.1
1.1.3.2
1.1.3.3
1.1.3.4
1.1.3.5
1.1.3.6

Captures Design Intent .................................................................................................................... 7

Allows Protocols to be Defined and Verified................................................................................... 7
Reduces the Time to Market ........................................................................................................... 8
Greatly Simplifies the Usage of Reusable IP .................................................................................... 8
Facilitates Functional Coverage Metrics ......................................................................................... 9
Generates Counterexamples to Demonstrate Violation of Properties ........................................... 9

1.1.4 Can/Should Entire Functional Verification Task be Performed Using SVA? .............................. 9
1.1.5 Is SystemVerilog Assertions Solely Restricted to Applications that Use SystemVerilog? ........ 10
1.2
SYSTEMVERILOG ASSERTIONS GOALS ................................................................................................... 10
1.3
SYSTEMVERILOG ASSERTIONS LANGUAGE ............................................................................................. 11
1.4
OVERVIEW OF PROPERTIES , ASSERTIONS, ATTEMPTS ............................................................................. 12
1.5
ASSERTION-BASED VERIFICATION ........................................................................................................ 18
1.5.1 Specification and Verification ................................................................................................. 18
1.5.2 assert / assume / cover / expect Directives .......................................................................... 19
1.5.3 Constraint -- assume/ restrict Directives ................................................................................ 19
1.5.4 Assertions ............................................................................................................................... 20
1.5.4.1
Immediate assertions assert / assume / cover ........................................................................... 20
1.5.4.1.1 Simple Immediate Assertions ................................................................................................... 20
1.5.4.1.2 Deferred Assertions.................................................................................................................. 21
1.5.4.2
Concurrent Assertions: assume property, assert property, cover property,
cover sequence, restrict property ..... 21

Understanding Properties .................................................................................................................... 23

2.1
ASSERTIONS AND PROPERTIES ............................................................................................................ 24
2.2
PROPERTY HEADER........................................................................................................................... 28
2.3
PROPERTY IDENTIFIER ....................................................................................................................... 28
2.4
BODY OF THE PROPERTY STATEMENT .................................................................................................. 28
2.4.1 Property Expression ................................................................................................................ 29
2.4.1.1
Safety And Liveness, Weak And Strong ............................................................................ 29
2.4.1.1.1 Strong and Weak ..................................................................................................................... 30
2.4.1.1.2 Liveness and Safety Properties ................................................................................................. 32

2.4.2
2.4.3

Clocking Event ......................................................................................................................... 32

Disabling Condition ................................................................................................................. 34

2.4.3.1
2.4.3.2

2.4.4

Formal Arguments and Usage ................................................................................................ 36

2.4.4.1

2.4.5

Disable Rules ................................................................................................................................. 34

Default Disable .............................................................................................................................. 35
Inferred functions for Clock and Disable ....................................................................................... 37

Property Operators ................................................................................................................. 39

2.4.5.1
Implication Operators |->, |=> ........................................................................................................ 39
2.4.5.1.1 Overlapped Implication Operator |->........................................................................................ 40
2.4.5.1.2 Non-Overlapped Implication Operator |=> ............................................................................... 41
2.4.5.2
not Operator .................................................................................................................................. 42
2.4.5.3
nexttime, s_nexttime .................................................................................................................... 43
2.4.5.4
and Operator + Vacuity Example ................................................................................................... 44

SystemVerilog Assertions Handbook, 2nd Edition

iv

2.4.5.5
2.4.5.6
2.4.5.7
2.4.5.8
2.4.5.9
2.4.5.10
2.4.5.11
2.4.5.12
2.4.5.13
2.4.5.14

or Operator ................................................................................................................................... 45
implies ........................................................................................................................................... 45
iff ................................................................................................................................................... 45
until ............................................................................................................................................... 46
Followed-by #-#, #=# ..................................................................................................................... 47
always, always[cycle_delay_const_range], s_always[bounded range] ......................................... 49
eventually, s_eventually................................................................................................................ 50
if else ............................................................................................................................................. 51
case ............................................................................................................................................... 52
accept_on, reject_on, sync_accept_on, sync_reject_on .............................................................. 53

2.5
LOCAL VARIABLES IN PROPERTIES ........................................................................................................ 55
2.5.1 Local Variable Formal Arguments........................................................................................... 57
2.5.2 First Application Example Using Variables ............................................................................. 58
2.5.3 Second Application Example Using Variables ........................................................................ 61
2.5.4 Third Application Example Using Variables ............................................................................ 62
3

UNDERSTANDING SEQUENCES ............................................................................................................ 63

3.1
SEQUENCE SYNTAX ........................................................................................................................... 64
3.2
SEQUENCE OPERATORS AND BUILT-IN FUNCTIONS ................................................................................. 66
3.3
REPETITION OPERATORS.................................................................................................................... 68
3.3.1 Attempt / Thread Difference ................................................................................................... 69
3.3.2 Impact of Multithreaded Sequences ....................................................................................... 72
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4

3.3.3

Multithreaded Sequence in Antecedent ....................................................................................... 72

Multithreaded Sequence in Consequent ...................................................................................... 74
Multithread Sequences in both Antecedent and Consequent ...................................................... 75
Consequent with Multiple Antecedent / Consequent Pairs .......................................................... 76

Consecutive Repetition ........................................................................................................... 77

3.3.3.1
3.3.3.2
3.3.3.3
3.3.3.4

[*n] Repetition Fixed ..................................................................................................................... 77

[*n:m] [*] [+] Repetition Range ...................................................................................................... 77
[*0 : m] Repetition Range with Zero ............................................................................................. 80
[*n : $], [*] [+] Repetition Range with Infinity ................................................................................ 81

3.3.4 Sequence Non-consecutive Repetition ([=n], [=range]) .......................................................... 83

3.3.5 Sequence goto Repetition ([->n ]) ........................................................................................... 84
3.3.6 Use Warnings: Non-Consecutive Repetition and goto Operators ........................................... 84
3.4
SEQUENCE COMPOSITION OPERATORS ................................................................................................. 86
3.4.1 Sequence Fusion (##0) and Empty Sequences ......................................................................... 87
3.4.2 Sequence Disjunction (or) ....................................................................................................... 88
3.4.3 Sequence Non-Length-Matching (and) ................................................................................... 89
3.4.4 Sequence Length-Matching (intersect, AND with length restriction)) ................................... 89
3.4.5 Sequence Containment (within) ............................................................................................... 90
3.4.6 Expression over Sequences (throughout operator) ................................................................... 91
3.5
METHODS SUPPORTING SEQUENCES .................................................................................................... 91
3.5.1 first_match Operator .............................................................................................................. 91
3.5.2 End Point of Sequences, .triggered ........................................................................................ 94
3.5.3 End Point of Sequences, .matched .......................................................................................... 96
3.5.4 End Point Application Examples ............................................................................................. 98
3.5.4.1
3.5.4.2
3.5.4.3

End Points as a Starting Point to Build Sequences ........................................................................ 98

.triggered as Level-Sensitive Control ........................................................................................... 100
Sequence Events ......................................................................................................................... 101

3.6
VARIABLES .................................................................................................................................... 101
3.6.1 Variable Types, Initializations, Assignments, Updates (Rule 1, 3, 4) .................................... 106
3.6.2 Update of Local Variables (Rule 15) ...................................................................................... 107
3.6.3 Local Variables in Repetitions (Rule 8, 9) .............................................................................. 107
3.6.4 Formal Arguments and Local Variables in sequences (Rule 11, 12, 17) ................................ 108
3.6.5 No Empty Match in Local Variables Assignments (rule 5) .................................................... 111

Preface

3.6.6
3.6.7
3.6.8

Local Variable Must be Written Once Before Being Read (rule 6) ........................................ 112
Local Variable is Unassigned if Not Flowed Out (rule 7, 10) ................................................. 112
Local Variables in Concurrent and, or, and intersect Threads (rule 14) ................................... 112

3.6.8.1
3.6.8.2
3.6.8.3

3.6.9
4

Variables Assigned on Parallel or Threads ................................................................................ 113

first_match(seq1 or seq2) ........................................................................................................... 115
Variables Assigned on Parallel and intersect Threads ........................................................... 115

.triggered Method in Sequences with Input or Inout Local Variable Formal Arguments ...... 117

Advanced Topics For Properties and Sequences ............................................................................... 121

4.1
ASSERTION-BASED SYSTEM FUNCTIONS.............................................................................................. 121
4.1.1 Sampled Valued Functions .................................................................................................... 121
4.1.1.1
Value Access Functions ............................................................................................................... 122
4.1.1.1.1 $sampled(expression) ............................................................................................................ 122
4.1.1.1.2 $past ....................................................................................................................................... 123
4.1.1.2
Value Change Functions .............................................................................................................. 124
4.1.1.2.1 $rose and $fell ........................................................................................................................ 124
4.1.1.2.2 $stable, $changed .................................................................................................................. 126

4.1.2
4.1.3
4.1.4

Vector-Analysis System Functions......................................................................................... 126

Severity-Level System Functions ........................................................................................... 127
Assertion-Control System Tasks ............................................................................................ 128

4.1.4.1
4.1.4.2

Assertion Evaluation -Control System Tasks ............................................................................... 128

Assertion Action Blocks -Control System Tasks ........................................................................... 130

4.2
CLOCKED SEQUENCES, PROPERTIES, AND MULTICLOCKING .................................................................... 130
4.2.1 Clock Inferrence .................................................................................................................... 131
4.2.2 Multiclocked Sequences and Properties ............................................................................... 133
4.2.3 Clocking Rules in Assertions .................................................................................................. 135
4.2.4 Clock Flow ............................................................................................................................. 136
4.2.5 Procedural Concurrent Assertion .......................................................................................... 137
4.2.6 Arguments to Procedural Concurrent Assertions .................................................................. 139
4.3
SYSTEMVERILOG SCHEDULING SEMANTICS FOR ASSERTIONS ................................................................... 142
4.4
PROPERTIES IN INTERFACES .............................................................................................................. 144
4.5
ASSERTION STATEMENTS ................................................................................................................. 145
4.5.1 Purpose of Verification Statements ...................................................................................... 146
4.5.1.1
4.5.1.2
4.5.1.3
4.5.1.4
4.5.1.5
4.5.1.6

assert Statement ......................................................................................................................... 146

assume Statement ...................................................................................................................... 146
restrict statement ....................................................................................................................... 148
cover Statement .......................................................................................................................... 149
Expect Construct ......................................................................................................................... 150
Action-Block ................................................................................................................................ 152

4.6
IMMEDIATE ASSERTIONS.................................................................................................................. 153
4.6.1 Simple Immediate Assertions ................................................................................................ 154
4.6.2 Deferred Assertions............................................................................................................... 155
4.7
BINDING PROPERTIES TO SCOPES OR INSTANCES .................................................................................. 157
5

CHECKER ............................................................................................................................................ 161

5.1
MOTIVATION AND ADVANTAGES OF CHECKER CONSTRUCT..................................................................... 162
5.1.1 Inlining of checkers ............................................................................................................... 163
5.1.2 Allows for Passing Additional Types of Arguments ............................................................... 163
5.1.3 Prevents Accidental Synthesis of Assertion Related Code ..................................................... 163
5.1.4 Assists in Code Reviews and Verification Plans ..................................................................... 163
5.1.5 Avoids False Negatives with Linting Process......................................................................... 164
5.2
SYNTAX OF CHECKER CONSTRUCT ...................................................................................................... 164
5.3
CHECKER CONTENTS ....................................................................................................................... 166
5.4
CHECKER USE MODEL ..................................................................................................................... 167

SystemVerilog Assertions Handbook, 2nd Edition

vi

5.4.1
5.4.2
5.4.3

Classification of checkers Assertion Statements .................................................................. 167

Classification of checker Instances........................................................................................ 168
checker Declaration and Instances ....................................................................................... 169

5.4.3.1
5.4.3.2

5.4.4

checker as Separate Verification Unit ......................................................................................... 169

checker Defined within DUT ....................................................................................................... 172

Behavior of Instantiated checkers ........................................................................................ 173

5.4.4.1
5.4.4.2

Static checker Instantiation ......................................................................................................... 173

Procedural checker Instantiation ................................................................................................ 174

5.5
CHECKER RULES ............................................................................................................................. 177
5.5.1 Allowed Procedures inside checker ....................................................................................... 177
5.5.2 Disallowed Procedures inside checker .................................................................................. 179
5.5.3 Argument Passing ................................................................................................................. 180
5.5.3.1
5.5.3.2
5.5.3.3
5.5.3.4
5.5.3.5

5.5.4
5.5.5
5.5.6

Allowed Assignment Style ..................................................................................................... 183

Context Inference .................................................................................................................. 184
Variables / Loops / rand Qualifier ......................................................................................... 186

5.5.6.1
5.5.6.2
5.5.6.3
5.5.6.4
5.5.6.5

5.5.7
5.5.8
5.5.9
6

Formal Argument Types and Directions ..................................................................................... 181

$ in Actual Argument................................................................................................................... 181
If Actual Argument is const Cast Or automatic then Formal Arguments
Used Only in Static Assertions ....... 182
Actuals can be Events, Sequences, or Properties ........................................................................ 182
Inside checker Actuals Get Arguments from Formal of Parent ................................................... 183

& Module automatic variable cannot be referenced from within checker ............................... 186
Loops and automatic variable in checkers .................................................................................. 186
checkers variables exist for whole simulation............................................................................ 187
variable with rand qualifier may behave non- deterministically ................................................. 189
checker variable assignment rules .............................................................................................. 189

checker Instantiation ............................................................................................................ 190

Whats not in Checkers ......................................................................................................... 191
Capturing Functional Coverage Model Inside Checker ......................................................... 192

SystemVerilog Assertions In the Design Process ............................................................................... 193

6.1
TRADITIONAL DESIGN PROCESS......................................................................................................... 194
6.2
DESIGN PROCESS WITH ABV USING SVA AS VEHICLE ............................................................................ 194
6.2.1 System-level Assertions......................................................................................................... 195
6.2.1.1
6.2.1.2
6.2.1.3
6.2.1.4

6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7

Cause and Effect Class of Requirements ..................................................................................... 197

Latencies ..................................................................................................................................... 198
Definition of Processing Algorithms ............................................................................................ 198
Analyzing Properties Prior to RTL Design .................................................................................... 199

Interface Assertions .............................................................................................................. 199

Architectural Plan ................................................................................................................. 200
Verification Plan.................................................................................................................... 200
RTL Design ............................................................................................................................ 201
Write Testbench and Simulate .............................................................................................. 201
Analyze the Simulation Results and Coverage ...................................................................... 202

6.2.7.1
6.2.7.2

Functional Coverage in Verification ............................................................................................ 202

SystemVerilog Assertions API ...................................................................................................... 203

6.2.8 Formal Verification (FV) ........................................................................................................ 206

6.3
CASE STUDY - SYNCHRONOUS FIFO................................................................................................... 206
6.3.1 Synchronous FIFO Requirements .......................................................................................... 206
6.3.2 Verification Plan.................................................................................................................... 217
6.3.3 RTL Design ............................................................................................................................ 224
6.3.4 Simulation ............................................................................................................................. 224

Preface

vii

FORMAL VERIFICATION USING Assertions ........................................................................................ 225

7.1
FORMAL VERIFICATION METHODOLOGY ............................................................................................ 226
7.2
GLOBAL CLOCKING PAST AND FUTURE SAMPLED VALUE FUNCTIONS ........................................................ 231
7.2.1 Global Clocking ..................................................................................................................... 232
7.2.2 Additional Sampled Value Functions .................................................................................... 232
7.2.3 Application of Global Clocking .............................................................................................. 236
7.3
ROLE OF SYSTEMVERILOG ASSERTIONS IN FV ....................................................................................... 237
7.3.1 SystemVerilog Assertions in Formal Specifications ............................................................... 237
7.3.2 SystemVerilog Assertions Usage in FV vs. Dynamic ABV ...................................................... 238
7.3.3 Same Inputs in Antecedent and Consequent ........................................................................ 239
7.4
CASE STUDY - FV OF A TRAFFIC LIGHT CONTROLLER.............................................................................. 239
7.4.1 Model .................................................................................................................................... 239
7.4.2 SystemVerilog Assertions for Traffic Light Controller ........................................................... 242
7.4.3 Verification ........................................................................................................................... 245
7.4.4 Good Traffic Light Controller ................................................................................................ 247
7.5
CASE STUDY: FORMAL VERIFICATION OF FIFO RTL .............................................................................. 251
7.5.1 Setting up Design and Properties.......................................................................................... 251
7.5.2 Debugging an Assertion ........................................................................................................ 253
7.5.3 Adding Constraints ............................................................................................................... 253
7.5.4 A Real Bug ............................................................................................................................. 256
7.5.5 Coverage and Final Result .................................................................................................... 257
7.5.6 assert and assume for Same Property: Then What? ............................................................ 258
7.6
FV COVERAGE METRICS .................................................................................................................. 259
7.6.1 Proof Radius .......................................................................................................................... 259
7.6.2 Explored State-Based Coverage ............................................................................................ 259
7.6.3 Flip-flop to Property Distance ............................................................................................... 260
7.6.4 Automated Gap Detection .................................................................................................... 260
7.7
EMERGING APPLICATIONS OF SYSTEMVERILOG ASSERTIONS WITH FORMAL METHODS ................................ 260
7.7.1 SystemVerilog Assertions-Based Performance Evaluation of Digital Systems ...................... 261
7.7.2 Hybrid (dynamic and formal) Verification ............................................................................ 261
7.7.3 Directed Random Test Generation from SystemVerilog Assertions ...................................... 262
7.7.4 Achieving Hard-to-hit Functional Coverage Goals using Formal Methods ........................... 262
7.7.5 Functional Coverage Points Generation from SVA + FV ....................................................... 264
7.8
SIMULATION OR FORMAL VERIFICATION? ........................................................................................... 265
7.8.1 Arguments for Simulation with ABV ..................................................................................... 265
7.8.2 Arguments for Formal Verification ....................................................................................... 266
7.8.3 Balance ................................................................................................................................. 266
7.8.4 Recommendations ................................................................................................................ 266
7.8.5 Validity of Formal Verification results................................................................................... 267

SystemVerilog Assertions Guidelines ................................................................................................. 269

8.1
NAMING CONVENTION GUIDELINES .................................................................................................. 270
8.1.1 File naming ........................................................................................................................... 270
8.1.2 Naming of Assertion Constructs ........................................................................................... 270
8.1.3 Ending Statements with Labels ............................................................................................. 271
8.1.4 Constants for Modules and Interfaces .................................................................................. 271
8.1.5 Local Variables within Properties and Sequences ................................................................. 272
8.2
STYLE........................................................................................................................................... 273
8.2.1 Explicit or Implicit Declaration of Properties ........................................................................ 274
8.2.2 Use Formal Arguments only when Reuse is Intended ........................................................... 275
8.2.3 Use generate Construct for Assertions Conditional on Parameters ...................................... 275
8.2.4 Standardize Action Block Error Display ................................................................................. 276

SystemVerilog Assertions Handbook, 2nd Edition

viii

8.2.5 Using Named Lets/Sequences/Properties ............................................................................. 276

8.2.6 Adopting New IEEE 1800-2009 Features .............................................................................. 277
8.2.7 Use Strong Property Operators for Assertions that Must Complete ..................................... 277
8.2.8 Defining Clocking Events ....................................................................................................... 277
8.2.9 Modeling Abort Conditions in Properties .............................................................................. 278
8.2.10
Module Ports or Registered Signals in Properties ............................................................ 279
8.2.11
Assertions with Verilog RTL .............................................................................................. 280
8.2.12
Dynamic Data Types inside Properties ............................................................................. 280
8.2.13
Cyclic Dependencies between Sequences ......................................................................... 281
8.2.14
Use the let Construct ..................................................................................................... 281
8.3
USE MODEL GUIDELINES ................................................................................................................. 282
8.3.1 Be Aware of Overlapping Assertions..................................................................................... 282
8.3.2 Use first_match in Antecedents to Avoid Unexpected Results ............................................. 282
8.3.3 Avoid not Properties When Possible ..................................................................................... 286
8.3.4 Beware of Metalogical Values .............................................................................................. 287
8.3.5 Avoid Vacuous Properties ..................................................................................................... 287
8.3.6 Avoid Contradictory Properties ............................................................................................. 287
8.3.7 Beware of unsized additions in +1 versus +1b1, Use Size Casting if Necessary .................. 288
8.3.8 Use $sampled Function in Action Block to Display Values Used in Assertion Evaluation...... 289
8.3.9 Use $sampled Function when Conditionally Instantiating Concurrent Assertions
in Procedural Code ....... 289
8.3.10
Update of Module Variables ............................................................................................ 289
8.3.10.1
8.3.10.2

Variables Updated in Action Block .............................................................................................. 290

Variables Update in Sequence Match Item ................................................................................. 290

8.3.11
Ensure Assertions Can Hold .............................................................................................. 292
8.3.12
Do Not Use [=n] in Antecedent Without a first_match .................................................... 292
8.3.13
Use $rose in Antecedents, but with Caution! There are Exceptions! ................................ 292
8.3.14
Do Not Use an Assertion When You Mean Coverage ....................................................... 292
8.4
METHODOLOGY GUIDELINES ............................................................................................................ 293
8.4.1 Classification of Properties ................................................................................................... 293
8.4.1.1
8.4.1.2
8.4.1.3
8.4.1.4
8.4.1.5

8.4.2
8.4.3
8.4.4
8.4.5
9

Design Centric ............................................................................................................................. 293

Assumption Centric ..................................................................................................................... 293
Requirement / Verification Centric ............................................................................................. 293
Environmental Properties ........................................................................................................... 294
Coverage Properties .................................................................................................................... 295

Process of Writing Properties and Assertions ....................................................................... 297

Review Properties and Assertions Against Requirements ..................................................... 299
Simulate and Formally Analyze the Design ........................................................................... 299
Guidelines for Debugging Assertions .................................................................................... 300

SystemVerilog Assertions Dictionary ................................................................................................ 301

9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11

IF COND1, THEN COND2 .............................................................................................................. 302

IF COND1, THEN AT NEXT COND2, COND3 ..................................................................................... 302
IF COND1, THEN AFTER NTH COND2, COND3 ................................................................................. 303
IF COND1 AND FIRST COND2, THEN COND3 UNTIL COND4 .............................................................. 303
IF COND1 AND FIRST COND2, THEN SEQUENCE ................................................................................. 304
BETWEEN COND1 AND COND2, SIGNAL 1 ASSERTED .......................................................................... 305
IF COND1 AND THEN 1 OCCURRENCE OF COND2 THEN SEQUENCE ........................................................ 306
IF COND1 THEN N OCCURRENCES OF COND2 BEFORE COND3; N IS VALUE OF A VARIABLE ........................ 307
IF COND1 AND, WITHIN N CYCLES, Y OCCURRENCES OF COND2 THEN COND3 ........................................ 308
IF COND1, THEN COND2 UNTIL COND3 ......................................................................................... 309
IF COND1 THEN COND2 BEFORE COND3 ............................................................................................ 309

Preface

9.12
9.13
9.14
9.15
9.16
9.17
9.18
9.19
9.20
9.21

ix

IF COND1 IS FOLLOWED BY COND2, AND COND3 IS NOT RECEIVED WITHIN 64 CYCLES WHILE COND2
THEN ERROR (COND5). IF COND3 IS RECEIVED WITHIN 64 CYCLES THEN COND4 . 310
IF COND1 THEN COND2 IN N CYCLES UNLESS COND3 ........................................................................ 311
DATA INTEGRITY IN MEMORY. DATA READ FROM MEMORY SHOULD BE SAME AS WHAT WAS LAST WRITTEN 313
DATA INTEGRITY IN QUEUES. INTERFACE DATA WRITTEN MUST BE PROPERLY TRANSFERRED
TO THE RECEIVING HARDWARE . 314
NEVER 2 CONSECUTIVE WRITES WITH SAME ADDRESS .......................................................................... 316
WHEN A CACHED ADDRESS (COND1) IS RETIRED (COND2), THE CACHE COPY SHALL BE INVALIDATED
(COND3) WITHIN 2 TO 7 CLOCKS .. 316
ASSUME RESET LOW FOR INITIAL N CYCLES .......................................................................................... 317
IF A SEQUENCE STARTS BUT DOES NOT COMPLETE, THEN STATE REGISTER MUST BE IN ERROR STATE .............. 318
COND1 AND COND2 ARE MUTUALLY EXCLUSIVE ............................................................................... 319
NO REWRITES TO SAME ADDRESS BEFORE READ .................................................................................. 321

Appendix A Answers to Exercises ............................................................................................................... 323

Appendix B: Definitions .................................................................................................................................. 331
Index ........................................................................................................................................................... 343

SystemVerilog Assertions Handbook, 2nd Edition

Preface

xi

FOREWORD, Dennis Brophy

Debug of electronic systems is an ever increasing challenge given the relentless increase in design
complexity. Many design issues are buried deep in a system and can difficult to reach or detect in
a timely fashion even with todays automated stimulus generation solutions.
Assertion-based verification technology has been found to address these challenges. Design and
verification engineers can place assertions in designs or bind assertions to designs to monitor,
report and take action when incorrect design behavior is detected. Assertions are the basic
elements that enable formal verification where design properties are examined to determine
design correctness and facilitate the creation of counter examples to demonstrate design failures.
Recent research has shown more than two-thirds of IC and ASIC designers are using
SystemVerilog assertions today with three-fourths to be using them during 2010. FPGA design
verification is also facilitated by the use of assertions given the advent of FPGAs with embedded
processor cores along with advanced protocol support that would generally require designers to
wait until the FPGA was placed in a system to fully debug the system.
The second edition to the SystemVerilog Assertions Handbook comes at a time when the IEEE
updates its popular SystemVerilog standard (IEEE Std. 1800-2009) and an FPGA community
that is increasing its adoption of SystemVerilog assertions. Design and verification engineers will
find the handbook as an excellent resource to begin to adopt assertions, and to apply the latest
additions and updates found in the IEEE standard to ever pressing design and verification
challenges.
Dennis Brophy
Director of Strategic Business Development
Design Verification Technology Division
Mentor Graphics Corporation
http://www.mentor.com/

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FOREWORD, Shankar Hemmady

When I was asked to review the book, my first thought was, Dont we have enough books on
SVA already? However, having worked with Ben and Srini in the past, I was curious to learn
more. As I browsed through the book, it became evident that this was a masterpiece in the
works. This is the first book to take a design verification engineers and managers perspective in
the assertions arena. It puts the debate on static formal analysis versus dynamic simulation-based
assertion checks to rest by providing guidelines on how and where to use these technologies
appropriately. The book also includes a lexicon of commonly used temporal
requirements/properties in plain English. This is valuable reference material for engineers
working in the trenches.
Shankar Hemmady
Principal Engineer,
Synopsys Inc,
Mountain View, California
The new IEEE SystemVerilog Standard has significantly expanded the support for assertions in
the language. Some of these extensions add capabilities for sophisticated users, while others
make the language easier to use even for beginners. The System Verilog Assertions Handbook,
2nd Edition, tackles the critical task of documenting the new (and original) language features with
clear explanations and numerous usage examples. Im certain that the authors efforts will
accelerate the adoption of these valuable new capabilities. I can certainly recommend this book
to anyone who wants to get up to speed on the latest System Verilog assertion capabilities for
simulation and formal verification.
Dan Benua
Principal CAE
Synopsys Verification Group
Mountain View, California

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FOREWORD, Michael Siegel

Assertion-based verification (ABV) and SystemVerilog assertions (SVA) have enjoyed

significant adoption in verification projects, both large and small. Assertions, in general, and
SystemVerilog assertions in particular, are an effective means to analyze and verify design
behavior. They are employed to share design intent, to check expected designs behavior, to
enhance error observability, to speed integration verification and to define coverage models, to
name but a few applications. Moreover, assertions can be used in simulation and formal
verification, enabling engineers to leverage the complementary strengths of these technologies for
block, subsystem, and chip-level verification, in order to reduce overall verification effort and to
achieve earlier verification closure.
This book, SystemVerilog Assertions Handbook, 2nd Edition by Ben Cohen, Srinivasan
Venkataramanan , Ajeetha Kumari and Lisa Piper, is a timely, practical and comprehensive
reference manual on the use of SystemVerilog assertions, addressing both the existing community
of SVA users and people who want to get started with SVA-based ABV, in both (System)Verilog
and VHDL designs.
The book one of the first to cover the new SystemVerilog standard, IEEE 1800-2009
establishes a conceptual foundation for how to use SVA for assertion-based verification and
serves as a practical users guide. It details a broad range of assertion use from the capture of lowlevel design intent to specification-level requirements, comprehensively covering language
features, style guidelines and methodology, taking a step-by-step approach illustrated by many
real-world design and assertion examples. Its examples also illustrate the power of using the
complementary strengths of dynamic and formal ABV. Experienced SVA users will appreciate
the clear presentation and good overview of the new SVA features in the IEEE 1800-2009
standard.
Michael Siegel
Product Marketing Director
OneSpin Solutions
http://onespin-solutions.com/

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SystemVerilog Assertions Handbook, 2nd Edition

FOREWORD, Scott Sandler

Like many transformative changes in electronic design, Assertion-Based Verification has taken a
long time to mature and become established in the mainstream methodology. And it has followed
the typical adoption pattern: early use by very large companies with their own in-house tools and
proprietary languages; subsequent emergence of commercial tools, still using proprietary
languages; standardization of a language; maturation of tools and techniques; and finally broad
acceptance. There is no longer any question that Assertion-Based Verification is a necessary part
of the design flow for complex integrated circuits.
Nor is there any uncertainty about the language that will be most widely used to express
assertions; it will be SystemVerilog Assertions. This update to the SystemVerilog Assertions
Handbook is of course very timely. With the recent release of IEEE 1800-2009, SystemVerilog
assertions have been greatly enhanced for both power and usability. The new checker entity in
particular, which gets authoritative treatment in the book, makes thorough verification easier to
accomplish and makes testbenches easier to understand.
The approach that Ben Cohens team uses to prepare and present highly technical information
renders it easily approachable, accessible, and useful. Readers will appreciate the clarity and
completeness of the text and examples, and will find they can rely on the SystemVerilog
Assertions Handbook as a constant companion as they adopt and refine assertion-based
verification using SVA.

Scott Sandler
Vice President, Corporate Marketing, SpringSoft, Inc.
President, SpringSoft USA
http://www.springsoft.com/

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FOREWORD, Tapan Kapoor

SVA is part of SystemVerilog standard (IEEE 1800). With the latest version of SystemVerilog
LRM (IEEE 1800-2009), several new constructs and enhancements have been added to SVA,
such as the checker construct, new sampled value functions, enhanced local variable support,
global clocking, contextual clock inferring, new property operators (iff/ implies/ followed-by/
nexttime/ always/ until/ eventually) and so on.
This book is an excellent enabler for beginners and a detailed guide for advance SVA users. The
book explains the syntax and semantics of all the existing and new constructs in SVA, identified
with a sidebar, and supplemented with examples, appropriate diagrams, and waveform charts.
The book also explains the guidelines for writing assertions that facilitate efficient and effective
usage of ABV. This book also addresses, by example, various components of verification
Coverage, Verification Methodology, Verification Planning, and Formal verification in the
context of SVA assertions.
At Cadence, we are committed to support SVA in all our tools including simulation, formal
verification, and hardware-assisted acceleration. Cadence supports SVA through the generation
of native code that is tightly integrated into our Incisive assertion-based verification
environment for simulation and formal verification, which is based on simulation and model
checking, respectively. We proactively created all the tools and flows required to support the
advanced verification components to work well in different verification environments.

Tapan Kapoor
Incisive ABV - R&D
Cadence Design Systems, Inc.
http://www.cadence.com/

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SystemVerilog Assertions Handbook, 2nd Edition

FOREWORD, Daniel Mlynek

In my opinion, the book SystemVerilog Assertions Handbook, 2nd Edition by Ben Cohen,
Srinivasan Venkataramanan, Ajeetha Kumari and Lisa Piper is a perfect source of ABV
knowledge. The book will guide the reader step by step through the ABV methodology.
Starting from basic knowledge for beginners, it will unveil the power of the SVA. The
book describes all language constructs - one by one - with examples and real design
applications for learned constructs. It points out the language pitfalls, and explains the
grey areas in the language so that you do not spend hours trying to understand why your
assertion code doesn't work as expected.
Along with providing a great level of detailed information on the assertion language
itself, this book also provides a wider look on the whole verification process and the role
of ABV in this process, including from the managers point of view. The book also shows
what features can be expected from the tools, and how tools can help us analyze the
results. At the end we are given a set of guidelines for the methodology and the language
that help avoid confusion. The 2nd edition of the book has another advantage, which is
significant; it is written on the basis of the new SystemVerilog standard - IEEE1800-2009
by people who were involved in the standard development. SystemVerilog is a living
language and the new standard introduces new, complex, and powerful features, which
can be found in the book.
In conclusion, I'm certain that the readers will not put this book on the shelf after reading,
but will be referring to it frequently as a reference manual.
Daniel Mlynek
Leader Application Engineer
http://www.aldec.com/

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FOREWORD, Don Mills

SystemVerilog Assertions Handbook, 1st Edition was a primary source for Sutherland HDL's
training courses on SystemVerilog Assertions. Students referred to the book often during training
classes, for details and reference. It is anticipated that this 2nd Edition will provide yet further
enlightenment on the topic of Assertions, for individuals and training courses, for many years to
come.
SystemVerilog Assertions Handbook, 2nd Edition is an excellent reference for learning the basics
of the assertion language. Syntax summaries alongside examples help in learning the syntax.
There are many examples with graphical representations that demonstrate the concepts. Basic
rules are listed, often with quotes from the standard, and then explained. The book goes beyond
the standard to demonstrate many subtleties that produce unexpected results and poor
performance, and flags the pitfalls to avoid. It is a great refresher for experienced users and for
those looking to understand what is new in the SVA language for the IEEE 1800-2009 release.
Additional chapters present methodology and application perspectives.
Don Mills
LCDM ENGINEERING.
Consultant, trainer for SystemVerilog and SVA courses.
http://www.lcdm-eng.com
http://www.sutherland-hdl.com

Quote, Erik Seligman

Bens probing questions have significantly helped those of us on the committee to better
understand some implications of the many new language features we added to the IEEE 18002009 standard. As a result, I am eagerly looking forward to the arrival of this new book, which I
will be using as a key reference on SystemVerilog assertion issues.
Erik Seligman,
Chair of the IEEE p1800 Special Subcommittee on Checkers

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SystemVerilog Assertions Handbook, 2nd Edition

PREFACE
The Book
SystemVerilog Assertions Handbook, 2nd Edition is a follow-up book to the first edition,
published in 2005. This version addresses the new SystemVerilog assertion features,
enhancements, and clarifications presented by the IEEE 1800-2009 Standard for SystemVerilog
Unified Hardware Design, Specification, and Verification Language (herein referred as IEEE
1800-2009, or LRM language reference manual).1 These new changes in the area of assertions
include several new operators for properties and sequences; newer assertion statements; defaults
disables; usage and restrictions of property and sequence local variables; changes in the
interpretation of some operators; and the definition of a new type of entity called checker. The
checker supports the grouping of several assertion directives and related supporting code, and the
inlined instantiation of this grouping in the design. Another significant enhancement to IEEE
1800-2009 was the redefinition of assertions in procedural code. The previous release of the
standard was also enhanced to protect against races causing false firings of immediate assertions
in procedural code.
Our goal is to make SystemVerilog Assertions Handbook, 2nd Edition an excellent reference
manual on the use of SystemVerilog assertions. We explain the concepts via text/tables/diagrams,
images, annotations, and simulation results. We present, by examples, the coding rules with
many simulatable models. We also provide guidelines and recommendations in the use of SVA
in the design and verification process. We address formal verification and use two complete
examples to demonstrate the value of formal verification. We provide a dictionary of modeling
requirements that are translated into assertions, and a dictionary of common terms used in
assertions. All new IEEE 1800-2009 features are identified with a bold bar on the left margin.
Many examples include complete test verification code, along with simple testbenches to
demonstrate the concepts and show the simulation results. These models, along with the captured
waveforms and thread viewer and assertion statistics are available in the distribution files. The
simulation results are courtesy of Mentor Graphics who provided us with access to QuestaSim
and ModelSim DE for the simulation of SVA code. We also used the ouputs of Verdi Automated
Debug System to further demonstrate the key points on assertions. In addition, the models used in
formal verification were verified with OneSpin 360 MV Product Family of formal verification
tools, and the graphical results are also provided on the distribution files, courtesy of OneSpin
Solutions.
This book represents the collaboration of four authors who are experts in SystemVerilog
linguistics, system engineering, architecture, and design and verification with hardware
description languages (HDLs) and hardware verification languages (HVLs), along with

1 This book is based on P1800/D9, August 6, 2009 DRAFT STANDARD FOR SYSTEMVERILOG,

which reflects the latest version frozen to further technical changes.

Preface

xix

experience in teaching and in authoring several books on assertion and verification, thus bringing
more synergism to this SystemVerilog Assertions Handbook, 2nd Edition.
How to read this book
When a child learns a language, he first learns, by dense exposure to the words and through
multiple passes, concepts, basic vocabulary, and overview before learning the alphabet and the
grammar of the language. SystemVerilog is a language, and the assertions aspect is another
outbreak of that language. In presenting the material for SVA, we took a similar approach to the
learning process of a language. We started with an overview and exposure of the basic concepts,
with many examples, without getting into the details of the grammar and rules. We then focused
on the details of the properties and sequences, and then moved on to advanced topics with more
examples. When addressing each of those topics, we decided to present applications and
information that dealt with the topic at hand (e.g., local variables) but with certain advanced
topics presented in later sections (e.g., first_match operators). Throughout the book we indicated
the forward / backward referencing of critical topics. Thus, we envision the reading of this book
as a multi-pass process, with appropriate jumps to forwarded material if the reader is more
interested in that topic. We believe that this process will help the reader grasp the various
concepts, applications, and grammar of the language.
Throughout the book we used a coding style notation explained in Chapter 8 on guidelines.
Those guidelines emerged from years of doing design and verification, and of using / teaching
HDLs and assertion languages. We strongly recommend that the guidelines presented in this
chapter be considered. We also strongly recommend writing the exercises at the end of Chapter 3
and reading the answers to those exercises in Appendix A; those answers provide additional
information and recommendations about the critical concepts.
The Intent
One of the reasons that we decided to write this handbook on SystemVerilog Assertions is the
positive impact that Assertion-based Verification (ABV) is providing, and we believe that
SystemVerilog is setting up a viable and effective standard in the design and verification
processes. We also felt that the assertions aspect of SystemVerilog needed special emphasis.
Thus, we maintain the focus of this book on SystemVerilog Assertions, with usage of many of the
new features that SystemVerilog provides. We are assuming that the users are familiar with
SystemVerilog, and have access to books that address SystemVerilog language. 2
AssertionBased Verification is changing the traditional design process because that methodology helps to
formally characterize the design intent and expected operations.3 ABV also quickens the
verification task because it provides feedback at the white-box level.4 As a formal property
specification language, SystemVerilog Assertions facilitate automation of common verification
tasks that can be exploited across various verification methodologies.

2 * SystemVerilog Language Reference Manual http://www.systemverilog.org/

* SystemVerilog For Verification, Tom Fitzpatrick, Dave Rich, Aturo Salz and Stuart Sutherland,
2005, Springer Springeronline.com
* SystemVerilog For Design A Guide to Using SystemVerilog for Hardware Design and Modeling
Stuart Sutherland, Simon Davidmann, Peter Flake, KAP, June 2003, ISBN 1-4020-7530-8
3 Assertion-Based Design, Second Edition, Harry D. Foster, Adam C. Krolnik, David J. Lacey
June 2004, ISBN 1-4020-8027-1,
The SystemVerilog Verification Methodology Manual (VMM), 2005 Springeronline.com
4 Writing Testbenches: Functional Verification of HDL Models, Janick Bergeron, Kluwer Academic
Publishers

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SystemVerilog Assertions Handbook, 2nd Edition

As designers and consultants/trainers, we experienced many designs that were weakly specified
and documented. The RTL modeling lacked information about properties and design
characteristics, and that led to difficulties and/or ambiguities in the maintenance and verification
processes. A design specification is helpful in defining requirements. However, specifications
are generally defined in an informal language, like English. They lack a standard machine
executable representation and cannot be dynamically simulated and/or statically processed by a
formal verification tool to ensure compliance to requirements.
Assertion-Based Verification with SystemVerilog Assertions
SVA gives the design architects a standard means of specifying design properties using a concise
syntax with clearly defined formal semantics. Similarly, it enables the RTL designers to capture
design intent and assumptions in a verifiable form, while enabling the verification engineers to
validate that the implementation satisfies its specification through dynamic (i.e., simulation) and
formal verification options. Furthermore, it provides a means to measure the quality of the
verification process through the creation of functional coverage models built on formally
specified properties. It provides a standard means for hardware designers and verification
engineers to rigorously document the design specifications using a machine-executable format.
SystemVerilog with assertions improves the quality of digital designs and helps eliminate defects
per the Six Sigma methodology5 because assertions play an important role in a unified
verification methodology ranging from requirement definitions through design and verification
(see Chapter 6 for discussion on the design process with SystemVerilog Assertions). Assertions
express functional design intent and can be used to express assumed input behavior, expected
output behavior, or forbidden behavior. Assertions allow the architects or designers to capture
the design intent and assumptions in a manner that can be verified in the implementation.
Assertions are captured during the development process and are continuously verified throughout
the design and verification process. Working in a unified verification methodology, assertions
reduce the verification time by detecting bugs earlier, and by isolating where a bug is located (by
being closer to the source of error). In addition to detection of property violations, assertions
improve the efficiency in a unified methodology by improving reuse, enhancing testbench
checking, and capturing coverage information. Per Lionel Bennings experience, designers
created fewer initial bugs in the RTL as an ABV methodology forced them to think more clearly
and accurately about what to design.6 Also, properties are more accurate and less prone to
misinterpretation than comments in the RTL.
Our experience with the usage of SystemVerilog Assertions for front-end design definitions
demonstrated that SystemVerilog Assertions are very powerful in the process of delving into
design requirements, design architecture, and definition of restrictions imposed by the
architecture. We found the property and assertion definitions more expressive and precise than
the use of a natural language, e.g., English. The RTL design and verification tasks were greatly
simplified as a result of using this assertion-based methodology because it alleviated the need to
write a thorough testbench reference model prior to debugging the model. During simulation the
assertions immediately alerted us of design and testbench errors. The use of formal verification
tools helped us greatly at quickly detecting errors in the design, along with counterexamples that
5http://www.isixsigma.com/sixsigma/six_sigma.asp

Six Sigma is a disciplined, data-driven approach and methodology for eliminating defects (driving towards
six standard deviations between the mean and the nearest specification limit) in any process -- from
manufacturing to transactional, and from product to service.
6 Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog, Lionel
Benning and Harry Foster, Kluwer Academic Publishers

Preface

xxi

demonstrated the problems without any testbench. Corrections of these errors were quickly
verified with another run of the formal verification tool.
We strongly recommend the use of ABV with SystemVerilog on design projects. ABV is a very
viable methodology for the definition and verification of designs. We must admit though that at
times assertions are very frustrating because they (correctly) insisted that our designs were in
error while we believed that we had all the necessary fixes!!!
Book Organization
Chapter 1 provides an introduction to Assertion-Based Verification and serves as an introduction
to SystemVerilog Assertions (SVA) concepts with emphasis on properties and assertions. It
prepares the readers for Chapters 2, 3, and 4, which represent the core of SystemVerilog
Assertions. Chapter 2 delves into understanding properties, along with the property operators.
Chapter 3 delves into the understanding and application of sequences that represent the real
potential of SystemVerilog Assertions. That chapter addresses the concepts of attempts / threads
of assertions; the definition of the sequence operators; and the rules of local variables. Chapter 4
provides a deeper appreciation of SystemVerilog Assertions by addressing advanced topics for
properties and sequences, including assertion-based functions; clocked sequences and
multiclocking; the SystemVerilog scheduling mechanism used in assertions; the assertion
directives; the immediate assertions; and binding of verification entities to modules. Chapter 5
introduces the new type of entity, the checker. That chapter includes the motivation behind this
new entity, the syntax, its contents, the use model, the rules, and its applications by examples.
Chapter 6 addresses the methodologies in using properties / sequences / assertions during the
requirement and verification planning phases, in addition to the RTL and testbench levels. It first
explains the process, and then demonstrates an application of assertions in the requirements
specification and verification plan using a synchronous First-In First-Out (FIFO) as an
Intellectual Property. SystemVerilog packages, interfaces, modules, and bindings are also
demonstrated. Chapter 7 addresses the formal verification aspects of SystemVerilog Assertions,
and introduces the global clocking functions, typically used in formal verification. Chapter 7
focuses on Formal Verification (FV) methodologies for functional verification of RTL designs. It
provides two case studies verified with OneSpin 360 MV Product Family of formal verification
tools using as testcases a traffic light controller model (an FSM type design) and the FIFO model
(control model with a memory) described in Chapter 6. Chapter 8 provides a summary set of
guidelines in using SystemVerilog Assertions. These guidelines emerged from experience with
usage of Assertion-Based Verification with Accelleras PSL, vendors recommendations, code
reviews, and LRM documentation. Chapter 9 represents a dictionary of classes of application
examples that translate English descriptions of properties to SystemVerilog properties.
Appendix A provides the answers to the exercises asked at the end of Chapter 3. Appendix B is
a summary of terms and definitions used within this book. A list of reserved words is also
provided. The Index provides a page lookup for information available in this book.

All code is available for download

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SystemVerilog Assertions Handbook, 2nd Edition

DISCLAIMER

Every attempt was made to ensure accuracy in the specifications and implementation of the
languages (HDLs and SystemVerilog Assertions) and models. However, all code provided in this
book and in the accompanied website is distributed with *ABSOLUTELY NO SUPPORT* and
*NO WARRANTY* from the authors. Neither the authors nor any supporting vendors shall be
liable for damage in connection with, or arising out of, the furnishing, performance or use of the
models provided in the book and website.
Without permission, use or reproduction of the information provided in this book and on the
linked website for commercial gain is strictly prohibited.

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Acknowledgements
SystemVerilog Assertions Handbook, 2nd Edition could not have been written without the support
and help from several companies who provided us with access to their design and verification
tools that support SystemVerilog, and without the insights of several engineers who helped us in
the review process.
We particularly thank Mentor Graphics for providing us licenses of ModelSim DE and
QuestaSim (a part of the Questa verification platform) both used for the verification of
assertions through simulation. 7 The ease of use of those tools, and the display of results with
concise, but on target, information on the various views helped us in better explaining the
behavior of assertions. Of particular interest was the waveform view that displayed the assertion
signals, assertion successful attempts, vacuity, pass, and fail. The assertion thread viewer was
also of great value as it provided more detailed information about an assertion attempt, its
threads, and the values of its local and related variables. Other valuable outputs provided by the
tool included the assertion / coverage/ cover / covergroup windows. We thank Mentor
Graphics for granting us permission to publish those results in our book and on the distribution
files.
Our sincere thanks are due to Synopsys for providing us access to their VCS platform supporting
many of the SystemVerilog IEEE 1800-2009 features.8 As Synopsys has been in the front line of
defining the new standard, the VCS simulator started supporting many of the LTL features much
before they became part of the IEEE standard. Early access to VCS meant that we could validate
most of our code, and at times clarify our understanding of some of the corner case behaviors of
these new features. This has resulted in several new Mantises being filed for clarification with
the SystemVerilog committee during our book writing journey. The recent simulator version,
along with support for the new LTL constructs and debug enhancements, is bringing most of the
new IEEE 1800-2009 SVA features to be production ready.
We would like to express our gratitude to OneSpin Solutions for providing us with formal
verification analyses and results of two of our RTL models using 360 MV9, OneSpins formal
assertion-based verification (ABV) solution for ASIC and FPGA designs. OneSpins 360 MV
supports a broad range of formal ABV applications including automatic RTL checks, verification
of implementation intent and high-level functional requirements, systematic operation- and
transaction-level design verification, as well as automatic detection of verification gaps in
assertion sets. Surprisingly, the application of 360 MV uncovered several subtle design and
assertion issues in our RTL models that have been missed by previous verifications. The
graphical root cause analysis features of 360 MV were very helpful in understanding and
correcting these issues. We also thank OneSpin Solutions for granting us permission to publish

7 Mentor Graphics provides software and hardware design solutions that enable companies to develop

better electronic products faster and more cost-effectively. They offer numerous products in the area of
chip design and verification. In the area of simulation and assertions, Mentor Graghics provides ModelSim
DE and QuestaSim simulators. http://www.mentor.com
8 The VCS solution powerful debug and visualization environment minimizes the turnaround time to find
and fix design bugs. http://www.synopsys.com/tools/verification/functionalverification/pages/vcs.aspx
9 OneSpins 360 MV product family is a comprehensive formal assertion-based verification solution for
starters, experienced users and experts. 360 MV is based on more than a decade of industrial application
experience and technology development in formal verification. http://www.onespin-solutions.com/

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SystemVerilog Assertions Handbook, 2nd Edition

the results in both the book and the distribution files. We also thank Klaus Winkelmann for
helping us in the formal verification of our models, and in uncovering the issues with our designs.
We thank SpringSoft for supporting us in this endeavor by providing us a license of the Verdi
Automated Debug System, an advanced solution for debugging digital designs and assertions.10
Verdis automated behavior tracing and Behavior Analysis technology, along with its intuitive
visualization of multiple threads, temporal annotation on source code, and the timing annotation
on temporal ranges helped us in demonstrating the inner works of complex assertions.
We thank Aldec for providing us engineering resource for technical review and access to their
Riviera-PRO a high-performance verification platform for ASIC and FPGA designs with ABV
support.11
We thank the IEEE for granting us permission to reproduce some material from the IEEE 1800
LRM, the document that defines the rules of SystemVerilog and SystemVerilog Assertions.
Several SystemVerilog experts participated in the review process of this book. The review is a
necessary step to iron out areas of disagreements, and to provide a piece of work that meets users
requirements in the use of SystemVerilog Assertions. In that endeavor, we sincerely thank the
following people and organizations: Dennis Brophy, from Mentor Graphics for his full support
of our endeavor; Michael Siegel and Klaus Winkelmann, from OneSpin Solutions for their help
and support in verifying two models through OneSpin 360 MV Product Family, and for
valuable feedback on formal verification. We also thank the following engineers for reviewing
our book and providing valuable feedback: Dan Benua, Synopsys; Daniel Mlynek, Aldec; Tapan
Kapoor, Cadence Design Systems; Roy Subir, Texas Instruments.
During the creation of this book there were several language issues and clarifications that needed
to be addresses in the IEEE 1800 SVA committee. Several participants of this committee
contributed to the clarification of issues; thus we particularly thank Dmitry Korchemny, Erik
Seligman, and Ed Cerny.
We also thank Forte Design Systems12 for granting us a license of TimingViewer as a tool to draw
timing diagrams for use in this book.
I (Ben) especially thank my wife, Gloria Jean, for supporting me in this endeavor.
We (Ajeetha & Srini) would like to acknowledge the valuable time our little son Anirudh has
allowed us to spare on this book. I (Srini) would like to personally dedicate this book to my
beloved father Sri. K. Venkataramanan who passed away recently; his memories and blessings
are my sole inspiration to cross any hurdle in my life.
10 The Verdi Automated Debug System is an advanced solution for debugging digital designs that provides

powerful technology to comprehend complex and unfamiliar design behavior; automate difficult and
tedious debug processes; and unify diverse and complicated design environments.
http://www.springsoft.com/products/debug-automation/verdi
11 Riviera-PRO is a high-performance verification platform for ASIC and FPGA design teams, equipped
with mixed-language simulation engine and advanced debugging tools. Riviera-PRO supports Electronic
System Level (ESL) Verification with SystemC and SystemVerilog, Assertions Based Verification (ABV),
Transaction Level Modeling (TLM) and VHDL/Verilog Design Rule Checking.
http://www.aldec.com/Products/default.aspx
12 TimingDesigner is a flexible, interactive timing analysis and diagram tool.
http://www.timingdesigner.com/ http://www.forteds.com/

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Sculpture Created by my Wife Gloria to

Express my Long Hours with a Laptop in the Creation of HDL Books

Preface

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About the Authors

Ben Cohen

is currently a consultant. He has technical experience in digital and analog

hardware design, computer architecture, ASIC design, synthesis, and use of hardware description
languages for modeling of statistical simulations, instruction set descriptions, and hardware
models. He applied VHDL since 1990 to model various bus functional models of computer
interfaces. He authored several books in the field of design and verification languages including
VHDL Coding Styles and Methodologies, first and second edition; VHDL Answers to Frequently
Asked Questions, first and second editions; Component Design by Example; Real Chip Design
and Verification Using Verilog and VHDL; Using PSL/SUGAR with Verilog and VHDL (first
edition, also translated to Japanese); Using PSL/Sugar for Formal and Dynamic Verification, 2nd
Edition; SystemVerilog Assertions Handbook (first edition, also translated into Japanese); and A
Pragmatic Approach to VMM Adoption.
He was one of the pilot team members of the VHDL Synthesis Interoperability Working Group of
the Design Automation Standards Committee who authored the IEEE P1076.6 Standard for
VHDL Register Transfer Level Synthesis. He was a member of the VHDL and Verilog Synthesis
Interoperability Working Group of the Design Automation Standards Committees, and Accellera
OVL and PSL standardization working groups. He participated in the working group for the
development of the new IEEE 1800-2009 LRM for SystemVerilog assertions. He taught several
VHDL, PSL, and SVA training classes.
VhdlCohen Publishing
ben@SystemVerilog.us http://SystemVerilog.us

Preface

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Srinivasan Venkataramanan is Chief Technical Officer (CTO) at CVC Pvt Ltd, a

high-end Design-Verification consulting firm based in Bangalore - India. CVC has been the
pioneer in high-end verification consulting and Corporate trainings on many advanced VLSI
topics. Starting in 2009, CVC productized an internal, time-tested incubation process of bringing
up fresh engineers to be VLSI experts.
Srinivasans areas of interest are the advanced verification solutions and methodologies such as
SystemVerilog, OVM, VMM, Assertion-Based Verification, formal verification etc. As part of
CVC, he provides support to leading edge semiconductor design companies on their verification
methodologies and challenges. CVC differentiates itself against other consulting firms by solving
complex customer problems, such as "time-to-debug", "qualifying verification effectiveness",
"choosing the right technology" for a given problem etc.
In his previous employment at Synopsys, India Private Ltd., Bangalore, he was a Senior Staff
Verification Solutions Engineer where he deployed advanced Verification solutions to many
customers across AsiaPac region including Taiwan, China, India and also Israel. He assisted
customers in variety of areas such as evaluating SystemVerilog, optimizing regressions using
multi-core technologies and showcasing value of VCS verification platform to specifcic domains,
such as Image processing, Networking, DSP etc. Prior to joining Synopsys, he worked at Intel,
Philips Semiconductors, and RealChip communications in the areas of front-end design and
verification of ASICs (leading edge high-speed, multi-million gates ASIC designs) with several
HDLs and HVLs, including VHDL, Verilog, Specman, and Vera. He successfully developed
complex verification environments using advanced methodologies, such as Coverage-Driven
Verification and Constrained-random verification using Verisitys Specman, ABV etc
Srini holds a Masters Degree from the prestigious Indian Institute of Technology (IIT), Delhi in
VLSI Design, and Bachelors degree in Electrical engineering from TCE, Madurai. Srini has coauthored the following books: A Pragmatic Approach to VMM Adoption; Using PSL/Sugar, 2nd
Edition; and SystemVerilog Assertions Handbook.
He presented several papers at conferences and forums such as DesignCon, DVCon, SNUG etc.
He has been delivering trainings on SVA, SVTB, OVM & VMM to customers for more than 5
years.
CVC Pvt.Ltd.,
Bangalore, India
http://www.cvcblr.com/ srini@cvcblr.com

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SystemVerilog Assertions Handbook, 2nd Edition

Ajeetha Kumari is

the founder and CEO and Managing Director of CVC Pvt Ltd, a
high-end Design-Verification consulting firm based in Bangalore - India. At CVC she leads a
team of elite, seasoned Verification professionals focused on next generation verification
automation and productivity techniques. As CEO, her focus is on business development, new
strategic partnerships and exploring new ventures for CVC. She has been providing consultancy
to leading edge semiconductor houses on various verification challenges for over half-a-decade.
Ajeetha is very well networked and known for close interaction with Design-Verification
community on various online forums and events. She presented many papers, tutorials at events
like DVCon, SNUG, CDNLive etc. She has experience with several HDLs and HVLs including
Verilog, VHDL, SystemVerilog, PSL, SystemVerilog Assertions, E and Vera. She co-authored
the following books: A Pragmatic Approach to VMM Adoption; Using PSL/Sugar, 2nd
Edition; and SystemVerilog Assertions Handbook.
She received her M.S. in Electrical engineering from the prestigious Indian Institute of
Technology (IIT), Madras.
CEO & Managing Director
http://www.cvcblr.com/
akumari@cvcblr.com

Lisa Piper is currently an independent consultant for front end verification. Lisa worked for
Cadence Design Systems for 10 years where she was involved with using assertions in
simulation-based verification, adapting OVL assertions for use in acceleration, and formal
verification(a.k.a. model checking). Product definition, training, assertion methodology, and new
product introduction were key aspects of the job. This also included active participation in IEEE
1800-2009 SVA standardization work. Prior to that, Lisa spent 10 years managing the definition
and applications support of Telecom IC's, LAN IC's, and ATM IC's at Lucent Microelectronics.
This built upon previous experience at AT&T Bell Labs co-developing the first ISDN S/T
Interface chip and designing ISDN phones. Lisa holds an MSEE from Ohio State University.
lisa_piper@systemverilog.us