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    Intel 8086 and Support Chips: Appendix

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    Lascu Mihai Sebastian
    8086 is a new generation, high performance microprocessor implemented in N-channel. Depletion load. Silicon gale IeChnolOgy (HMOS) and packaged in a 40.pin CerOlP package. The processor has attributes of both 8. And 16-bit microprocessors It addresses memory a s a sequence of 8-blt bytes. But has a 16.bil wide physlcal path to mem. Ory tor high performance

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    Intel 8086 and Support Chips: Appendix

    Uploaded by

    Lascu Mihai Sebastian
    61 views6 pages
    8086 is a new generation, high performance microprocessor implemented in N-channel. Depletion load. Silicon gale IeChnolOgy (HMOS) and packaged in a 40.pin CerOlP package. The processor has attributes of both 8. And 16-bit microprocessors It addresses memory a s a sequence of 8-blt bytes. But has a 16.bil wide physlcal path to mem. Ory tor high performance

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    8086 is a new generation, high performance microprocessor implemented in N-channel. Depletion load. Silicon gale IeChnolOgy (HMOS) and packaged in a 40.pin CerOlP package. The processor has attributes of both 8. And 16-bit microprocessors It addresses memory a s a sequence of 8-blt bytes. But has a 16.bil wide physlcal path to mem. Ory tor high performance

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    61 views6 pages

    Intel 8086 and Support Chips: Appendix

    Uploaded by

    Lascu Mihai Sebastian
    8086 is a new generation, high performance microprocessor implemented in N-channel. Depletion load. Silicon gale IeChnolOgy (HMOS) and packaged in a 40.pin CerOlP package. The processor has attributes of both 8. And 16-bit microprocessors It addresses memory a s a sequence of 8-blt bytes. But has a 16.bil wide physlcal path to mem. Ory tor high performance

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6
    At a glance
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    The key takeaways are that the document discusses several Intel chips that support microprocessors including the 8086, 8288, 2732, and 8255A.

    The Intel 8086 is a 16-bit microprocessor that can address memory as bytes but has a 16-bit data path. It has attributes of both 8-bit and 16-bit processors and features include direct memory access up to 1MB, arithmetic operations, and 24 addressing modes.

    The Intel 8288 bus controller provides command and timing generation as well as bipolar bus driving capability. It optimizes system performance and can be configured for use with a multi-master system bus and separate I/O bus.

    Fundamentals of Digital Logic andhficrocomputer Design. M. Rafiquzzaman Copyright 02005 John Wiley & Sons, Inc.

    APPENDIX

    INTEL 8086 AND SUPPORT CHIPS

    808618086-2/8086-4 16=BITHMOs MICROPROCESSOR


    Direct Addressing Capability to 1 MByte of Memory
    rn Assembly Language Compatible with

    rn Blt, Byte, Word, and Block Operations


    rn &and 16-Bll Signed and Unsigned

    808018085

    Arithmetic in Binary or Decimal including Multiply and Divide

    14 Word, By 16-Bit Register Set with Symmetricel Operations


    rn 24 Operand Addressing Modes

    5 MHz Clock Rate (8 MHz for 6086.2) (4 MHt for 8086.4)


    rn MULTIBUSTM System Compatible

    interface

    The Intel@ 8086 is a new generation, high performance microprocessor implemented in N-channel. depletion load. Silicon gale IeChnolOgy (HMOS). and packaged in a 40.pin CerOlP package. The processor has attributes of both 8. and 16-bit microprocessors It addresses memory a s a sequence of 8-blt bytes. but has a 16.bil wide physlcal path to mem. Ory tor high performance.

    40 LEAD

    8086 Pln Dlrgrim

    67 1

    672

    Fundamentals of Digital Logic and Microcomputer Design

    CL0C.C GENERATOR AP.D DRIVER FOR 8086,8088,8089 PROCESSORS


    Generates the System Clock for the 8086, 8088 and 8089
    m Uses a Crystal or

    I8284

    quency Source Single

    a TTL Signal for Fre-

    + 5V Power Supply

    18-Pin Package

    Generates System Reset Output from Schmltt Trigger Input Provides Local Ready and MULTIBUSTM Ready Synchronization Capable of Clock Synchronization with other 8284's Industrial Temperature Range -40' to +85'C

    The 18284 I S a bipolar clock generatoridrlver designed lo provide clock signals for the 8086, 8088 & 8089 and systems and prowdes the processors peripherals It also contains READY logic for operation wllh two MULTIEUSTM required READY synchronization and timlng Reset loglc with hysteresis and synchronizatlon is also provided

    I8284 PIN CONFIGURATION

    18284 BLOCK DIAGRAM

    CIIW

    ---t=kJ

    ii,
    ICNK

    18284 PIN NAMES


    fONNECTlONS FOR C R Y S l l L USED WITH O V E I T O N C CRYSTAL CLOCR SOURCE SELECT EXTERNAL CLOCK INPUT CLOCK SYNCWROHIZCTION INPUl RECDV SIGNAL FROM TWO HULTIIUS'" SYSIEHS

    Fle

    t::i: R x
    CLI

    EFl CSINC

    :2 s
    ~

    AOORESS ENABLE0 OUCLIFIERS FOR R O I t I

    RESEl OSC
    K L K READY

    vcc

    RESET IHPUT SVNCHROHIZED R E 5 E l OUTPUT OSCILLATOR OUTPul MOS CLOCK FOR THE PROCESSOR TTL CLOCK FOR PfRlPYERALS SYNCHRONIZED REAOV O U I Q U l . 5 VOLTS

    GND

    OYOLTS

    Appendix E: Intel 8086 and Support Chips

    673

    inu"
    B

    8288 BUS CONTROLLER FOR 8086,8088,8089 PROCESSORS


    %State Command Output Drivers Configurabie for Use with an 10 Bus 1 Facilitates Interface to One or Two Multi-Master Busses

    Bipolar Drive Capability Provides Advanced Commands

    m Provides Wide Flexibility in System

    Configurations

    The Intel@ 8288 Bus Controller is a 20.pin bipolar component for use with medium-to4arge 8086 processing Systems. The bus controller provides command and control timing generation as well as bipolar bus drive capability while optimizing system performance.

    A strapping option on the bus controller configures i t for use with a multi-master system bus and separate 10 bus. 1

    PIN CONFIGURATION

    BLOCK DIAGRAM

    Sl

    s2

    5)

    --

    DECODEn SIGNAL GENER

    LYUC

    iORC IOWC AIOWC

    COYYAWD IICWALS

    YULTIBUS'"

    FUNCTIONAL PIN-OUT

    t5V

    OND

    COYYANO

    nus

    674

    Fundamentals of Digital Logic and Microcomputer Design

    in@@ 32K (4K x 8) UV2732 ERASABLE PROM


    m Fast Access Time:

    - 550 ns Max. 2732-6 - 450 ns Max. 2732


    Slngle +5V f 5% Power Supply Output Enable for MCS-85'" and MCS-86'" Compatibility

    Pin Compatlble to Intel@2716 EPROM Completely Static

    m Simple Programming Requirements

    - Single Location Programmlng

    Low Power Dlsslpation:

    - Programs with One 50ms Pulse

    150mA Max. Actlve Current 30mA Max. Standby Current

    Three-State Output for Direct Bus Interface

    The IntelQ 2732 is a 32.768-bit ultraviolet erasable and electrically programmable read-only memory :EPROMi. The 2732 operates from a single 5volt power supply, has a standby mode. and features an output enable control. The total program. ming time for all bits is three and a half minutes. All these features make designing with the 2732 in microcomputer systems faster, easier, and more economical. An important 2732 feature is the separate output control, Output Enable I F E I ,from the Chip Enable control The@ Control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-30 describes the and controls on Intel's 2716 and 2732 EPROMs. AP-30 is avallable microprocessor system implementation of the from Intel's Literature Department.

    o ?

    ,=

    The 2732 has a standby mode which reduces the power dissipation without increasing access time. The maximum active current is 150mA. while the maximum standby current is only 30mA. an 80% savings. The standby mode is achieved by input. applying a TTL-high signal to the

    PIN CONFIGURATION
    (181
    Read Standby

    i5ENpp I201
    VII Don't Care

    vcc
    (24

    (911.1117l
    Lhir

    OUTPUTS

    VII VIH

    +5
    +5 +5

    High Z

    Program Vsrofy

    VIL

    V I ~

    Dour
    I

    BLOCK DIAGRAM

    PIN NAMES

    Appendix E: Intel 8086 and Support Chips

    675

    8255AI8255A-5 PROGRAMMABLE PERIPHERAL INTERFACE


    rn MCS.85TYCompatlble 8255A-5

    24 Programmable 10 Pins 1 Completely TTL Compatible


    8

    Dlrect Blt SeUReset Capablllty Easing Control Application Interface 4QPln Oual In-Llne Package

    Fully Compatible with Intel@Micro processor Families Improved Tlmlng Characteristics

    m Reduces System Package Count

    m Improved DC Driving Capability

    The lntela 8255A is a general purpose programmable 10 device designed for use with Intel. microprocessors. I1 has 1 24 1 0 1 pins which may be individually programmed in 2 groups of 12 and used In 3 major modes of operalion. In the flnt mode (MODE O), each group of 12 UO pins may be programmedin sets of 4 to be input or output. In MODE 1, the second mode, each group may be programmed to have 8 lines of input or outpul. Of the r w t i i n h g 4 pins, 3 are used for hand. shaking and interrupt control signale. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8 lines lor a bidirectional bus, and 5 lines. borrowing one from the other group, for handshaking.

    PIN CONFIGURATION

    PIN NAMES

    0 -

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