A3 1 1IntroductionFlipFlops

Activity 3.1.
1 Introduction to Flip-Flops
Introduction
Flip-flops; not the sandals, but the logic gates, are the fundamental building blocks of sequential logic. There are a variety of different flip-flop types and configurations. In this activity, and this course for that matter, we will only be studying two, the D flipflop and the J/K flip-flop. After reviewing the basic operation of the 74LS74 D and the 74LS76 J/K flip-flips, this activity will examine two introductory applications of flipflops. Note: Where did the flip-flops get their name? The D in the D flip-flop stands for data. No one is absolutely sure where the J/K name originated, but one theory is that it is named after Jack Kilby, the inventor of the integrated circuit.
Equipment
Paper and pencil Circuit Design Software (CDS)
Procedure
Before we jump into a discussion of practical applications of J/K or D flip-flops, let first make sure that you have a solid understanding of how these flip-flops work. 1. For the 74LS74 D flip-flop shown below, complete the timing diagram for the output signal Que. Note that the CLK input for this flip-flop is a positive edge trigger and both the PR and CLR asynchronous inputs are active low.
Project Lead The Way, Inc. Copyright 2009 DE Unit 3 Lesson 3.1 Activity 3.1.1 Introduction to Flip-Flops Page 1
Que Dee Preset Clear Clock
2. For the 74LS76 J/K flip-flop shown below, complete the timing diagram for the output signal Que. Note that the CLK input for this flip-flop is a negative edge trigger and both the PR and CLR asynchronous inputs are active low.
Que Jay Kay Preset Clear Clock
Lets examine some simple applications of the D and J/K flip-flops. 1. When flip-flops were discussed briefly back in unit (1), we saw that a D flip-flop could be used to create a Divide-By-Two circuit. Remember, a Divide-By-Two circuit is one that generates a clock output that is half the frequency of the clock input. Likewise, a Divide-By-Two circuit can be implemented with a J/K flip-flop. See below.
J/K Divide-By-Two Circuit a. Complete the timing diagram shown below for a J/K Divide-By-Two circuit.
Clock_Out Clock_In
b. Using the CDS, enter the Divide-By-Two circuit. Add an oscilloscope to monitor the two signals Clock_In and Clock_Out. Run the simulation and capture several periods of the output signal. Verify that the circuit is working as expected and that the output signal matches the predictions from step (a). If the results do not match, review your work and make any necessary corrections.
c. Change the frequency of Clock_In to 20 KHz and re-simulate. What effect did this change have on the frequency of the output signal Clock_Out? 2. The circuit shown below generates two non-overlapping signals at the same frequency. These signals, C-OUT1 and C-OUT2, were frequently used by early microprocessor systems that required four different clock transitions all synchronized by one clock.
Non-Overlapping Signal Generator a. Complete the timing diagram shown below for the Non-Overlapping Signal Generator circuit.
C-OUT2 C-OUT1 Que_Not Que Clock
b. Using the CDS, enter the Non-Overlapping Signal Generator circuit. Add an oscilloscope to monitor the three signals Clock, C-OUT1, and C-OUT2. Run the simulation and capture several periods of the output signals. Verify that the circuit is working as expected and the output signals match the predictions from step (a). If the results do not match, review your work and make any necessary correction. c. The input signal, Clock, was a 1 KHz square wave with a 50% duty cycle. What is the frequency and duty cycle of the output signals C-OUT1 and COUT2? d. Change the frequency of Clock to a 2 KHz and re-simulate. What effect did this change have on the frequency of the output signals C-OUT1 and C-OUT2? What effect did this change have on the duty cycle of the output signals COUT1 and C-OUT2?
Conclusion
1. Flip-flops have both synchronous and asynchronous inputs. Describe each input type and give an example of each.
2. Match each of the four input symbols with their signal type. Active Low Input Negative Edge Trigger Active High Input Positive Edge Trigger
3. Describe the functional difference between a D flip-flop and a D latch.

A3 1 1IntroductionFlipFlops

Uploaded by

Copyright:

Available Formats

A3 1 1IntroductionFlipFlops

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

A3 1 1IntroductionFlipFlops

Uploaded by

Copyright:

Available Formats

What are the two types of flip-flops covered in the document?

What are two applications of flip-flops described in the document?

Activity 3.1.

Que Dee Preset Clear Clock

Que Jay Kay Preset Clear Clock

3. Describe the functional difference between a D flip-flop and a D latch.

You might also like