ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6, December 2012

Designing of Charge Pump for Fast-Locking and Low-Power PLL

Swati Kasht, Sanjay Jaiswal, Dheeraj Jain, Kumkum Verma, Arushi Somani
Abstract The specific property of fast locking of PLL is required in many clock and data recovery circuits. Many researchers [1], [3], [5] have tried to reduce this locking time but at the expense of power, phase noise and jitter. This paper presented a PLL with redesigning of individual blocks like- PFD is designed using edge triggered D flip flop to reduce area and static phase error, CP is designed using current mirrored structure to minimize the current mismatch with increased output voltage and VCO has been designed using self bias differential ring oscillator to achieve low jitter operation of PLL. The PLL is designed using 180 nm CMOS technology for high performance with 1.0 V power supply. Keywords charge pump (CP), power delay product (PDP), phase frequency detector (PFD), Phase locked loop (PLL), voltage controlled oscillator (VCO).

Many researchers have tried to design PLL which offers either of the following property- low power consumption, fast locking, high speed, less jitter, less phase noise and hence less area or even grouping of them. However, the two design criteria are often in conflicts and improving one particular aspect of the design constrains the other. The need of high performance PLL gives rise to redesign of individual blocks in PLL. This paper presents a PLL with designing of each block to achieve fast locking time with reduced power consumption, less jitter and phase noise [8]. This paper summarizes the detail study of PLL with its individual blocks using Tanner Tool in 180nm CMOS technology. Section II presented basics of PLL. Section III explained Implementation of PLL circuits. Simulation results are described in Section IV. Finally the conclusion of the paper is given in Section V. II. BASICS OF PLL A PLL is a feedback system as shown in figure 1, compares the output signal with the input signal. The comparison is performed by a phase frequency detector. The basic building blocks of a Phase locked Loop (PLL) are Phase frequency detector (PFD), Charge Pump (CP), Low Pass Filter (LPF) and Voltage Controlled Oscillator (VCO) in a feedback loop through a frequency divider [8].

I. INTRODUCTION A Phase lock loop (PLL) is a closed loop control system which synchronizes an output signal with input signal in terms of frequency and phase. This synchronized state is referred as locked state of PLL [8]. The PLL are widely employed in clock generation, frequency multiplication, clock and data recovery circuits and distribution of timing pulses. At this locked state, the phase and the frequency deviation between output and input signal is ideally zero or constant but in practical, frequency remains same but small phase error occurs in the output signal [11]. The time at which PLLs output frequency matches the input frequency is known as locking time of PLL. This fast locking property is required in many clock and data recovery circuits.

Manuscript received Nov 19, 2012. Swati Kasht, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: swati.kasht.26@gmail.com). Sanjay Jaiswal, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: to.sanjay1985@gmail.com). Dheeraj Jain, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: dheeraj.suryamtech@gmail.com). Kumkum Verma, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: kumkum.verma1983@gmail.com). Arushi Somani, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: arushisomani@gmail.com).

Fig.1 Basic block diagram of Phase locked Loop [8] The role of phase frequency detector is to generate a digital signal (difference or error signal) which drives the charge pump to either increase the control voltage of the VCO or decrease it or keep it without change [10]. The charge pump then converts this digital signal into an analog signal. This analog signal has high frequency (undesired) signal as well as low frequency (desired) signal. Then this high frequency signal is filtered out by a low pass filter and applied to the voltage controlled oscillator. This VCO output frequency (fout) is divided by the divider N.

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6, December 2012 When the phase and frequency of input (fin) and the divider output (fD) are aligned then the loop is said to be locked i.e. fin = fD Where fD = fout / N and fout = frequency of output signal. At this state the control voltage of the oscillator must remain constant. III. IMPLEMENTATION OF PLL CIRCUIT A. Phase Frequency Detector (PFD) As the name suggest that the phase detector and the frequency detector are merged, such that it can detect both phase and frequency differences. It is only possible for the periodic signals [11]. It consists of two edge-triggered resettable D-flip-flops with their D inputs connected to logic 1. The reference frequency signal (A) and the signal derived from its divider output (B) form the two inputs of the flip-flops and QA (UP) and QB (DOWN) are the outputs [7]. This circuit shown in figure 2 compares the phase and frequency of these two input signals and generates an error signal which is proportional to the phase deviation between them. The proposed charge pump implementation is shown in figure 3. This circuit consists of UP and DN switches like M1 and M2, current source transistors are M3 and M4, a variable current reference providing current Icp and current mirrors transistors are M5-M9. The dummy transistors M10-M12 are used to match the voltage drop across the switches, so that the current reference can be accurately mirrored to M3 and M4.

Fig.3 Schematic diagram of proposed Charge Pump C. Low Pass Filter It is imperative to note that the output translated from the phase detector output consists of a undesirable high-frequency components and a desirable dc component. Thus, the low pass filter is one of the key design components which serve to effectively filter out the undesired AC component and provides a steady control voltage or the dc level to operate the VCO [8]. D. Voltage Controlled Oscillator The voltage controlled oscillator is the circuit block where the control voltage of CP controls the oscillators output frequency so that it matches the reference signal frequency [9]. This VCO is designed using self bias ring oscillator to reduce jitter in PLL [6]. A ring oscillator is a closed loop cascade connection of odd number of inverters, where the output node of the last inverter is connected to the input node of the first inverter. The schematic diagram of this VCO is shown in figure 4.

B. Proposed Charge Pump (CP) The charge pump is the heart of the PLL. To further reduce the error signal to a very small value a charge pump is used between the phase frequency detector and the low pass filter as an amplifier. It transfers the digital signals from phase/frequency detector (PFD) to an analog signal for controlling the voltage-controlled oscillator (VCO). The frequency of voltage control oscillator (VCO) is controlled by the output signal of charge pump circuit [9]. The output voltage of the charge pump circuit must be held on a constant voltage. The objective is to obtain minimum power dissipation with a large output voltage range under a low power supply [9].

Fig.4 Schematic diagram of Current starved voltage controlled oscillator [1]

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6, December 2012 E. Frequency Divider Table I: Simulation Result for proposed Charge Pump The output of the VCO has to be divided before it is fed Values back to the input of the PLL. A programmable divider circuit Parameters as shown in figure 5 is used, which receives a reference clock Power Supply (Vdd) 1.0 V signal of a predetermined frequency and is structured to Output Voltage 1.045 V divide the reference clock signal by N and provide an output Power Consumption 0.127mW pulse signal for every N cycles of reference clock signal [2].

Delay PDP No of Transistors Technology

19.425ns 2.46ps 64 180nm

Another block of PLL is VCO whose characteristic shows a linear relationship between VCO voltage and frequency and the frequency range is given by the linearity in the characteristic curve as shown in figure 7.

Fig.5 Frequency divide-by-2 counter [2] IV. SIMULATION RESULTS To achieve good PLL performance a charge pump is proposed which has following characteristics: Increased output voltage. This charge pump show charging waveform when UP signal is high and discharging when DOWN signal triggers high. Low Power consumption. The output waveform and simulation result of proposed charge pump is shown in figure 6 and Table I respectively.

Fig.7 Characteristic of VCO The output frequency of VCO is divided by the frequency divider which produces output pulse for every two cycles of input pulse as shown in figure 8.

Fig.8 Output waveform of frequency divider Thus by combining all these individual blocks a PLL is proposed which has following properties: Very less locking time Low power consumption Less Delay Reduced phase noise Less Jitter

Fig.6 Output Waveform of proposed charge pump

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6, December 2012 In the output waveform of proposed PLL, shown in figure 9, the frequency of reference clock (fA) is same as the frequency of the divider output (fdiv) at the time 554 ns. This is called the locked state as mentioned earlier. At this state the control voltage of VCO (Vcontrol) remains constant. Phase noise performance of PLL shown in figure 10 is also analyzed in this work. The phase noise is decreased with increase in frequency.
Power Consumption Delay Power Delay Product Phase Noise at 100 KHz Jitter 0.38mW 6.5 ns 2.47ps -98.14 dBc/Hz 159.5ps 4.1mW 160ps 16.38mW -107 dBc/Hz 19.8mW -89.92 dBc/Hz -

V. CONCLUSION In this paper fast locking and low power PLL has been designed and simulated using 180 nm CMOS technology of tanner tool and for the analysis of phase noise and jitter an another software named as National Clock Design tool is used. For these specific properties of PLL a charge pump of current mirrored structure of increased output voltage and low power consumption is used with appropriate parameters of PFD, LPF and VCO. Thus the PLL is designed with a very less locking time of 554ns and it is observed to consume a power of 0.38mW with a root mean square (RMS) jitter of 159.5ps and a phase noise of -98.14dBc/Hz at 100 kHz. REFERENCES
[1] P. K. Rout, B. P. Panda, D. P. Acharya and G. Panda, Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition International Conference on Electronic Systems, National Institute of Technology, Rourkela, pp.212-215,January 2011. [2] Jayabalan Ramesh, Ponnusamy Thangapandian Vanathi, and Kandasamy Gunavathi, Fault Classification in Phase-Locked Loops Using Back Propagation Neural Networks ETRI Journal, Vol. 30, No. 4, pp.546-554, August 2008. [3] H. Hedayati, B. Bakkaloglu, A 3 GHz Wideband Fractional-N Synthesizer with Switched-RC Sample-and-Hold PFD IEE Transactions on very large scale integration (VLSI) Systems, pp.1-10, June 2011. [4] Wei-Hao Chiu, Yu-Hsiang Huang, Tsung-Hsien Lin, A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops IEEE Journal of solid-state circuits, Vol. 45, No. 6, pp. 1137-1149, June 2010. [5] Kuo-Hsing Chen, Huan-Sen Liao, Lin-Jiunn Tzou, A Low-Jitter and Low-Power Phase -Locked Loop Design IEEE pp. 257-260, 2000. [6] Jianbin Pan, Yuanfu Zhao, Design of a Charge-Pump PLL for LVDS SerDes International multi conference of Engineers and Computers Scientists, Vol. II, March 2010. [7] Bortecene Terlemez and John P. Uyemura, The design of a differential CMOS Charge pumps for high performance phase-locked loops IEEE pp. 561-564, 2004. [8] Abishek Mann, Amit Karalkar, Lili He, and Morris Jones, The Design of A Low-Power Low-Noise Phase Lock Loop IEEE, pp. 528-531, 2010. [9] Jyoti Gupta, Ankur Sangal, Hemlata Verma, High Speed CMOS Charge Pump Circuit for PLL Applications using 90nm CMOS Technology IEEE, pp. 346-349, 2011. [10] Nesreen Ismail, Masuri Othman, A Simple CMOS PFD for High Speed Applications European Journal of Scientific Research, Vol 33, No. 2, pp. 261-269, 2009. [11] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata-McGraw Hill 2002, Ch. 15, pp. 532-578.

Fig.9 Proposed PLL output waveform

Fig.10 Phase Noise Characteristic The design performance of the PLL is summarized in Table II. Table II. Result comparison with proposed PLL
Parameters Technology Supply Voltage Input Frequency Range VCO Frequency Range Divider Locking Time Result of Current work 180nm 1.0 V 40 MHz to 70 MHz 80 MHz to 140 MHz 2 554ns Result reported in [5] 500nm 3.0 V 50MHz to 162 MHz 200MHz to 650 MHz 17.1s Result reported in [3] 180nm 1.8 V 38 MHz 3 GHz 10s Result reported in [4] 180nm 1.8 V 10 MHz 5.27 GHz 20s

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ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6, December 2012
Authors Profile: Swati Kasht received her B.E degree in Electronics and Communication Engineering with honors from Rajasthan University, Jaipur in 2009, and pursuing M.Tech in VLSI Design from Rajasthan Technical University, Kota. Her research interests are Analog and Digital Integrated Circuit Design, Biomedical, Wireless Communication, and Microprocessor. Sanjay Kumar Jaiswal received his M.Tech. Degree in VLSI Design from the Centre for Development of Advanced Computing (C-DAC), Ministry of I.T. Government Noida. He is an Assistant Professor in Electronics and Communication Engineering, from Institute of Technology and Management Bhilwara (Rajasthan). His field of interest includes VLSI Design, Communication system, Null convention Logic Design, SRAM Memory Design, and Sense Amplifier. He is also a member of IETE, Delhi. Dheeraj Jain received his M.Tech. Degree in VLSI Design from the Centre for Development of Advanced Computing (C-DAC), Ministry of I.T. Government Noida. He is an Assistant Professor in Electronics and Communication Engineering, from Institute of Technology and Management Bhilwara (Rajasthan). He is pursuing Ph.d from Dr. K.N. Modi University (Raj.). His field of interest includes VLSI Design, Communication system, Electronics Devices and Circuit, and Embedded System. Kumkum Verma received her M.Tech. Degree in VLSI Design from the Centre for Development of Advanced Computing (C-DAC), Ministry of I.T. Government Noida. She is an Assistant Professor in Electronics and Communication Engineering, from Institute of Technology and Management Bhilwara (Rajasthan). Her field of interest includes VLSI Design, SRAM Memory Design, Communication system, Null convention Logic Design, and Sense Amplifier. She is also a member of IETE, Delhi. Arushi Somani received her B.E degree in Electronics and Communication Engineering with honors from Rajasthan University, Jaipur in 2007, and pursuing M.Tech in VLSI Design from Rajasthan Technical University, Kota. Her research interests include digital integrated circuit design, Signal and System, Digital Signal Processing, Wireless Communication and Microprocessor.

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