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Implementation of Frequency Demodulator Using The PLL Demodulation Method

1. The document describes the implementation of an FM demodulator using a Phase Locked Loop demodulation method. An IC LM565 PLL is used for FM demodulation. 2. The demodulator circuit consists of two main sections - the FM demodulation section using the LM565 PLL IC, and an output audio amplifier section to amplify the demodulated audio signal. 3. Experimental results show that the PLL demodulator is able to successfully demodulate FM waves with carrier frequencies between 200kHz to 7MHz, extracting the audio information signal around 1.2kHz.

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0% found this document useful (0 votes)
488 views

Implementation of Frequency Demodulator Using The PLL Demodulation Method

1. The document describes the implementation of an FM demodulator using a Phase Locked Loop demodulation method. An IC LM565 PLL is used for FM demodulation. 2. The demodulator circuit consists of two main sections - the FM demodulation section using the LM565 PLL IC, and an output audio amplifier section to amplify the demodulated audio signal. 3. Experimental results show that the PLL demodulator is able to successfully demodulate FM waves with carrier frequencies between 200kHz to 7MHz, extracting the audio information signal around 1.2kHz.

Uploaded by

asmonov
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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NCCI 2010 -National Conference on Computational Instrumentation CSIO Chandigarh, INDIA, 19-20 March 2010

IMPLEMENTATION OF FREQUENCY DEMODULATOR USING THE PLL DEMODULATION METHOD


Patel Janakkumar B. , R.S.Anand ,Patel Nilam J. Indian Institute of Technology Roorkee, Janakbpatel71@gmail.com.
Abstract: There are many methods available for FM demodulation like slope detector, Foster-Seeley discriminator, Phase Lock Loop detector, Quadrature method, Ratio detector. In our project we are using the PLL demodulation method using IC LM565 which is FM demodulation IC. The LM565 and LM565C are general purpose phase locked loops containing a stable, highly linear voltage controlled oscillator for low distortion FM demodulation, and a double balanced phase detector with good carrier suppression. The VCO frequency is set with an external resistor and capacitor, and a tuning range of 10:1 can be obtained with the same capacitor. The characteristics of the closed loop systembandwidth, response speed, capture and pull in rangemay be adjusted over a wide range with an external resistor and capacitor. The loop may be broken between the VCO and the phase detector for insertion of a digital frequency divider to obtain frequency multiplication. Available TTL and DTL compatible phase detector input and square wave output. After the demodulation it follows, amplifier stage. In this amplifier stage IC TBA810 is used. This demodulator can work up to 10 mega Hz frequency. All this IC required 5,-5.15,-15 DC supply externally. The main aim of this project is to study MULTISIM and ULTIBOARD software and run & simulate our project in MULTISIM and how to make circuit layout of the required circuit. MULTISIM, Aimspice, Free PCB & Ultiboard softwares are utilized for implementation of circuit & PCB layout. Keywords: PLL (Phase Locked Loop),VCO(Voltage Control Oscillator),TTL(Transistor Transistor Logic)

1. FM DEMODULATION The process of removing the information signal from the carrier is termed demodulation. The challenge is to design a circuit (or algorithm) that will achieve this task optimally in the presence of noise, interference and varying signal strength, frequency and phase, whilst being compact, power efficient and cheap. To detect an FM signal, it is necessary to have a circuit whose output voltage varies linearly with the frequency of the input signal. The slope detector is a very basic form of such a circuit, although its linearity of response is not a good. The tuning circuit tune to receive the signal on the slope of the response curve. The carrier amplitude is caused to vary with the frequency. There are four methods for the frequency demodulation technique. These are as follows: 1. Foster-Seeley Discriminator 2. Ratio Detector 3. Phase Lock Loop Detector 4. Quadrature Detector Here IC LM565 is used as a Phase Lock Loop Detector. Mainly two sections are present as follows: 1. FM Demodulation by PLL. 2. Output audio amplifier section. 2. FM DEMODULATION BY PLL An IC565 PLL is used for FM demodulation. It contain voltage controlled oscillator which produces the frequency, which is proportional to the voltage

applied to it. The frequency of oscillation is determined by resistance and capacitance at pin 8 and 9 by 4k7 preset. IC TBA810 is used as output audio amplifier.

The block diagram for Phase locked loop demodulator is shown in fig. The phase detector which is basically balance modulator, produce an average output voltage that is a linear function of the phase difference between the two input signals .The frequency component is selected by the low pass filter which also remove much of the noise. The filtered signal is given is amplified through amplifier A and pass as a control voltage to the VCO where it result in frequency modulation of the VCO frequency .When the loop is in lock the VCO frequency follows or track the incoming frequency .For example when the instantaneous frequency increases. The control voltage will cause the VCO frequency to increase.

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NCCI 2010 -National Conference on Computational Instrumentation CSIO Chandigarh, INDIA, 19-20 March 2010
3. OUTPUT AUDIO AMPLIFIER SECTION: The Output audio amplifier consists of Pre-amplifier and output amplifier stage. This section is used to amplify low-level audio signal coming from Mike/Loudspeaker and give it to the F.M. modulator section for live F.M. modulation. The pre-amplifier consists of one transistor Q1. Transistor Q1 is connected in C-E configuration. The input signal from mike is connected to the base of Q1 through coupling capacitor 10/16 EC. The amplified audio signal obtained at the collector of Q1 is given to the output driver amplifier consisting of IC 810 at pin 10 through volume control pot P1. The IC 810 performs the functions of the audio amplifier, driver and the o/p stage. The amplified signal obtained from the transistor Q1 is given at the audio input (pin 10) of the IC. This amplified by the IC and the o/p is available at the pin 16 of the IC. The feedback is given from the output to the emitter of pre-amplifier transistor in the IC (through resistor 4k provided internally).The feedback voltages develops over R6 (22), C12 (220/10) being used for dc blocking at pin 8.the gain of amplifier depends on this feedback. The amplified output is available at pin 16 and in turn at output terminals. 4. CIRCUIT DIAGRAM 8) 220k: 1 8) 470f/16V 9) 1k : 1 10) 22 : 1 11) 100: 1 12) 1 : 1 13) 1, 0.5w: 1 14)330k : 1 PRESETS : 1) 10k pot ICs: 1) 810 ( audio amplifier) 2) 565( fm demodulator) 3) 741 ( amplifier) :2

6. SPECIFICATIONS 1) Power supply requirement : +5,-5,+15,-15 DC 2) On board RF carrier signal generator : 200 KHz to 1 MHz (VCO) frequency range 3) Demodulator type : Phase lock loop 4) Vp-p 0 to 5v 5) On board input audio amplifier with volume control for modulating external signal from mike. 7. EXPERIMENT RESULT Frequency modulated waves:

Resistor 1) 100k: 1 2) 22k: 2 3) 10k: 1 4) 4k7 : 1 5) 1k5 : 1 6) 47k : 4 7) 1 : 1

5. COMPONENTS Capacitors 1) 47Nf dc 2) 1nf dc 3) 1nf ppc 4) 330pf dc 5) 470pf 6) 10f/16V 7) 220f/16V

:1 :1 :1 :1 :1 :2 :3

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NCCI 2010 -National Conference on Computational Instrumentation CSIO Chandigarh, INDIA, 19-20 March 2010
DIAGRAM:

Fig. shows the frequency modulated waves. It can be seen that frequency of carrier signal varies with respect to the amplitude of information signal. The output frequency of fm modulator varies between 200 kHz to 7 MHz.. The above waveform shown in the fig. is applied to the PLL demodulator whose output is shown in the below fig. As shown in the fig. we get the information signal whose frequency is near about the modulating signal. Frequency of information signal Frequency of FM wave MHZ Frequency of PLL output : 1.4 KHz : 200 KHz to 7 The 565 is a bipolar chip that, like the 4046, contains a phase detector and a VCO. These modules are not completely separate, as they are in the 4046, so they are a little more difficult to experiment with individually. The input to the 565 is intended to be a sine wave, or something similar, so the phase detector is designed accordingly. It is a doublebalanced modulator, and does for analog signals essentially what the XOR gate does for square waves. It is a Type I phase detector, with a range of 0 to 180 in phase. The circuit is shown at the left. The inputs at pins 2 and 3 of the 565 are directly to the bases of the input transistors. The square wave from the VCO switches the transistors that are conducting at any moment, and the outputs are taken differentially from the collectors. There is a minimum output for zero phase difference, and a maximum for anti phase. The output is sent through amplifying circuits directly to the VCO, whose DC input appears at pin 7. This is from 8 to 10 V, so a reference voltage is output at pin 6 to make connection with op-amps easier. The loop filter is connected between pin 7 and VCC (not ground). At its simplest, it is simply a capacitor of fairly large capacitance. A lead-lag filter can be made by connecting a resistance in series with this capacitor, also adding a smaller capacitor directly from pin 7 to +V. There is an internal 3.6k resistance in series with pin 7 that provides R3. The 565 can be used at supply voltages up to 12 V, and will function up to 100 kHz or so. In the experiment, we use 12 V, because that is what we have, but the data sheets suggest that 6 V is more typical. The center frequency is set by Rt and Ct, and will be not far from fo = 1 / 3.7RtCt. The formula is correct, but the graph in the data sheet was incorrect (this was an old data book; there may be a correction). The values used in the experiment below gave 27.88 kHz, while the calculated value was 27.03 kHz. A circuit for studying the 565 is shown at the right. Note that both inputs are returned to ground through 470O resistors, so there is no

: 1.2 KHz

8. IC LM565 200 ppm/C frequency stability of the VCO Power supply range of 5 to 12 volts with 100 ppm/% typical 0.2% linearity of demodulated output Linear triangle wave with in phase zero crossings available TTL and DTL compatible phase detector input and square wave output

Adjustable hold in range from 1% to > 60%

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NCCI 2010 -National Conference on Computational Instrumentation CSIO Chandigarh, INDIA, 19-20 March 2010
trouble with bias currents to the bases, and the input from the function or signal generator is through a coupling capacitor. Set the signal source for a sine wave output, and amplitude of about 2 V peak-topeaks. It must be at least 1 V p-p for the PLL to work. Connect scope leads as shown, Ch 1 at the input, and Ch 2 at the VCO output. Connect a frequency counter to the input, and measure the VCO control not worth it here. A simple capacitor loop filter appears to work in this case, but will not be optimum in critical applications. The 565 works better than the 4046 for sine wave inputs, because of the more appropriate phase detector. The LM565 and LM565C are general purpose phase locked loops containing a stable, highly linear voltage controlled oscillator for low distortion FM demodulation, and a double balanced phase detector with good carrier suppression. The VCO frequency is set with an external resistor and capacitor, and a tuning range of 10:1 can be obtained with the same capacitor. The characteristics of the closed loop system bandwidth, response speed, capture and pull in rangemay be adjusted over a wide range with an external resistor and capacitor. The loop may be broken between the VCO and the phase detector for insertion of a digital frequency divider to obtain frequency multiplication. The LM565H is specified for operation over the -55C to +125C military temperature range. The LM565CN is specified for operation over the 0C to +70C temperature range. Applications : Data and tape synchronization Modems FSK demodulation FM demodulation Frequency synthesizer Tone decoding Frequency multiplication and division SCA demodulators Telemetry receivers Signal regeneration Coherent demodulators 9. CONCLUSION FM demodulation in which PLL demodulator is working up to 200 KHz to 6MHz frequency. The output of the PLL demodulator is somewhat distorted so to get the proper output Low Pass Filter is required. In the output FM demodulated wave in the form of sine wave is obtain. 10. REFERENCES [1]Eletronics And Communication System: Roddy & Coolen [2]Electronics And Communication : George Keneddy [3]Op-Amp and Integrated circuits : R. Gayakwad [4]FM demodulation using adigital radio and digital signal processing : James Michael Shima [5] Communication Engineering :B.P.Lathi [6] www.icmaster.com [7] www.ic4u.com

voltage with the DMM at pin 7. Don't try to measure the VCO gain as we did for the 4046--pin 7 has a limited range of voltages for which the circuit will function, and we will make this measurement another way. Turn the power on, then the counter and the signal source. Vary the frequency until the PLL locks, which will happen around 25-30 kHz. Observe that the following range is greater than the capture range. To narrow the capture range, connect a resistance between pins 6 and 7. Leaving this open, as we have, makes the capture range as large as possible. Shorting it makes the range as small as possible. Measure the VCO control voltage at pin 7 while varying the frequency. It is found from 7.99 V at 35.5 kHz to 9.87 V at 20.2 kHz, which was about the maximum lock-in range in this case. As you vary the frequency, note the phase relation between the input and the VCO output, which changes as expected for a Type I phase detector. Although we can find KP and KVCO well enough, there are internal mysteries in the rest of the loop that make estimating the loop gain as a function of frequency more difficult than with the 4046. The data sheets give some help in this exercise, plotting the loop gain as a function of the resistance between pins 6 and 7. Further experimentation could reveal some details, but it is

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