DIGITALLY CONTROLLED OSCILLATOR

RFIC PROJECT

(Submitted By)

Anu Mariam John Shilpi Varshney

200941003 200941015

M.Tech. VLSI and Embedded Systems

IIIT Hyderabad
Introduction
Any communication system that transmits and receives data on a high frequency carrier
needs to be able to generate the carrier, usually using an oscillator. An oscillator is a circuit
that can produce a high-quality signal at a pre-determined frequency with little noise and low
harmonics. In real receivers, the oscillator is phase and frequency locked to the incoming
carrier using a carrier recovery circuit.

Fig 1: Communication System

In recent years, CMOS technology is scaling down resulting to a very low control voltage
that leads to the availability of only very steep slope, and this complicates the implementation
of conventional RF circuits in CMOS technology, often causes instability and the portability
issues. Furthermore, low voltage and thin metal interconnects which are achieved in a scaled
down CMOS process are advantageous to digital circuits but the same becomes
disadvantages to RF circuits due to reduced voltage headroom, low inductor’s quality factor,
and reduced gate oxide reliability. Therefore, RF circuits such as RF oscillators need to be
realized employing digitally controlled logics for future generation wireless technology.

Barkhausen’s Criteria
For steady oscillation, two conditions must be simultaneously met at w0.

 The open loop gain, |H(jw0)|, must be equal to unity.

 The total phase shift around the loop must be equal to zero.

Oscillator Characteristics
An oscillator generates a periodic output. The circuit must entail a self sustaining mechanism
that allows it’s own noise to grow and eventually become a periodic signal.

Most RF oscillator can be viewed as feedback circuits.

 Fig 2: Feedback Circuit

We design oscillators with criteria such as:

 frequency stability over bias and temperature variations

 spectral purity (low power in harmonics, and low phase noise)
 power consumption
 area consumption

Oscillators consist of two major blocks:

 An active, nonlinear element that provides gain

 A frequency selective circuit (e.g. LC tank, crystal oscillator, dielectric resonator)

In most RF oscillator, a frequency selective network, e.g. an LC tank, is included in the loop
so as to stabilize the frequency.

The frequency selective network is also known as resonator.

Fig 3: Frequency Selective Network

Need for Digitally Controlled Oscillator

In conventional wireless systems, two types of oscillators i.e. ring oscillator and LC-tank
oscillator are often used to generate a local frequency in a phase-locked loop (PLL) . The
former is often used in MHz frequency applications because of its compactness, as spiral
inductors are usually not necessary in a ring topology. In GHz frequency applications, the
later is usually preferred because of its improved noise performance and lower power
consumption. As a ring oscillator is more compact than LC-tank oscillator, we designed a
ring oscillator which can work for GHz frequency applications. For this, following techniques
can be employed:
  Use of transmission gates: Transmission gates can be used between inverter delay
stages and the resistance of the transmission gates can be varied with the control
voltage applied to the transmission gate. But this circuit has the drawback of
frequency saturation for higher voltages so that it provides low control voltage range.
 Use of digital control: Digital control with asymmetrical stages can be used. But it
reduces the output voltage swing that makes the circuit sensitive to the phase noise.
 Use of parallel resistor: Parallel resistors can be used in transmission gate and
resistance can be controlled by changing digital control. It provides high load
resistances means more power dissipation. And also resistance becomes saturated at
high control logic so that linearity worsens.

In 8 bit digitally controlled ring oscillator, we tried to overcome all the above problems.
In our design, we have provided symmetrical load, high linearity and very large output
voltage swing. The output frequency of the DCO is controlled by varying the driving current
according to the input control bits.

Conventional Ring Oscillator

A basic ring oscillator uses odd number of inverters.

Fig 4: 3 stage RING OSCILLATOR

Each inverter in the oscillator is used as a delay cell. The frequency of oscillation for
identical cell is given by following equation,

Where Td is the delay of each inverter cell and N is the number of identical cell. The period
or frequency of oscillation is varied either by changing the number of inverter stages in the
ring or varying the propagation delay of inverter. The delay of each inverter cell is further
expressed as,
Where CL is load capacitance, change in V is the output voltage swing and Id is the driving
current to the load. So the frequency of oscillation without changing number of stages can be
varied either by changing the load capacitance or driving current to the load. The propagation
delay of inverter is proportional to Width to Length (W/L) ratio of the transistor as increment
in width increases the capacitance and decreases the resistance that makes time constant
equal and frequency remains constant. The load capacitance (CL) at the output node of
inverter can be expressed by following equation.

Where, suffices g, s, b represent gate, source and body (substrate) of transistors M1, M2 and
M3, respectively. Similarly, Cw represents wire capacitance. The load capacitance can be
changed by using MIM capacitor or MOS transistor at the output node of inverter. But it
cannot be much useful in sub-micron technology as wired capacitance have significant
portion in load capacitance, which in turn, limits the maximum oscillating frequency [6] of an
oscillator. Thus, this approach would not be much useful to achieve wide turning range of an
oscillator. Controlling delay by changing the driving current (Id) would support for wide
tuning range and also provides high linearity which is utilized in the DCO.

Digitally Controlled Oscillator

The schematic of the proposed 3-stages digital controlled ring oscillator is:

Fig 5: Digitally Controlled Oscillator

The circuit has 8 control bits (D0-D7). All the stages are identical and make a ring for an
individual bit. For 8 bits, 8 rings with different W/L ratio are made in parallel by connecting
them at the output of each delay cell. Each ring is made with identical stages to provide equal
delay. One of the advantages of the proposed method is that it provides symmetrical load.
The output frequency of the oscillator depends on the control bits. This oscillator has used
tristate inverter for the delay cell.

 Tristate Inverter:

(a) (b)

Fig 6 : (a) Tristate Inverter (b) equivalent circuit when control bit is 1

In the tristate inverter, it has control input D that controls the signal propagation from input to
the output through transistors M1 and M3 or M2 and M4 depending on the input level Low
(0), High (1), respectively. When D=0, the output will no longer connected to the input and
none of the transistors M3, M4 conducts. The sizes of the transistors are selected to provide
equal delay through both the paths. The proposed tristate inverter cell can be approximated as
transmission gate followed by an inverter when D=1. Equivalent circuit of the proposed
inverter when D=1 is shown in Fig. 6(b).
Spice Code
.include "C:\Users\Shilpi\Desktop\tsmc018.md"

MN1 Out A Gnd 0 NMOS W=2.7u L=180n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.7u L=180n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
.ends

.subckt Tristate_inv D Db In Out Gnd Vdd

MN1 Out N_2 Gnd 0 NMOS W=2.7u L=180n AS=450f PS=2.8u AD=450f PD=2.8u
MN2 In D N_2 0 NMOS W=2.7u L=180n AS=450f PS=2.8u AD=450f PD=2.8u
MP2 N_1 Db In Vdd PMOS W=2.7u L=180n M=2 AS=2.25p PS=8.6u AD=1.5625p PD=5u
MP3 Out N_1 Vdd Vdd PMOS W=2.7u L=180n M=2 AS=2.25p PS=8.6u AD=1.5625p
PD=5u
.ends

XTristate_inv_10 D3 N_6 Vout trigger Gnd Vdd Tristate_inv

XTristate_inv_11 D3 N_6 trigger N_2 Gnd Vdd Tristate_inv
XTristate_inv_12 D3 N_6 N_2 Vout Gnd Vdd Tristate_inv
XTristate_inv_13 D4 N_5 Vout trigger Gnd Vdd Tristate_inv
XTristate_inv_14 D4 N_5 trigger N_2 Gnd Vdd Tristate_inv
XTristate_inv_15 D4 N_5 N_2 Vout Gnd Vdd Tristate_inv
XTristate_inv_16 D7 N_1 N_2 Vout Gnd Vdd Tristate_inv
XTristate_inv_17 D7 N_1 trigger N_2 Gnd Vdd Tristate_inv
XTristate_inv_18 D7 N_1 Vout trigger Gnd Vdd Tristate_inv
XTristate_inv_19 D6 N_3 N_2 Vout Gnd Vdd Tristate_inv
XINV_1 D0 N_7 Gnd Vdd INV
XINV_2 D1 N_8 Gnd Vdd INV
XINV_3 D2 N_9 Gnd Vdd INV
XINV_4 D3 N_6 Gnd Vdd INV
XINV_5 D4 N_5 Gnd Vdd INV
XINV_6 D7 N_1 Gnd Vdd INV
XINV_7 D6 N_3 Gnd Vdd INV
XTristate_inv_1 D0 N_7 Vout trigger Gnd Vdd Tristate_inv
XINV_8 D5 N_4 Gnd Vdd INV
XTristate_inv_2 D0 N_7 trigger N_2 Gnd Vdd Tristate_inv
XTristate_inv_3 D0 N_7 N_2 Vout Gnd Vdd Tristate_inv
XTristate_inv_4 D1 N_8 Vout trigger Gnd Vdd Tristate_inv
XTristate_inv_5 D1 N_8 trigger N_2 Gnd Vdd Tristate_inv
XTristate_inv_6 D1 N_8 N_2 Vout Gnd Vdd Tristate_inv
XTristate_inv_20 D6 N_3 trigger N_2 Gnd Vdd Tristate_inv
XTristate_inv_21 D6 N_3 Vout trigger Gnd Vdd Tristate_inv
XTristate_inv_7 D2 N_9 Vout trigger Gnd Vdd Tristate_inv
XTristate_inv_22 D5 N_4 Vout trigger Gnd Vdd Tristate_inv
XTristate_inv_8 D2 N_9 trigger N_2 Gnd Vdd Tristate_inv
XTristate_inv_9 D2 N_9 N_2 Vout Gnd Vdd Tristate_inv
XTristate_inv_23 D5 N_4 trigger N_2 Gnd Vdd Tristate_inv
XTristate_inv_24 D5 N_4 N_2 Vout Gnd Vdd Tristate_inv

Vdd Vdd Gnd DC 1.8v

VD0 D0 Gnd DC 1.8v
VD1 D1 Gnd DC 1.8v
VD2 D2 Gnd DC 1.8v
VD3 D3 Gnd DC 1.8v
VD4 D4 Gnd DC 1.8v
VD5 D5 Gnd DC 1.8v
VD6 D6 Gnd DC 1.8v
VD7 D7 Gnd DC 1.8v
.tran 0.1n 30n

.power vdd 4.2n

.PRINT I(VDD)
.PRINT PTOTAL=PAR('V(VDD)*I(VDD)')

.measure TRAN iavg AVG i(vvdd) FROM=20.35n TO=21.37n

.PARAM vvddpar=1.8
.measure TRAN power PARAM='iavg*vvddpar'
.print v(Vout) v(D0) v(D1) v(D2) v(D3) v(D4) v(D5) v(D6) v(D7)

.op
.probe
.end
Waveform
We calculated the frequency of the oscillator for different W/L ratios.

W/L .9u/.18u = 5 1.8u/.18u = 10 2.7u/.18u = 15 3.6u/.18u = 20

 W/L = .9u/.18u = 5
o When all the D bits are 1

 W/L = 1.8u/.18u = 10
o When all the D bits are 1
 W/L = 2.7u/.18u = 15
o When all the D bits are 1

 W/L = 3.6u/.18u = 20
o When all the D bits are 1
Simulation Result
 W/L = .9u/.18u = 5

Frequency and power calculation:

Num of 1’s in D Delay(ns Freq Power(mW) Avg

) current(mA)
8 1.42 704.2MHZ 1.925 1.0694
7 1.50 666.66MHz 1.7049 0.947
6 1.61 621.1Mhz 1.5098 0.838
5 1.75 571.42MHz 1.3357 0.7420
4 2.04 490.19MHz 1.1007 0.6114
3 2.41 414.93MHz 0.8902 0.4945
2 3.17 315.45MHz 0.6461 0.3589
1 4.87 205.33MHz 0.4150 0.2305

o Frequency range = 205.33MHz – 704.2 MHz

Phase Noise Calculation:

Element Source Phase noise (dbc/Hz)

XINV_2.MN1 Tot -4.9423e+000
XINV_3.MN1 Tot -4.9423e+000
XINV_4.MN1 Tot -4.9423e+000
XINV_7.MN1 Tot -4.9423e+000
XINV_6.MN1 Tot -4.9423e+000
XINV_1.MN1 Tot -4.9423e+000
XINV_8.MN1 Tot -4.9423e+000
XINV_5.MN1 Tot -4.9423e+000
XTRISTATE_INV_6.MN1 Tot -7.6510e+000
XTRISTATE_INV_3.MN1 Tot -7.6510e+000
XTRISTATE_INV_9.MN1 Tot -7.6510e+000
XTRISTATE_INV_24.MN Tot -7.6510e+000
1
XTRISTATE_INV_19.MN Tot -7.6510e+000
1
XTRISTATE_INV_12.MN Tot -7.6510e+000
1
XTRISTATE_INV_15.MN Tot -7.6510e+000
1
 XTRISTATE_INV_16.MN Tot -7.6510e+000
1
XTRISTATE_INV_9.MN2 Tot -8.0084e+000
XTRISTATE_INV_6.MN2 Tot -8.0084e+000
XTRISTATE_INV_3.MN2 Tot -8.0084e+000
XTRISTATE_INV_16.MN Tot -8.0084e+000
2

o Total Phase Noise ( dBc/Hz ) : | 1.0872e+001 |

 W/L = 1.8u/.18u = 10

Frequency and power calculation:

Num of 1’s in D Delay(ns) Freq Power(mW) Avg

current(mA)
8 1.09 917MHZ 3.4330 1.9072
7 1.15 869MHz 3.1250 1.7361
6 1.25 794Mhz 2.7592 1.5329
5 1.42 704MHz 2.3629 1.3127
4 1.52 654MHz 2.0093 1.1163
3 1.81 552MHz 1.6160 . 89776
2 2.24 446MHz 1.2090 . 67167
1 3.27 305MHz . 75757 .42087

o Frequency range = 305MHz – 917 MHz

Phase Noise Calculation:

Element Source Phase noise (dbc/Hz)

XINV_2.MN1 Tot -4.5633e+000
XINV_3.MN1 Tot -4.5633e+000
XINV_4.MN1 Tot -4.5633e+000
XINV_7.MN1 Tot -4.5633e+000
XINV_6.MN1 Tot -4.5633e+000
XINV_1.MN1 Tot -4.5633e+000
XINV_8.MN1 Tot -4.5633e+000
XINV_5.MN1 Tot -4.5633e+000
XTRISTATE_INV_3.MN2 Tot -7.1832e+000
XTRISTATE_INV_16.MN Tot -7.1832e+000
2
XTRISTATE_INV_24.MN Tot -7.1832e+000
2
XTRISTATE_INV_6.MN2 Tot -7.1832e+000
XTRISTATE_INV_9.MN2 Tot -7.1832e+000
XTRISTATE_INV_19.MN Tot -7.1832e+000
 2
XTRISTATE_INV_15.MN Tot -7.1832e+000
2
XTRISTATE_INV_12.MN Tot -7.1832e+000
2
XTRISTATE_INV_6.MN1 Tot -7.2737e+000
XTRISTATE_INV_12.MN Tot -7.2737e+000
1
XTRISTATE_INV_24.MN Tot -7.2737e+000
1
XTRISTATE_INV_3.MN1 Tot -7.2737e+000

o Total Phase Noise ( dBc/Hz ) : | 1.1500e+001 |

 W/L = 2.7u/.18u = 15

Frequency and power calculation:

Num of 1’s in Delay(ns) Freq Power(mW) Avg

D current(mA)
8 0.98 1.014GHz 4.937 2.743
7 1.04 961.5MHz 3.920 2.177
6 1.09 917.4MHz 3.443 1.913
5 1.26 793.6MHz 2.875 1.597
4 1.37 729.9MHz 2.393 1.329
3 1.59 628.9MHz 1.786 0.9922
2 1.97 507.6MHz 1.128 0.6267
1 2.90 344.8MHz 0.4150 0.2305

o Frequency range = 344.8MHz – 1.014GHz

Phase Noise Calculation:

Element Source Phase noise (dbc/Hz)

XINV_3.MN1 Tot -4.0113e+000
XINV_4.MN1 Tot -4.0113e+000
XINV_5.MN1 Tot -4.0113e+000
XINV_6.MN1 Tot -4.0113e+000
XINV_2.MN1 Tot -4.0113e+000
XINV_1.MN1 Tot -4.0113e+000
XINV_7.MN1 Tot -4.0113e+000
 XINV_8.MN1 Tot -4.0113e+000
XTRISTATE_INV_15.MN Tot -6.3667e+000
2
XTRISTATE_INV_9.MN2 Tot -6.3667e+000
XTRISTATE_INV_16.MN Tot -6.3667e+000
2
XTRISTATE_INV_6.MN2 Tot -6.3667e+000
XTRISTATE_INV_3.MN2 Tot -6.3667e+000
XTRISTATE_INV_12.MN Tot -6.3667e+000
2
XTRISTATE_INV_24.MN Tot -6.3667e+000
2
XTRISTATE_INV_19.MN Tot -6.3667e+000
2
XTRISTATE_INV_11.MN Tot -6.5477e+000
1
XTRISTATE_INV_17.MN Tot -6.5477e+000
1
XTRISTATE_INV_5.MN1 Tot -6.5477e+000
XTRISTATE_INV_23.MN Tot -6.5477e+000
1

o Total Phase Noise ( dBc/Hz ) : | 1.2228e+001 |

 W/L = 3.6u/.18u = 20

Frequency and power calculation:

Num of 1’s in Delay(ns) Freq Power(mW) Avg

D current(mA)
8 0.87 1.142GHz 6.5113 3.6174
7 0.93 1.075GHz 5.8770 3.2650
6 0.98 1.013GHz 5.1902 2.8835
5 1.09 917.43MHz 4.4798 2.4888
4 1.26 793MHz 3.8385 2.1325
3 1.53 653.59MHz 3.1069 1.7260
2 1.75 571MHz 2.3814 1.3230
1 2.57 389MHz 1.4898 .82765

o Frequency range = 389MHz – 1.142GHz

Phase Noise Calculation:

Element Source Phase noise (dbc/Hz)

 XINV_2.MN1 Tot -3.5160e+000
XINV_7.MN1 Tot -3.5160e+000
XINV_4.MN1 Tot -3.5160e+000
XINV_8.MN1 Tot -3.5160e+000
XINV_3.MN1 Tot -3.5160e+000
XINV_1.MN1 Tot -3.5160e+000
XINV_5.MN1 Tot -3.5160e+000
XINV_6.MN1 Tot -3.5160e+000
XTRISTATE_INV_12.MN Tot -5.6853e+000
2
XTRISTATE_INV_16.MN Tot -5.6853e+000
2
XTRISTATE_INV_9.MN2 Tot -5.6853e+000
XTRISTATE_INV_15.MN Tot -5.6853e+000
2
XTRISTATE_INV_19.MN Tot -5.6853e+000
2
XTRISTATE_INV_24.MN Tot -5.6853e+000
2
XTRISTATE_INV_6.MN2 Tot -5.6853e+000
XTRISTATE_INV_3.MN2 Tot -5.6853e+000
XTRISTATE_INV_23.MN Tot -5.7402e+000
1
XTRISTATE_INV_20.MN Tot -5.7402e+000
1
XTRISTATE_INV_8.MN1 Tot -5.7402e+000
XTRISTATE_INV_2.MN1 Tot -5.7402e+000

o Total Phase Noise ( dBc/Hz ) : | 1.2861e+001 |

Frequency Variation
 Frequency is in MHz.
1200

1000

800

W/L =5
600 W/L =10
W/L = 15
Series 4
400

200

0
D=1 D=2 D=3 D=4 D=5 D=6 D=7 D=8

Power Variation
 Power is in mW.

4 W/L=5
W/L=10
3 W/L=15
W/L=20

0
D=1 D=2 D=3 D=4 D=5 D=6 D=7 D=8

Phase Noise Variation

 Phase Noise is in dBc/Hz
 Phase Noise
13.5

13

12.5

12
Phase Noise
11.5

11

10.5

10

9.5
W/L = 5 W/L = 10 W/L = 15 W/L = 20

 As no of 1’s in D is increasing, frequency is increasing.

 As no of 1’s in D is increasing, power is increasing.
 As W/L is increasing, frequency is increasing.
 As W/L is increasing, power is increasing.
 As W/L is increasing, phase noise is also increasing.

Total frequency range for the DCO for different W/L is : 205.33 MHz – 1.142 GHz

Conclusion
A high-linearity 8-bit digitally-controlled oscillator (DCO) is designed on a ring topology
using TSMC 0.18 um CMOS process parameters. One of the advantages of the ring topology
over a LC-tank oscillator is that it does not contain any spiral inductor so that the chip size is
very small. DCO provides a wide tuning range from MHz frequency to GHz frequency.

References
 Thomas H. Lee “The design of CMOS Radio- Frequency Integrated Circuits”.