Total No.

of Questions : 8]

[Total No. of Pages :2

P1649

[3965] - 636 M.E. (E & TC) (VLSI & Embedded Systems)

Time :3 Hours] [Max. Marks :100 Instructions to the candidates: 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Figures to the right indicate full marks. 5) Use of logarithmic tables slide rule, Mollier charts, electronic pocket calculator and steam tables is allowed. 6) Assume suitable data, if necessary.

SECTION - I
Q1) a) b) Q2) a) b) Derive an expression for conversion gain of single ended MOSFET mixer. MOSFET is operated in CS mode. [8] With suitable example, explain back gate bias effect. [8] What are the causes of cross talk? List the sources. Give the cross connect mechanism [8] What is the power constrained noise optimization? Give the expression for device width and noise figure. [8] Design RF amplifier for following specifications A v = 50, Bandwidth = 200 MHz, Source resistance = 50 , load = 10 Pf, supply voltage = 2.5V. Assume suitable data. [8] With the help of incremental model of MOSFET based tuned amplifier, explain unilateralization & neutralization techniques in detail. [8] [18]

Q3) a) b)

Q4) Write short notes on (any Three) a) EDA tools in Analog IC design. b) MOSFET capacitor. c) Power budget & noise optimization. d) Effects of technology scaling on RF amplifiers.

P.T.O.

SECTION - II
Q5) a) b) Q6) a) b) How will you make EMI immune RF ASIC? Give the analytical justifications to the suggestions. [8] Explain ASIC design flow. At what stage will you care for cross talk.[8] Why is degeneration required in LNA? Explain inductive source degeneration with necessary expression. [8] Design LNA to operate at 650 MHz. Design suitable bias. Compute device width degenerating inductance, noise figure & Lg. Assume suitable data. [8] Explore the bandwidth enhancement with fT doublers. [8]

Q7) a) b)

With suitable schematics explain LF and RF models for MOSFET. What is SPICE model? What are the dynamic elements? [8] [18]

Q8) Write short notes on (Any Three): a) b) c) d) e) Spurs and solutions. Power match versus noise match. Requirements of LNA. Types of noise in RF. Series and shunt peaking amplifier.

EEE

[3965]-636

Total No. of Questions : 6]

[Total No. of Pages : 2

P1767

[3965]-137 M.E. (E/TC) (VLSI & Embedded System)

Time : 3 Hours] Instructions to the candidates: 1) All questions are compulsory. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Assume suitable data, if necessary.

[Max. Marks : 100

SECTION - I
Q1) a) b) Draw the design flow for an ASIC design process and explain each step. Write short notes on structural, behavioral and data flow modeling techniques used in VHDL. What do you mean by RTL modeling, explain. [18] What are different simulation modes in simulators. Explain in detail static timing analysis. [8] What is error masking problem in BIST. Derive the equation to define probability of error masking to calculate with length of test sequence = 3 and length of signature = 16. [8] Explain in detail clock tree insertion and methods to minimise clock skew in clock tree synthesis. [8] Explain memory BIST insertion design in detail. [8]

Q2) a) b)

Q3) a) b)

SECTION - II
Q4) a) b) List out goals and objectives for each physical design step of ASIC design? What are the factors contributes to best floorplanning? Explain in detail. [18]

P.T.O.

Q5) a)

Explain the following terms: i) ii) Back Annotation. Logic synthesis.

[8]

b)

Classify placement algorithm on constructive method.

[8] [16]

Q6) Write short note on (Any Three): a) b) c) d) Random Testing. Issues in verification. Stick diagram. Semiconductor intellectual property core.

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[3965]-137

Total No. of Questions :10]

[Total No. of Pages :2

P1459

[3965] - 632 M.E. (E & TC) (VLSI & Embedded System) MEMORY TECHNOLOGIES (2008 Course) (Elective - II) (504185)

Time : 3 Hours] [Max. Marks :100 Instructions to the candidates: 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagram must be drawn wherever necessary. 4) Figures to the right indicate full marks. 5) Assume suitable data, if necessary.

SECTION - I Q1) a) b) What are the parameters which should be taken into account while designing SRAMs? [8] Draw the various SRAM cell structures? Explain then for various operations. [8] What do mean by Dual-port SRAMs? What are its applications and features? Draw typical dual-port RAM cell. [8] Write short note on Nonvolatile SRAMs. [8]

Q2) a) b) Q3) a) b)

Draw the 1T cell structure of DRAM; explain its operation in short. Discuss its pro and cones. [8] What are the developments took place in the sense amplifier for improvement of DRAM performance? [8] What do mean by OTP EPROM? What are its advantages and disadvantages? [8] What is antifuse? How this is been utilized in semiconductor memories? [8]
P.T.O.

Q4) a) b)

Q5) What is the function of refreshing circuit? What are the parameters which should be taken into account while designing the refreshing circuit for semiconductor memories? Draw typical refreshing circuit. [18] SECTION - II Q6) a) b) Q7) a) b) List the faults that can occur in semiconductor chip. Out of these which affects semiconductor memory more. [8] What is MSCAN? Describe the steps involved in it? How the Embedded DRAM fault modeling and testing is done? [8] [8]

Describe Classical Test Algorithm GALPAT for semiconductor memory testing? [8] What are the advantages and disadvantages of the FRAM? [8]

Q8) a) b)

What are applications of Analog Memories? Draw the typical block diagram of Analog memory. [8] Compare MRAM, SRAM, DRAM, EEPROM and FRAM. [10]

Q9) a) b)

Enlist the memory cards available in the market. What are the different packaging materials used for memories? [8] Why radiation hardening is required for semiconductor memories? Explain one best known producer for radiation hardening. [8] Justify Semiconductor Rate failure analysis is very important from reliability point of view. [8]

Q10)a) b)

TTT

[3965]-632

Total No. of Questions : 8]

[Total No. of Pages : 3

P1711

[3965]-635 M.E. (E & TC) (VLSI & Embedded System) EMBEDDED SIGNAL PROCESSING
(Sem. - II) (2008 Course) (504189)

Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates: 1) Answer any 3 questions from each section. 2) Answer 3 questions from Section - I and 3 questions from Section - II 3) Answers to the two sections should be written in separate books. 4) Neat diagrams must be drawn wherever necessary. 5) Figures to the right indicate full marks. 6) Assume suitable data, if necessary.

SECTION - I
Q1) a) What is correlation? Find out cross - correlation of following. Finite length sequences. [6] x (n) = { 1, 2, 3, 9, 6}

y (n) = { 1, 2, 3, 4} b) Compare linear & circular convolution. How linear convolution is calculated using circular convolution. Find linear convolution using circular convolution for following sequences. [6] x1 (n) {1, 1, 1}, x2 (n) = {1 1 1}

c) Q2) a)

What is Discrete Cosine Transform (DCT)? Discuss in detail the different properties of DCT. [6] Design a Butterworth filter using the impulse invariance method for the following specifications. [8]
0.8 H (e j ) 1 H (e j ) 0.2 0 0.2 0.6

P.T.O.

b) c)

Draw the signal flow graph complete in all respect for 8 point DIT FFT. [4] Find IDFT of a given sequence. i) ii) X (K) = [ 10, 2.0 + 2.0 i, 2.0, 2.0 2.0i] X (K) = {0, 0, 2, 0} [4]

Q3) a)

With reference to DSP processor explain the following: i) ii) iii) Pipelining. Hardware multiplier - acumulator. Special Instructions. [8]

b)

What are requirement of DSP processor? Describe important blocks & parallelism in built in DSP processor. [8] [16]

Q4) Write short notes on (any three): a) DTMF generation & detection. b) Data - flow graph. c) Havelet Transform. d) IEEE floating point representation format.

SECTION - II
Q5) a) Compute the iteration bound of the given DFG using LPM algorithm.

[8] [3965]-635 2

b) Q6) a)

Define unfolding? State & explain properties of unfolding. Consider the DFG shown below.

[8]

i) ii) b)

What is the maximum sample rate of this DFG. Manually retime this DFG to minimize the clock period.

[8] What are the architecture issues of 32 bit TMS 320C67X floating point DSP processor? With the suitable example explain programming consideration for C67X processor. [8] Draw & explain the architecture of black fin processor. Explain different addressing modes of TMS 320 C54XX. [8] [8]

Q7) a) b)

Q8) Write short notes on (any three): a) Inverse Modeling. b) Adaptive filters. c) Folding transformation. d) Window functions & their characteristics.

[18]

]]]

[3965]-635

Total No. of Questions : 8]

[Total No. of Pages : 2

P1750

[3965]-625 M.E. (E & T/C VLSI & Embedded Systems) ANALOG & DIGITAL CMOS IC DESIGN
(2008 Course) (504181) (Sem. - I)

Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates: 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary.

SECTION - I
Q1) Design current mirror for 100 A . Assume suitable data. What are the techniques to improve output resistance? Give mathematical analysis to support. [16] Q2) a) b) What are the performance parameters of voltage reference circuit? Explore in brief. What is state of art? [8] Design differential amplifier for voltage gain of 40 dB and bandwidth of 1MHz. [8] List and explain in brief, device & wire parasitics normally considered while design. [8] What is need of low voltage opamp? What are its design techniques? [8] [18]

Q3) a) b)

Q4) Write short notes on any three: a) b) c) d) High gain opamp. Macro model of opamp. BGR. Cascode amplifier.

P.T.O.

SECTION - II
Q5) Draw FSM diagram, write VHDL code & test bench for 10111 mealy sequence detector. [16] Q6) a) b) Design CMOS logic for F = AB + CDE + E (F + G). Compute area on chip. [8] What are the constraints in FSM design? How to tackle them? Explain any one in detail. [8] Derive an expression for power delay product. How does PDP help designer? [8] What is parameter? Explain technology scaling in detail. [8] [18]

Q7) a) b)

Q8) Write short notes on any three: a) Merits, demerits & applications of transmission gate. b) Trends in ultra fast technology. c) CMOS layout rules. d) NORA logic.

]]]

[3965]-625

SECTION - II
Q5) a) b) c) Q6) a) b) Describe need and operation of stack checking feature of COS - II . [6] Write and describe RTOS Initialization Code for three different tasks [6] using COS - II . Describe various task states defined in COS - II . What are the techniques used to protect shared data? [6] [8]

What is the need of task synchronization? What are the techniques used to synchronize different tasks? [8]

Q7) a)

Describe role and operation of following COS - II services. i) ii) iii) iv) v) OSMboxCreate(), OSMboxPend(), OSMboxPost(), OSMboxAccept() and OSMboxQuery().

[10]

b)

What is meant by porting the RTOS? What are the basic requirements [6] for porting COS - II ? How IDE is useful for design and development of system software? Explain. [8] Describe file manipulation techniques used in Linux/RT-Linux. [8]

Q8) a) b)

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[3965]-634 2

Total No. of Questions : 8]

[Total No. of Pages : 2

P1768

[3965]-138 M.E. (E & T/C) (VLSI & Embedded Systems) RFIC DESIGN
(2002 Course) (Elective - I)

Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates: 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary.

SECTION - I
Q1) a) b) Q2) a) b) Q3) a) b) Draw a.c. equivalent ckt. of MOSFET. Modify it for RF signal. What are different parasitics? List RF sensitive parasitics. [8] Explore OCT & SCT methods to compute bandwidth of an amplifier. List their limitations. [8] How do zeros act as bandwidth enhancer? Explore with suitable example. [8] What are bandwidth enhancement techniques? Explain any one in detail. [8] Design CMOS amplifier for voltage gain of 60dB and bandwidth of 100 MHz. Assume suitable data. [8] What is need of neutralization & unilaterization in RF amplifiers? Explain any one in detail. [8] [18]

Q4) Write short notes on any three: a) AM-PM conversion. b) c) d) Cascaded amplifiers. S parameters. SPICE model.

P.T.O.

SECTION - II
Q5) a) b) What different noise types are important in RF amplifiers? Explain any one noise type in detail. [8] Design LNA for voltage gain of 60 dB. Assume suitable data. What type of matching technique will you use? [8]

Q6) a) b)

What are the types of mixer? Explain any one with the help of mathematical analysis in detail. [8] What is meant by power match & noise match? Explore with the help of suitable schematics. [8]

Q7) a) b)

With the help of mathematical analysis, explain power constrained noise optimization in detail. [8] Design CMOS mixer for IF = 455 kHz at signal frequency of 900 kHz. Assume suitable data. [8]

Q8) Write short notes on any three: a) b) c) d) Linearity in mixer. Spurs. Diode ring mixer. Crosstalk mitigation techniques.

[18]

]]]

[3965]-138