TLH5583

A
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January 1995
ADC0831ADC0832ADC0834 and ADC0838
8-Bit Serial IO AD Converters with Multiplexer Options
General Description
The ADC0831 series are 8-bit successive approximation
AD converters with a serial IO and configurable input mul-
tiplexers with up to 8 channels The serial IO is configured
to comply with the NSC MICROWIRE
TM
serial data ex-
change standard for easy interface to the COPS
TM
family of
processors and can interface with standard shift registers
or mPs
The 2- 4- or 8-channel multiplexers are software configured
for single-ended or differential inputs as well as channel as-
signment
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero in-
put voltage value In addition the voltage reference input
can be adjusted to allow encoding any smaller analog volt-
age span to the full 8 bits of resolution
Features
Y
NSC MICROWIRE compatibledirect interface to
COPS family processors
Y
Easy interface to all microprocessors or operates
stand-alone
Y
Operates ratiometrically or with 5 V
DC
voltage
reference
Y
No zero or full-scale adjust required
Y
2- 4- or 8-channel multiplexer options with address
logic
Y
Shunt regulator allows operation with high voltage
supplies
Y
0V to 5V input range with single 5V power supply
Y
Remote operation with serial digital data link
Y
TTLMOS inputoutput compatible
Y
03" standard width 8- 14- or 20-pin DIP package
Y
20 Pin Molded Chip Carrier Package (ADC0838 only)
Y
Surface-Mount Package
Key Specifications
Y
Resolution 8 Bits
Y
Total Unadjusted Error g LSB and g1 LSB
Y
Single Supply 5 V
DC
Y
Low Power 15 mW
Y
Conversion Time 32 ms
Typical Application
TLH55831
TRI-STATE is a registered trademark of National Semiconductor Corporation
COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation RRD-B30M115Printed in U S A
Absolute Maximum Ratings (Notes 1 2)
If MilitaryAerospace specified devices are required
please contact the National Semiconductor Sales
OfficeDistributors for availability and specifications
Current into V
a
(Note 3) 15 mA
Supply Voltage V
CC
(Note 3) 65V
Voltage
Logic Inputs b03V to V
CC
a 03V
Analog Inputs b03V to V
CC
a 03V
Input Current per Pin (Note 4) g5 mA
Package g20 mA
Storage Temperature b65`C to a150`C
Package Dissipation
at T
A
e25`C (Board Mount) 08W
Lead Temperature (Soldering 10 sec)
Dual-In-Line Package (Plastic) 260`C
Dual-In-Line Package (Ceramic) 300`C
Molded Chip Carrier Package
Vapor Phase (60 sec) 215`C
Infrared (15 sec) 220`C
ESD Susceptibility (Note 5) 2000V
Operating Ratings (Notes 1 2)
Supply Voltage V
CC
45 V
DC
to 63 V
DC
Temperature Range T
MIN
s
T
A
s
T
MAX
ADC08318BCJ
ADC083148CCJ
ADC0832BIWM
ADC0831248CIWM b40`C to a85`C
ADC0831248BCN
ADC0838BCV
ADC0831248CCN
ADC0838CCV
ADC0831248CCWM 0`C to a70`C
Converter and Multiplexer Electrical Characteristics
The following specifications apply for V
CC
e Va e V
REF
e 5V V
REF
s
V
CC
a01V T
A
e T
j
e 25`C and f
CLK
e 250 kHz
unless otherwise specified Boldface limits apply from T
MIN
to T
MAX

BCJ BIWM BCV CCV CCWM BCN

CIWM and CCJ Devices and CCN Devices
Parameter Conditions
Typ
Tested Design
Typ
Tested Design
Units
(Note 12)
Limit Limit
(Note 12)
Limit Limit
(Note 13) (Note 14) (Note 13) (Note 14)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error V
REF
e500 V
ADC0838BCV (Note 6) g g
ADC0831248BCN g g LSB
ADC08318BCJ g
ADC0832BIWM g
ADC0838CCV g1 g1
ADC0831248CCN g1 g1
ADC0831248CCWM g1 g1
ADC083148CCJ g1
ADC0831248CIWM g1
Minimum Reference 35 13 35 13 13 kX
Input Resistance (Note 7)
Maximum Reference 35 59 35 54 59 kX
Input Resistance (Note 7)
Maximum Common-Mode Input V
CC
a005 V
CC
a005 V
CC
a005 V
Range (Note 8)
Minimum Common-Mode Input GND b005 GND b005 GNDb005 V
Range (Note 8)
DC Common-Mode Error g g g g g LSB
2
Converter and Multiplexer Electrical Characteristics (Continued)
The following specifications apply for V
CC
e Va e 5V T
A
e T
j
e 25`C and f
CLK
e 250 kHz unless otherwise specified
Boldface limits apply from T
MIN
to T
MAX

BCJ BIWM BCV CCV CCWM BCN

CIWM and CCJ Devices and CCN Devices
Parameter Conditions
Typ
Tested Design
Typ
Tested Design
Units
(Note 12)
Limit Limit
(Note 12)
Limit Limit
(Note 13) (Note 14) (Note 13) (Note 14)
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
Change in zero 15 mA into Va
error from V
CC
e5V V
CC
eNC
to internal zener V
REF
e5V
operation (Note 3) 1 1 1 LSB
V
Z
internal MIN 15 mA into Va 63 63 63
diode breakdown MAX 85 85 85 V
(at Va) (Note 3)
Power Supply Sensitivity V
CC
e5Vg5% g g g g g g LSB
I
OFF
Off Channel Leakage On Channele5V b02 b02 b1 mA
Current (Note 9) Off Channele0V b1
On Channele0V a02 a02 a1 mA
Off Channele5V a1
I
ON
On Channel Leakage On Channele0V b02 b02 b1 mA
Current (Note 9) Off Channele5V b1
On Channele5V a02 a02 a1 mA
Off Channele0V a1
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
Logical 1 Input V
CC
e525V 20 20 20 V
Voltage (Min)
V
IN(0)
Logical 0 Input V
CC
e475V 08 08 08 V
Voltage (Max)
I
IN(1)
Logical 1 Input V
IN
e50V 0005 1 0005 1 1 mA
Current (Max)
I
IN(0)
Logical 0 Input V
IN
e0V b0005 b1 b0005 b1 b1 mA
Current (Max)
V
OUT(1)
Logical 1 Output V
CC
e475V
Voltage (Min) I
OUT
eb360 mA 24 24 24 V
I
OUT
eb10 mA 45 45 45 V
V
OUT(0)
Logical 0 Output V
CC
e475V 04 04 04 V
Voltage (Max) I
OUT
e16 mA
I
OUT
TRI-STATE Output V
OUT
e0V b01 b3 b01 b3 b3 mA
Current (Max) V
OUT
e5V 01 3 01 a3 a3 mA
I
SOURCE
Output Source V
OUT
e0V b14 b65 b14 b75 b65 mA
Current (Min)
I
SINK
Output Sink Current (Min) V
OUT
eV
CC
16 80 16 90 80 mA
I
CC
Supply Current (Max)
ADC0831 ADC0834 09 25 09 25 25 mA
ADC0838
ADC0832 Includes Ladder 23 65 23 65 65 mA
Current
3
AC Characteristics
The following specifications apply for V
CC
e 5V t
r
e t
f
e 20 ns and 25`C unless otherwise specified
Typ
Tested Design
Limit
Parameter Conditions
(Note 12)
Limit Limit
Units
(Note 13) (Note 14)
f
CLK
Clock Frequency
Min 10 kHz
Max 400 kHz
t
C
Conversion Time Not including MUX Addressing Time 8 1f
CLK
Clock Duty Cycle Min 40 %
(Note 10) Max 60 %
t
SET-UP
CS Falling Edge or 250 ns
Data Input Valid to CLK
Rising Edge
t
HOLD
Data Input Valid 90 ns
after CLK Rising Edge
t
pd1
t
pd0
CLK Falling C
L
e100 pF
Edge to Output Data Valid Data MSB First 650 1500 ns
(Note 11) Data LSB First 250 600 ns
t
1H
t
0H
Rising Edge of C
L
e10 pF R
L
e10k 125 250 ns
CS to Data Output and (see TRI-STATE Test Circuits)
SARS Hi Z
C
L
e100 pf R
L
e2k 500 ns
C
IN
Capacitance of Logic 5 pF
Input
C
OUT
Capacitance of Logic 5 pF
Outputs
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2 All voltages are measured with respect to the ground plugs
Note 3 Internal zener diodes (63 to 85V) are connected from Va to GND and V
CC
to GND The zener at Va can operate as a shunt regulator and is connected
to V
CC
via a conventional diode Since the zener voltage equals the ADs breakdown voltage the diode insures that V
CC
will be below breakdown when the device
is powered from Va Functionality is therefore guaranteed for Va operation even though the resultant voltage at V
CC
may exceed the specified Absolute Max of
65V It is recommended that a resistor be used to limit the max current into Va (See Figure 3 in Functional Description Section 60)
Note 4 When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k V
b
or V
IN
l V
a
) the absolute value of current at that pin should be limited
to 5 mA or less The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four
Note 5 Human body model 100 pF discharged through a 15 kX resistor
Note 6 Total unadjusted error includes offset full-scale linearity and multiplexer errors
Note 7 Cannot be tested for ADC0832
Note 8 For V
IN
(b)tV
IN
(a) the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater then the V
CC
supply Be careful during testing at low V
CC
levels (45V)
as high level analog inputs (5V) can cause this input diode to conductespecially at elevated temperatures and cause errors for analog inputs near full-scale The
spec allows 50 mV forward bias of either diode This means that as long as the analog V
IN
or V
REF
does not exceed the supply voltage by more than 50 mV the
output code will be correct To achieve an absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4950 V
DC
over
temperature variations initial tolerance and loading
Note 9 Leakage current is measured with the clock not switching
Note 10 A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of
these limits the minimum time the clock is high or the minimum time the clock is low must be at least 1 ms The maximum time the clock can be high is 60 ms The
clock can be stopped when low so long as the analog input voltage remains stable
Note 11 Since data MSB first is the output of the comparator used in the successive approximation loop an additional delay is built in (see Block Diagram) to
allow for comparator response time
Note 12 Typicals are at 25`C and represent most likely parametric norm
Note 13 Tested limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level)
Note 14 Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels
4
Typical Performance Characteristics
vs V
REF
Voltage
Unadjusted Offset Error
Voltage
Linearity Error vs V
REF
Temperature
Linearity Error vs
TLH55832
Linearity Error vs f
CLK
ADC0831 ADC0834)
Temperature (ADC0838
Power Supply Current vs
Temperature
Output Current vs
Note For ADC0832 add I
REF
TLH558340
Power Supply Current
vs f
CLK
TLH558329
Leakage Current Test Circuit
TLH55833
5
TRI-STATE Test Circuits and Waveforms
t
1H
t
0H
TLH55834
t
1H
t
0H
TLH558323
Timing Diagrams
Data Input Timing
TLH558324
Data Output Timing
TLH558325
ADC0831 Start Conversion Timing
TLH558326
6
Timing Diagrams (Continued)
ADC0831 Timing
TLH558327
*LSB first output not available on ADC0831
ADC0832 Timing
TLH558328
ADC0834 Timing
TLH55835
7
Timing Diagrams (Continued)
A
D
C
0
8
3
8
T
i
m
i
n
g
T
L

5
5
8
3

6
*
M
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k
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8
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B
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8
ADC0838 Functional Block Diagram
T
L

5
5
8
3

7
*Some of these functionspins are not available with other options
Note 1 For the ADC0834 D1 is input directly to the D input of SELECT 1 SELECT 0 is forced to a 1 For the ADC0832 DI is input directly to the DI input of
ODDSIGN SELECT 0 is forced to a 0 and SELECT 1 is forced to a 1
9
Connection Diagrams
ADC0838 8-Channel MUX
Small OutlineDual-In-Line Package (J M and N)
TLH55838
Top View
ADC0834 4-Channel MUX
Small OutlineDual-In-Line Package (J M and N)
TLH558330
Top View
COM internally connected to A GND
ADC0832 2-Channel MUX
Dual-In-Line Package (J and N)
TLH558331
Top View
COM internally connected to GND
V
REF
internally connected to V
CC

ADC0832 2-Channel MUX

Small Outline Package (M)
TLH558341
Top View
ADC0831 Single
Differential Input
Dual-In-Line Package (J and N)
TLH558332
Top View
ADC0831 Single Differential Input
Small Outline Package (M)
TLH558342
Top View
ADC0838 8-Channel MUX
Molded Chip Carrier (PCC) Package (V)
TLH558333
10
Functional Description
10 MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample-data com-
parator structure which provides for a differential analog in-
put to be converted by a successive approximation routine
The actual voltage converted is always the difference be-
tween an assigned a input terminal and a b input ter-
minal The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive If the assigned a input is less than the
b input the converter responds with an all zeros output
code
A unique input multiplexing scheme has been utilized to pro-
vide multiple analog channels with software-configurable
single-ended differential or a new pseudo-differential op-
tion which will convert the difference between the voltage at
any analog input and a common terminal The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexi-
bility One converter package can now handle ground refer-
enced inputs and true differential inputs as well as signals
with some arbitrary reference voltage
A particular input configuration is assigned during the MUX
addressing sequence prior to the start of a conversion The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differen-
tial In the differential case it also assigns the polarity of the
channels Differential inputs are restricted to adjacent chan-
nel pairs For example channel 0 and channel 1 may be
selected as a different pair but channel 0 or 1 cannot act
differentially with any other channel In addition to selecting
differential mode the sign may also be selected Channel 0
may be selected as the positive input and channel 1 as the
negative input or vice versa This programmability is best
illustrated by the MUX addressing codes shown in the fol-
lowing tables for the various product options
The MUX address is shifted into the converter via the DI
line Because the ADC0831 contains only one differential
input channel with a fixed polarity assignment it does not
require addressing
The common input line on the ADC0838 can be used as a
pseudo-differential input In this mode the voltage on this
pin is treated as the b input for any of the other input
channels This voltage does not have to be analog ground
it can be any reference potential which is common to all of
the inputs This feature is most useful in single-supply appli-
cation where the analog circuitry may be biased up to a
potential other than ground and the output signals are all
referred to this potential
TABLE I MultiplexerPackage Options
Part Number of Analog Channels Number of
Number
Single-Ended Differential
Package Pins
ADC0831 1 1 8
ADC0832 2 1 8
ADC0834 4 2 14
ADC0838 8 4 20
11
Functional Description (Continued)
TABLE II MUX Addressing ADC0838
Single-Ended MUX Mode
MUX Address Analog Single-Ended Channel
SGL ODD SELECT
0 1 2 3 4 5 6 7 COM
DIF SIGN 1 0
1 0 0 0 a b
1 0 0 1 a b
1 0 1 0 a b
1 0 1 1 a b
1 1 0 0 a b
1 1 0 1 a b
1 1 1 0 a b
1 1 1 1 a b
Differential MUX Mode
MUX Address Analog Differential Channel-Pair
SGL ODD SELECT 0 1 2 3
DIF SIGN
1 0 0 1 2 3 4 5 6 7
0 0 0 0 a b
0 0 0 1 a b
0 0 1 0 a b
0 0 1 1 a b
0 1 0 0 b a
0 1 0 1 b a
0 1 1 0 b a
0 1 1 1 b a
TABLE III MUX Addressing ADC0834
Single-Ended MUX Mode
MUX Address Channel
SGL ODD SELECT
DIF SIGN
1
0 1 2 3
1 0 0 a
1 0 1 a
1 1 0 a
1 1 1 a
COM is internally tied to A GND
Differential MUX Mode
MUX Address Channel
SGL ODD SELECT
DIF SIGN
1
0 1 2 3
0 0 0 a b
0 0 1 a b
0 1 0 b a
0 1 1 b a
TABLE IV MUX Addressing
ADC0832
Single-Ended MUX Mode
MUX Address Channel
SGL ODD
0 1
DIF SIGN
1 0 a
1 1 a
COM is internally tied to A GND
Differential MUX Mode
MUX Address Channel
SGL ODD
0 1
DIF SIGN
0 0 a b
0 1 b a
12
Functional Description (Continued)
Since the input configuration is under software control it
can be modified as required at each conversion A channel
can be treated as a single-ended ground referenced input
for one conversion then it can be reconfigured as part of a
differential channel for another conversion Figure 1 illus-
trates the input flexibility which can be achieved
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above V
CC
(typically 5V)
without degrading conversion accuracy
20 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor Using a serial
communication format offers two very significant system im-
provements it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor transmit-
ting highly noise immune digital data back to the host proc-
essor
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence For clarity a
separate diagram is shown of each device
1 A conversion is initiated by first pulling the CS (chip se-
lect) line low This line must be held low for the entire con-
version The converter is now waiting for a start bit and its
MUX assignment word
2 A clock is then generated by the processor (if not provid-
ed continuously) and output to the AD clock input
3 On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register The
start bit is the first logic 1 that appears on this line (all
leading zeros are ignored) Following the start bit the con-
verter expects the next 2 to 4 bits to be the MUX assign-
ment word
8 Single-Ended
4 Differential
8 Pseudo-Differential
Mixed Mode
TLH55839
FIGURE 1 Analog Input Multiplexer Options for the ADC0838
13
Functional Description (Continued)
4 When the start bit has been shifted into the start location
of the MUX register the input channel has been assigned
and a conversion is about to begin An interval of clock
period (where nothing happens) is automatically inserted to
allow the selected MUX channel to settle The SAR status
line goes high at this time to signal that a conversion is now
in progress and the DI line is disabled (it no longer accepts
data)
5 The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time
6 When the conversion begins the output of the SAR com-
parator which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder appears at the DO line on each
falling edge of the clock This data is the result of the con-
version being shifted out (with the MSB coming first) and
can be read by the processor immediately
7 After 8 clock periods the conversion is completed The
SAR status line returns low to indicate this clock cycle
later
8 If the programmer prefers the data can be provided in an
LSB first format |this makes use of the shift enable (SE)
control line] All 8 bits of the result are stored in an output
shift register On devices which do not include the SE con-
trol line the data LSB first is automatically shifted out the
DO line after the MSB first data stream The DO line then
goes low and stays low until CS is returned high On the
ADC0838 the SE line is brought out and if held high the
value of the LSB remains valid on the DO line When SE is
forced low the data is then clocked out LSB first The
ADC0831 is an exception in that its data is only output in
MSB first format
9 All internal registers are cleared when the CS line is high
If another conversion is desired CS must make a high to
low transition followed by address information
The DI and DO lines can be tied together and controlled
through a bidirectional processor IO bit with one wire This
is possible because the DI input is only looked-at during
the MUX addressing interval while the DO line is still in a
high impedance state
30 REFERENCE CONSIDERATIONS
The voltage applied to the reference input to these convert-
ers defines the voltage span of the analog input (the differ-
ence between V
IN(MAX)
and V
IN(MIN)
) over which the 256
possible output codes apply The devices can be used in
either ratiometric applications or in systems requiring abso-
lute accuracy The reference pin must be connected to a
voltage source capable of driving the reference input resist-
ance of typically 35 kX This pin is the top of a resistor
divider string used for the successive approximation conver-
sion
In a ratiometric system the analog input voltage is propor-
tional to the voltage used for the AD reference This volt-
age is typically the system power supply so the V
REF
pin
can be tied to V
CC
(done internally on the ADC0832) This
technique relaxes the stability requirements of the system
reference as the analog input and AD reference move to-
gether maintaining the same output code for a given input
condition
For absolute accuracy where the analog input varies be-
tween very specific voltage limits the reference pin can be
biased with a time and temperature stable voltage source
The LM385 and LM336 reference diodes are good low cur-
rent devices to use with these converters
The maximum value of the reference is limited to the V
CC
supply voltage The minimum value however can be quite
small (see Typical Performance Characteristics) to allow di-
rect conversions of transducer outputs providing less than a
5V output span Particular care must be taken with regard to
noise pickup circuit layout and system error voltage sourc-
es when operating with a reduced span due to the in-
creased sensitivity of the converter (1 LSB equals V
REF

256)
TLH558310
a) Ratiometric b) Absolute with a Reduced Span
FIGURE 2 Reference Examples
14
Functional Description (Continued)
40 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces-
sor with a highly noise immune serial bit stream This in itself
greatly minimizes circuitry to maintain analog signal accura-
cy which otherwise is most susceptible to noise pickup
However a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage
The differential input of these converters actually reduces
the effects of common-mode input noise a signal common
to both selected a and b inputs for a conversion (60
Hz is most typical) The time interval between sampling the
a input and then the b input is of a clock period
The change in the common-mode voltage during this short
time interval can cause conversion errors For a sinusoidal
common-mode signal this error is
V
error
(max)e V
PEAK
(2qf
CM
)

05
f
CLK J
where f
CM
is the frequency of the common-mode signal
V
PEAK
is its peak voltage value
and f
CLK
is the AD clock frequency
For a 60 Hz common-mode signal to generate a LSB
error (5 mV) with the converter running at 250 kHz its
peak value would have to be 663V which would be larger
than allowed as it exceeds the maximum analog input limits
Due to the sampling nature of the analog inputs short spikes
of current enter the a input and exit the b input at the
clock edges during the actual conversion These currents
decay rapidly and do not cause errors as the internal com-
parator is strobed at the end of a clock period Bypass ca-
pacitors at the inputs will average these currents and cause
an effective DC current to flow through the output resist-
ance of the analog signal source Bypass capacitors should
not be used if the source resistance is greater than 1 kX
This source resistance limitation is important with regard to
the DC leakage currents of input multiplexer as well The
worst-case leakage current of g1 mA over temperature will
create a 1 mV input error with a 1 kX source resistance An
op amp RC active low pass filter can provide both imped-
ance buffering and noise filtering should a high impedance
signal source be required
50 OPTIONAL ADJUSTMENTS
51 Zero Error
The zero of the AD does not require adjustment If the
minimum analog input voltage value V
IN(MIN)
is not ground
a zero offset can be done The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any V
IN
(b) input at this V
IN(MIN)
value This
utilizes the differential mode operation of the AD
The zero error of the AD converter relates to the location
of the first riser of the transfer function and can be mea-
sured by grounding the V
IN
(b) input and applying a small
magnitude positive voltage to the V
IN
(a) input Zero error is
the difference between the actual DC input voltage which is
necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal LSB value
( LSBe98 mV for V
REF
e5000 V
DC
)
52 Full-Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1 LSB down from the desired
analog full-scale voltage range and then adjusting the mag-
nitude of the V
REF
input (or V
CC
for the ADC0832) for a
digital output code which is just changing from 1111 1110 to
1111 1111
53 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AD is shifted away from
ground (for example to accommodate an analog input sig-
nal which does not go to ground) this new zero reference
should be properly adjusted first A V
IN
(a) voltage which
equals this desired zero reference plus LSB (where the
LSB is calculated for the desired analog span using
1 LSBe analog span256) is applied to selected a input
and the zero reference voltage at the corresponding b
input should then be adjusted to just obtain the 00
HEX
to
01
HEX
code transition
The full-scale adjustment should be made |with the proper
V
IN
(b) voltage applied] by forcing a voltage to the V
IN
(a)
input which is given by
V
IN
(a) fs adj e V
MAX
b15

(V
MAX
bV
MIN
)
256 (
where
V
MAX
e the high end of the analog input range
and
V
MIN
e the low end (the offset zero) of the analog
range
(Both are ground referenced)
The V
REF
(or V
CC
) voltage is then adjusted to provide a
code change from FE
HEX
to FF
HEX
This completes the ad-
justment procedure
60 POWER SUPPLY
A unique feature of the ADC0838 and ADC0834 is the inclu-
sion of a zener diode connected from the V
a
terminal to
ground which also connects to the V
CC
terminal (which is
the actual converter supply) through a silicon diode as
shown in Figure 3 (See Note 3)
TLH558311
FIGURE 3 An On-Chip Shunt Regulator Diode
15
Functional Description (Continued)
This zener is intended for use as a shunt voltage regulator
to eliminate the need for any additional regulating compo-
nents This is most desirable if the converter is to be re-
motely located from the system power source Figures 4
and 5 illustrate two useful applications of this on-board ze-
ner when an external transistor can be afforded
An important use of the interconnecting diode between V
a
and V
CC
is shown in Figures 6 and 7 Here this diode is
used as a rectifier to allow the V
CC
supply for the converter
to be derived from the clock The low current requirements
of the AD and the relatively high clock frequencies used
(typically in the range of 10k400 kHz) allows using the
small value filter capacitor shown to keep the ripple on the
V
CC
line to well under of an LSB The shunt zener regula-
tor can also be used in this mode This requires a clock
voltage swing which is in excess of V
Z
A current limit for the
zener is needed either built into the clock generator or a
resistor can be used from the CLK pin to the V
a
pin
Applications
TLH558312
FIGURE 4 Operating with a Temperature
Compensated Reference
TLH558334
FIGURE 5 Using the AD as
the System Supply Regulator
TLH558335
FIGURE 6 Generating V
CC
from the Converter Clock
TLH558336
FIGURE 7 Remote Sensing
Clock and Power on 1 Wire
*Note 45V s V
CC
s 63V
16
Applications (Continued)
Digital Link and Sample Controlling Software for the
Serially Oriented COP420 and the Bit Programmable IO INS8048
TLH558313
COP CODING EXAMPLE
Mnemonic Instruction
LEI ENABLES SIOs INPUT AND OUTPUT
SC C e 1
OGI G0e0 (CSe0)
CLR A CLEARS ACCUMULATOR
AISC 1 LOADS ACCUMULATOR WITH 1
XAS EXCHANGES SIO WITH ACCUMULATOR
AND STARTS SK CLOCK
LDD LOADS MUX ADDRESS FROM RAM
INTO ACCUMULATOR
NOP
XAS LOADS MUX ADDRESS FROM
ACCUMULATOR TO SIO REGISTER
u
8 INSTRUCTIONS
v
XAS READS HIGH ORDER NIBBLE (4 BITS)
INTO ACCUMULATOR
XIS PUTS HIGH ORDER NIBBLE INTO RAM
CLR A CLEARS ACCUMULATOR
RC C e 0
XAS READS LOW ORDER NIBBLE INTO
ACCUMULATOR AND STOPS SK
XIS PUTS LOW ORDER NIBBLE INTO RAM
OGI G0e1 (CSe1)
LEI DISABLES SIOs INPUT AND OUTPUT
8048 CODING EXAMPLE
Mnemonic Instruction
START ANL P1 0F7H SELECT AD (CSe0)
MOV B 5 BIT COUNTERw5
MOV A ADDR AwMUX ADDRESS
LOOP 1 RRC A CYwADDRESS BIT
JC ONE TEST BIT
BITe0
ZERO ANL P1 0FEH DIw0
JMP CONT CONTINUE
BITe1
ONE ORL P1 1 DIw1
CONT CALL PULSE PULSE SK 0x1x0
DJNZ B LOOP 1 CONTINUE UNTIL DONE
CALL PULSE EXTRA CLOCK FOR SYNC
MOV B 8 BIT COUNTERw8
LOOP 2 CALL PULSE PULSE SK 0x1x0
IN A P1 CYwDO
RRC A
RRC A
MOV A C AwRESULT
RLC A A(0)wBIT AND SHIFT
MOV C A CwRESULT
DJNZ B LOOP 2 CONTINUE UNTIL DONE
RETR
PULSE SUBROUTINE
PULSE ORL P1 04 SKw1
NOP DELAY
ANL P1 0FBH SKw0
RET
17
Applications (Continued)
A Stand-Alone Hook-Up for ADC0838 Evaluation
*Pinouts shown for ADC0838
For all other products tie to
pin functions as shown
Low-Cost Remote Temperature Sensor
TLH558314
18
Applications (Continued)
Digitizing a Current Flow
TLH558315
Operating with Ratiometric Transducers
TLH558337
*V
IN
(b) e 015 V
CC
15% of V
CC
s V
XDR
s 85% of V
CC
19
Applications (Continued)
Span Adjust OV
s
V
IN
s
3V
Zero-Shift and Span Adjust 2V
s
V
IN
s
5V
TLH558316
20
Applications (Continued)
Obtaining Higher Resolution
TLH558317
Controller performs a routine to determine which input polarity (9-bit example) or which channel pair (10-bit example) provides a non-zero output code
This information provides the extra bits
a) 9-Bit AD b)10-Bit AD
Protecting the Input
Diodes are 1N914
TLH558318
21
Applications (Continued)
High Accuracy Comparators
TLH558338
DO e all 1s if aV
IN
l bV
IN
DO e all 0s if aV
IN
k bV
IN
Digital Load Cell
TLH558319
Uses one more wire than load cell itself
Two mini-DIPs could be mounted inside load cell for digital output transducer
Electronic offset and gain trims relax mechanical specs for gauge factor and offset
Low level cell output is converted immediately for high noise immunity
22
Applications (Continued)
4 mA20 mA Current Loop Converter
All power supplied by loop
1500V isolation at output TLH558320
Isolated Data Converter
No power required remotely
1500V isolation
TLH558339
23
Applications (Continued)
TLH558321
T
w
o
W
i
r
e
I
n
t
e
r
f
a
c
e
f
o
r
8
C
h
a
n
n
e
l
s
24
Applications (Continued)
Two Wire 1-Channel Interface
TLH558322
Ordering Information
Part Number
Analog Input Total
Package
Temperature
Channels Unadjusted Error Range
ADC0831BCJ
1
g
Hermetic (J) b40`C to a85`C
ADC0831BCN Molded (N) 0`C to a70`C
ADC0831CCJ
g1
Hermetic (J) b40`C to a85`C
ADC0831CCN Molded (N) 0`C to a70`C
ADC0831CIWM SO(M) b40`C to a85`C
ADC0831CCWM SO(M) 0`C to a70`C
ADC0832BIWM
2
g
SO(M) b40`C to a85`C
ADC0832BCN Molded (N) 0`C to a70`C
ADC0832CIWM
g1
SO(M) b40`C to a85`C
ADC0832CCN Molded (N) 0`C to a70`C
ADC0832CCWM SO(M) 0`C to a70`C
25
Ordering Information (Continued)
Part Number
Analog Input Total
Package
Temperature
Channels Unadjusted Error Range
ADC0834BCN
4
g Molded (N) 0`C to a70`C
ADC0834CCJ
g1
Hermetic (J) b40`C to a85`C
ADC0834CCN Molded (N) 0`C to a70`C
ADC0834CCWM SO(M) 0`C to a70`C
ADC0834CIWM SO(M) b40`C to a85`C
ADC0838BCJ
8
g
Hermetic (J) b40`C to a85`C
ADC0838BCV PCC (V) 0`C to a70`C
ADC0838BCN Molded (N) 0`C to a70`C
ADC0838CCJ
g1
Hermetic (J) b40`C to a85`C
ADC0838CCV PCC (V) 0`C to a70`C
ADC0838CCN Molded (N) 0`C to a70`C
ADC0838CIWM SO(M) b40`C to a85`C
ADC0838CCWM SO(M) 0`C to a70`C
See NS Package Number J08A J14A J20A M14B M20B N08E N14A N20A or V20A
26
27
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
NS Package Number J08A
Ceramic Dual-In-Line Package (J)
NS Package Number J14A
28
Physical Dimensions inches (millimeters) (Continued)
Ceramic Dual-In-Line Package (J)
NS Package Number J20A
Hermetic Dual-In-Line Package (M)
NS Package Number M14B
29
Physical Dimensions inches (millimeters) (Continued)
Hermetic Dual-In-Line Package (M)
NS Package Number M20B
Molded Dual-In-Line Package (N)
NS Package Number N08E
30
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
NS Package Number N14A
Molded-Dual-In-Line Package (N)
NS Package Number N20A
31
A
D
C
0
8
3
1

A
D
C
0
8
3
2

A
D
C
0
8
3
4
a
n
d
A
D
C
0
8
3
8
8
-
B
i
t
S
e
r
i
a
l
I

O
A

D
C
o
n
v
e
r
t
e
r
s
w
i
t
h
M
u
l
t
i
p
l
e
x
e
r
O
p
t
i
o
n
s
Physical Dimensions inches (millimeters) (Continued)
Molded Chip Carrier Package (V)
Order Number ADC0838BCV or ADC0838CCV
NS Package Number V20A
LIFE SUPPORT POLICY
NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or 2 A critical component is any component of a life
systems which (a) are intended for surgical implant support device or system whose failure to perform can
into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system or to affect its safety or
with instructions for use provided in the labeling can effectiveness
be reasonably expected to result in a significant injury
to the user
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Corporation Europe Hong Kong Ltd Japan Ltd
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