Allegro Footprint Library Development Specifications

Cadence Design Systems, Inc.

This document contains information that is proprietary to Cadence Design Systems, Inc.This information is not to be disclosed, duplicated or released to any third party without prior written permission from an authorized representative of Cadence Design Systems, Inc.Any recipient of this document agrees to make every reasonable effort to prevent the unauthorized use of the information contained in this document.

Allegro Footprint Library Development Specification

Rev. 1.2 1/6/2009

Revision Block

Rev.
Draft 1.0 Draft 1.1 Draft 1.2

Date
11-12-2006 09-17-08 10-16-08

Description
Cadence Draft. Draft Update Draft Update

Changed by
F. Winsor D. Pierce D. Pierce / C. Saathoff /F Winsor

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Allegro Footprint Library Development Specification

Rev. 1.2 1/6/2009

TABLE OF CONTENTS
1 Introduction...............................................................................................................................4 1.1 1.2 2 2.1 Assumptions.......................................................................................................................4 Reference Documents ........................................................................................................4 Pad Stack Editor.................................................................................................................5 Through-hole Component Padstacks, Plated..............................................................5 Surface Mount Padstacks............................................................................................5

Physical Package Pad Stacks ....................................................................................................5 2.1.1 2.1.2

Package Symbols (Footprints) ..................................................................................................6 3.1 Allegro ...............................................................................................................................6 Package Symbols ........................................................................................................6 Mechanical Symbols...................................................................................................6 Flash Pad Symbols (Negative Planes Only) ...............................................................6 3.1.1 3.1.2 3.1.3

Nomenclature ............................................................................................................................6 4.1 4.2 Polarization ........................................................................................................................6 General Footprint Requirements........................................................................................7 Component Body Outline Requirements....................................................................7 Component Boundary Area ........................................................................................7 DFA Boundary Area...................................................................................................8 Reference Designator..................................................................................................8

4.2.1 4.2.2 4.2.3 4.2.4

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Allegro Footprint Library Development Specification

Rev. 1.2 1/6/2009

1 Introduction
This document provides specifications and guidelines for the development and content of Allegro footprint libraries. For specific procedures used and the user interface details please review the user guides and tutorials found with your installed tools. This document provides ECAD librarians with a set of basic requirements and guidelines to develop Allegro footprint libraries. Allegro footprint libraries generated, in accordance with this specification, will support design verification and printed circuit board layout.

1.1

Assumptions

This guideline document assumes that the audience is familiar with the Cadence Library development process, and the Cadence tools. This documentation is based upon the SPB16.01 releases of Cadence software. All guidelines have been developed to encourage use of the standard Cadence applications in the PCB flow. Property ownership and hierarchy is understood. Properties can be added to the Cadence libraries in different places, and duplicate properties will be overridden in a preset order. All interfaces to other CAD applications have been identified and are understood.

1.2

Reference Documents
Allegro Online documentation; Pad Stack Editor online documentation.

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Allegro Footprint Library Development Specification

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2 Physical Package Pad Stacks

This section defines the criteria for Allegro pad stacks.

2.1

Pad Stack Editor

The Pad Stack Editor is used to define and create pad stacks to be used by Allegro to create footprints.
Begin Layer Pad stack type Default Internal Layer
Thermal Regular Anti

End Layer

Solder Mask
Bottom Anti Top

Paste Mask
Bottom Top

Film Mask
Bottom Top

Thermal

Through Hole Through Via SMT Top SMT Bottom

x x x

x x

x x

x x

x x

X X

x x

x x

Thermal

Regular

Regular

Anti

x x

x x

x x x

2.1.1

Through-hole Component Padstacks, Plated

FHS = Pin size + .3 mm (.012) PAD Size - See Table below:

FHS PAD Size

Up to 1.016 mm (0.040) 1.016 mm (0.040) < FHS <= 1.905 mm (0.075) Greater than 1.905 mm (0.075)

FHS + 0.508 mm (0.020) FHS + 0.762 mm (0.030) FHS + 1.27 mm (0.050)

Antipad size = Pad size + 0.381 mm (0.15) Thermal reliefs size should equal antipad size Flash symbols, if required, (negative planes only), should use the power void size as the outer diameter and the pad size as the inner diameter. Spokes should be on 45s (diagonal) and the width will be sized as follows:
Finished hole size < 0.7mm (0.028"), width to be 0.203mm (0.008").
0.7mm (0.028") < hole size < 2.0mm (0.080"), width to be 0.254mm (0.010").

Finished hole size > 2.0mm (0.080"), width to be 0.381mm (0.015)".

2.1.2

Surface Mount Padstacks

Soldermask and pastemask are typically created one-to-one to the pad size Confidential Page 5 of 8

Allegro Footprint Library Development Specification

Rev. 1.2 1/6/2009

3 Package Symbols (Footprints)

3.1
3.1.1

Allegro
Package Symbols

Allegro PCB tool is used to create the footprints for layout.

Package Symbols are footprints that typically contain electrical characteristics. They are created in Allegro as package symbols. These are the .dra and .psm files. These footprints are associated with the DE HDL (Concept) library symbols.

3.1.2

Mechanical Symbols

Mechanical symbols contain no electrical characteristics. They are created in Allegro as mechanical symbols. Mechanical symbols (.dra and .bsm) would include such things as logos, copyrights, board level fiducials, etc.

3.1.3

Flash Pad Symbols (Negative Planes Only)

Flash pad symbols contain no electrical characteristics. They are created in Allegro as .dra and .fsm files and used in plated through hole padstacks to create thermal reliefs for flooded planes.

4 Nomenclature
The following features should be included where possible to denote component polarization, designation, and values. The text height on silkscreen legends should be 0.889mm (0.035"). Text heights smaller than 0.889mm (0.035") typically are not legible on the PCB. The aperture size used to draw the text should be 0.152mm (0.006") to provide an adequate opening on the screen for legend ink deposition. Numbering on components should not include leading zeros (A1 not A01).

4.1

Polarization

Class/Subclass: package_geometry/silkscreen_top, /assembly_top. Polarized parts should always have their polarity indicator aligned with pin 1 and marked with a + on the positive end of the part. Diode symbols should always have their cathodes aligned with pin 1. Silkscreen polarity should be placed such that it is visible after component placement. See Figure 4 for details.

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Allegro Footprint Library Development Specification

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Figure 4Polarization

4.2

General Footprint Requirements

The following component elements or geometries should be used to define the component. In some cases, there may be exceptions, but there are few. All data for these requirements are added under the PACKAGE GEOMETRY class.

4.2.1 Component Body Outline Requirements

Component outlines should exist on subclass, ASSEMBLY_TOP. SILKSCREEN_TOP outlines are not always required. Class/Subclass: package_geometry/assembly_top. Assembly graphics should define the maximum outline of the part, showing any component important orientation marking. Class/Subclass: package_geometry/silkscreen_top. If needed, silkscreen should identify the location and orientation of the part but should be minimized as much as possible. Silkscreen should be a minimum 0.127mm (0.005") line width and kept a minimum of 0.254mm (0.010") from pads so as not to interfere with the manufacturing process. Silkscreen should be visible after component placement. Exceptions are generally, SOICs, TSOPs and SSOPs. Only the top and bottom edges of the silkscreen would be visible for these parts, because the outline is drawn 0.254mm (0.010") inside the lead pads.

4.2.2 Component Boundary Area

Class/subclass: package_geometry/place_bound_top: (shapes only). Each component should have a placement boundary defined in the Allegro symbol. The size of the placement boundary should encompass the furthest extents of the pin pads and body outline. The maximum height should always be specified. In the case of multiple boundaries in a symbol, each boundary should have a maximum height attached. Additional height information, relative to allowing another symbol of to be added underneath the current one, may be attached to the boundary shape.

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4.2.3 DFA Boundary Area

Class/subclass: package_geometry/dfa_bound_top: (shapes only). Each component should have a DFA boundary defined in the Allegro symbol. The size of the DFA boundary should encompass the furthest extents of the pin pads and body outline. The DFA_DEV_CLASS property can be assigned to the footprint to enable the dynamic placement rules.

4.2.4 Reference Designator

Class/Subclass: ref des/assembly_top, silkscreen_top,: The assembly reference designator text (placeholder) is usually placed inside the boundary of the part. The silkscreen reference designator text (placeholder) is not always required. Text height should be 0.889mm (0.035") for two pin parts and 1.016mm (0.040") for other types.

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