Rheinisch-Westflische Technische Hochschule Aachen Institut fr Stromrichtertechnik und Elektrische Antriebe Universittsprofessor Dr. ir. Rik W.

De Doncker

RWTH Aachen University Institute for Power Electronics and Electrical Drives Professor Dr. ir. Rik W. De Doncker

Student Laboratory: Power Electronic Components

October 14, 2010

Contents
1 Introduction 2 Thyristor 2.1 PNPN structure . . . . . . . . . . . . . . 2.2 Latching with open gate contact . . . . . 2.3 Two-transistor equivalent circuit diagram 2.4 Summary . . . . . . . . . . . . . . . . . 2.4.1 Latching . . . . . . . . . . . . . . 2.5 Device structure in student laboratory . 3 Basics and procedures for the 3.1 Diusion processes . . . . 3.2 Photolithography . . . . . 3.3 Plasma etching . . . . . . 3.4 Oxide formation . . . . . . 3.5 Metallization . . . . . . . 3.6 Annealing . . . . . . . . . 3.7 Four-terminal sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 3 5 7 7 7 9 9 11 12 13 14 14 15 18 21

manufacturing of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

semiconductor devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Overview of the manufacturing process 5 FEM simulation

6 Clean Room 23 6.1 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 Wafer Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 Safety instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Experiment 1: Introduction into the properties and fabrication of GCTs 27

8 Experiment 2: Introduction into the device simulation tools 28 8.1 Introduction into the device simulation tools . . . . . . . . . . . . . . . . . . 28 8.1.1 Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Experiment 3: Device and Process simulation 36 9.1 Inspect, Tecplot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2 Process simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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Contents

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10 Experiment 4: Clean room and safety introductions, start of thyristor fabrication; substrate preparation and doping 40 11 Experiment 5: Four-point, diusion depth, oxide layer growth and metallization 43 12 Experiment 6: Lithography, etching and measurement of the etch prole 13 Experiment 7: Visit Inneon, last experimental steps 14 Experiment 8: Device measurement 15 Experiment 9: Presentation List of Figures List of Tables Bibliography 45 46 47 48 49 51 52

1 Introduction
This student laboratory will give an insight into the eort and challenges that exist in the fabrication of semiconductor devices. Several productions steps like FEM simulations, high-temperature diusion, photolithography, annealing and metallization are addressed. The goal is to fabricate a gate-commutated thyristor (GCT) and to show the technical and time-consuming eort for the production of a rather trivial appearing device. The student laboratory includes an excursion to the production site of a semiconductor company. The thyristor has been a long time the dominant device in power electronics and can also be fabricated without ne structures or high-precision photolithography. Especially for low frequencies in soft-switching components like for rectier operating at 50 Hz thyristors are suited. A further application eld for thyristors is the power class with very high voltages and currents, which is not reached by other devices yet (1.1).

Figure 1.1: Applications elds of power devices [ISEA]

2 Thyristor
2.1 PNPN structure

Figure 2.1: PNPN structure of a thyristor [ISEA]

2 Thyristor

The PNPN structure of a thyristor is shown in gure 2.1. J indicates the junction of two dierent doped regions. At the junction is n = p (equilibrium condition). A positive voltage between anode and cathode in o state (no voltage is applied at the gate) is called forward blocking voltage and a negative voltage as reverse blocking voltage. In the non-conductive state, the thyristor can hold both voltages up to reaching the respective breakdown voltage. Figure 2.2 a) and b) show the respective space charge regions with the corresponding I V -characteristics. The space charge region expands in reverse and blocking mode mainly into the low n-doped region. In conduction mode the I -V -characteristic of a thyristor is like that of a diode (gure 2.2 c). First it needs to be gured out how the device can be brought into the conducting state. The structure of the junctions appears as that this will not be possible. Because at least there is always one P-N junction, which is in reverse mode. Thermally generated charge carriers can act in the thyristor structure (with open gate) as a base current in a NPN transistor. By this many free charge carriers are created and the device is latched (conducting mode). This procedure corresponds in principle to the intended latching through the gate contact. But with linear amplication factors the thyristor can not described in all the elds.

Figure 2.2: Space charge regions with the corresponding I-V-characteristics for a) reverse, b) blocking, c) conducting [ISEA]

2.2 Latching with open gate contact

First, the switching on of the thyristor with open gate contact will be considered. After applying a voltage in forward direction a (low) current IA ows through the thyristor, which

2 Thyristor is equal at each P-N junction, see gure 2.2. IA = IJ 1 = IJ 2 = IJ 3

In the highly P-doped region (anode side) the total current IA ows nearly as pure defect electron ow. The asymmetrical P-N junction J1 is biased in forward direction. Therefore defect electrons in the form of a diusion current ow into the next N-region. There the hole diusion current is weakened by recombination with electrons from the strongly N-doped area (cathode side). Only one part P IA = IJ 2p of the hole current reaches reversed biased P-N junction J2 , that means that only one part of the current IJ 2 = IJ 2p + IJ 2n is carried by defect electrons. The electron current I2n is the portion of the total current. In the highly N-doped region of the cathode there is only electron current, which diuse toward the anode and recombine partly. Only the current portion N IA = IJ 2n reaches the transition J2 . The current balance on the central junction is IA = p IA + N IA This equation is not only formally correct. The space charge region in the thyristor with forward blocking voltage expands spatially. Junction J2 is biased in reverse mode. Charge carriers, which have been generated in the space charge region can not be neglected and lead to the quiescent current portion IR2 . This is added to IA , since the past consideration is valid only up to the borders of the space chare region. IA = P IA + N IA + IR2 The total current is therefore IA = IR2 1 (P + N )

2 Thyristor

As long as N + p < 1, which is the case for sucient recombination, the current IA remains nite. For N + p 1 the current results in IA . For N + P = 0,999 the current results in IA = 1000 IR2 . For N + P > 1 the current IA < I2p + I2n + IR2 and the current at junction J2 would be larger than the current through the outer electrodes. This condition can occur only transiently. A displacement current |Iv | = A
r 0

dE dt

occurs and the space charge and the eld strength at junction J2 gets reduced. The blocking P-N junction disappears and thus the thyristor is conducting.

Figure 2.3: Switching of the thyristor at suciently high reverse current in the forward mode [ISEA]

2.3 Two-transistor equivalent circuit diagram

The four layer structure can be replaced by two transistors (gure 2.4, right image) that have a PNP and an NPN-layer sequence. The two outer areas are heavily doped, as shown in gure 2.1, therefore the junctions J1 and J3 show good emitter properties in forward bias of the respective carriers into the central base areas. In the left image of gure 2.4 the turn-on sequence of the thyristor is shown. As soon the switch in the control circuit is closed, a control current ows through the P-N junction J3 . This junction is now more biased in forward direction and more electrons move from the N-emitter into the P-basis. They partly recombine with the holes of the base, which are supplied by the base contact. One part of the electrons reaches the space charge region of the N-collector, which is the base of the (upper) PNP transistor. By analogy the same process occurs in the (upper) PNP transistor. Holes from the emitter of the PNP-transistor (anode of the thyristor) ow into the base. One part of the holes reaches the space charge region of the P-collector, which is the base of the NPN transistor. The positive feedback of

2 Thyristor

Figure 2.4: The four layer structure of the thyristor replaced by two transistors. Right image shows the equivalent circuit diagram of a thyristor as a pair of tightly coupled bipolar junction transistors.[ISEA] these eects leads to a reduction of the space charge region at J2 and an increase of charge carriers in both base areas. Finally the current reaches a stationary level which is limited by the resistance in the circuit. The feedback eect between the emitter junctions J1 and J3 or rather the switching on of the thyristor with a suciently large reverse current at the P-N junction J2 can be initiated also without a control current. There is surplus of charge carriers in the space charge region of J2 The charge carriers are separated by the eld in the space charge region and move into the middle areas. It is: I1 = IA P + IR1 IR1 , IR2 is the reverse current of the single transistors it follows

I2 = (IA + IG )N + IR2 I1 + I2 = IA (N + P ) + IG N + IR1 + IR2 IA = IA (N + P ) + IG N + IR with IR1 + iR2 = IR transformed it follows IA = IG N + IR 1 (N + P )

As explained before, the gain factors N and P are inuencing the latching properties. Both factors can be adjusted by the doping and the dimensions of the layers during the fabrication of the device. If the sum of these factors is above one, then the device is permanently turned on.

2 Thyristor

2.4 Summary
2.4.1 Latching
The most common latching of a thyristor is the injection of a gate current IG . For the safe use a minimum current IG min and a minimum voltage VG min have to be supplied by a control device, assuming a positive anode-cathode voltage. In turned o state the NPN transistor blocks due to a negative or neutral base voltage. To turn on, a positive gate current has to be applied. The NPN gets a positive base current, thus the collector-emitter is of low resistance and the transistor is switched to "LOW". The voltage on the collector-emitter path decreases. Due to the circuit the VBE PNP voltage is larger and the PNP transistor switches to "LOW". The supplied current Ic NPN now supplies the base current for the NPN transistor. Once the latching process is initiated, the base of NPN-transistor theoretically can be left in high resistance, since the turn on eect is self-reinforced by the negative feedback. Usually small positive gate currents are used in order to ensure constant engaging at low loads.

2.5 Device structure in student laboratory

A bipolar device must have two characteristics, high blocking voltage and current gain, which are not compatible at rst glance. By the choice of the dimensions a N P N P structure can be created which solves this conict. The four-layer semiconductor structure of thyristors can be described by the layer sequence shown gure 2.5 including the contacts. The base contact of the NPN transistor is the gate contact of the whole structure and its emitter is the cathode. The collector of the NPN transistor is in the N-doped substrate, which is at the same time the base contact of the PNP transistor. The collector and emitter of the PNP transistor are the gate and the anode of the whole structure respectively.

2 Thyristor

Figure 2.5: Structure of four-layer sequence of a thyristor including the contacts The used Si wafers have a thickness of 525 m (semi standard) and are phosphorus doped (N-type) with a donor concentration of 11014 cm3 . Depending on the intended device properties and by taking into account the occurring strain by doping, the depths of layers can be varied. In this case the thicknesses are: N-doped cathode layer: 3-4 m P-doped gate layer: 40 m P-doped anode layer: 40 m

3 Basics and procedures for the manufacturing of semiconductor devices

3.1 Diusion processes
For a better understanding of the distribution of impurities in semiconductors a brief physical description of the diusion process is given here. In principle there are three dierent methods of doping semiconductors: diusion, ion implantation and epitaxy. For thyristor manufacturing diusion is preferred because of its simple handling. The term "diusion" describes the process of balancing the dierences in concentration. In order to diuse dopants into a silicon (Si) crystal, a high concentration of impurities is generated outside of the Si. The diusion takes place automatically because of the concentration dierence. At room temperature this balancing process is very slow and can be speed up at higher temperatures. The diusion is thus a process that should be carried out at the beginning of the device fabrication to prevent later the destruction of any temperature-sensitive structure on the wafer like the metallic contacts. The diusion process creates an over the space of some monolayer spread P-N junction. Gaussian prole can be created with the help of the diusion in which the maximum doping concentration is at the surface. The process of the diusion is described by Ficks rst and second law. It is sucient to consider Ficks rst law one-dimensional, since it is assumed that the diusion from the wafer surface into the wafer occurs one-dimensional: dN dx 2 J is the diusion ux in mol/m s, N the concentration in cm3 and D is the diusion coecient in m2 /s, which is in solids depending on the direction, except in cubic and diamond lattice structures. J = D The law describes the proportionality of the current density J to the concentration gradient dN . The Ficks second law of diusion describes the relationship between the temporal and dx spatial changes in the concentration N and follows from the continuity equation dN dJ = dt dx as well as from Ficks rst law to:

3 Basics and procedures for the manufacturing of semiconductor devices

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d2 N dN =D 2 dt dx For dierent boundary value problems and initial value problems dierent solutions of Ficks second law can be found. In general two cases are distinguished: the diusion from an innite and from a nite (dopant) source. Doping is achieved by diusion of atoms from the surface into the layer. If the doping level on the surface does not change, then the source for doping is innite. The solution of Ficks second law is a complementary error function:

N (x,t) = N0 erfc With: N0 x D(T ) t

x 2 D(T ) t

(3.1)

surface concentration doping depth dconstant, depending on the temperature and the dopant diusion time

For the diusion from the gas phase and with a suciently thick doping layer on the substrate surface an innite source is assumed. A semiconductor surface that is exposed to ion implantation where a thin layer with a limited number of ions or atoms is created on the surface corresponds to diusion from a nite source. The solution of Ficks second law leads after approximation to a Gaussian prole:

N (x,t) = With: Q = N0 d d x D(T ) t

Q D(T ) t

e 4D(T )t

x2

(3.2)

initial thickness of source layer on surface doping depth diusion constant, depending on the temperature and the dopant diusion time

The surface concentration decreases with the diusion length and the total concentration of impurities remains constant over the substrate thickness. In gure 3.1, the impurity concentration N is shown normalized to the surface concentration according to the Gaussian prole.

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Figure 3.1: Diusion behavior for innite (left) and nite (right) dopant source [Zim]

3.2 Photolithography
The photolithography is a transferring process, in which the structures of a mask (like in left image of gure 3.2) are mapped onto a photoresist. For the processing of semiconductor devices dened areas on the surface have to be protected by photoresist from processes like etching or deposition of a material. A light-sensitive photoresist is deposited onto a wafer. This is done by dropping some droplets of photoresist onto the wafer surface. The wafer is placed in a so-called spin-coater, where by fast rotation the photoresist is spread homogenously. In a photolithography system it is exposed to light through a mask and then developed. There are positive and negative resists. The chemical bonds of the positive resist are cracked during the exposure and therefore the solubility in a developer is increased. In contrast, the molecular chains crosslink in a negative resist by exposing to light. Here it is dicult to remove the exposed areas by the developer. In the right image of gure 3.3 the dierence between positive and negative photoresist is shown after development. The (photo)mask is usually made of a chromium layer which is deposited on a quartz substrate. For the relatively rough structure of a thyristor, however, it is sucient to use a foil-printed mask xed on glass. The structures of the foil mask have to be in a very homogeneous black. For this a laser printer with a resolution of 25,000 dpi is necessary. For comparison standard oce printer have a maximum resolution of 1,200 dpi, as shown in gure 3.2 (left). There are three dierent exposure methods: contact, proximity and projection. The simplest exposure system is contact lithography. Here the mask is in direct contact with the photoresist and therefore the highest resolution is possible. In the proximity method there is small gap between mask and substrate of 10 m to 50 m. The advantage is that the mask keeps clean but the disadvantage is a lower resolution. In the projection lithography there is also a gap between wafer and mask, but here the pattern of the mask is projected by lenses onto the surface. The advantage here is that the pattern of a small mask like for

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Figure 3.2: Photomask for thyristor process (right) and dierence of positive and negative resist (right) [Zim]

a certain device can be projected many times onto a wafer.

3.3 Plasma etching

Plasma is an ionized gas consisting of neutral as well as from excited atoms or molecules, ions and electrons. It can be generated in a high frequency eld (usually 13.56 MHz) and exhibits a characteristic color depending on the used gas. Plasma etching is a chemical, physical or combined etching process. In the chemical dry etching with plasma, gaseous reaction products are generated which lead to a high selectivity with isotropic etching proles. In the physical process a bombardment of the substrate surface with inert ion takes place which beats out physically material. Due to the dened direction of the bombardment of almost perpendicular to the surface the etching proles is anisotropic. The etching method in this student laboratory is the chemical dry etching process. The used process gases are sulfur hexauoride (SF6 ) and oxygen (O2 ), which get cracked in plasma to free uoride radicals F* and SFx ions. In the chemical etching process uorine radicals attack the surface and form gaseous Si tetrauoride SiF4. Characteristic for this process is the formation of a SiOx Fy mixed oxide, which covers the inner side wall and the bottom of the etched valley. This passivative oxide creates a protection against the uoride radicals. Due to the vertical ion bombardment the protective oxide layer on the bottom is removed whereas the cover remains at the side walls. By this condition the uoride radicals etch only the bottom and the side walls keep protected the by the oxide layer. This creates a highly anisotropic etching prole (gure 3.3).

3 Basics and procedures for the manufacturing of semiconductor devices In the plasma the following reaction take place:

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SF6 SF6 SF6 + e SF6 + e SF6 + 2e O2 SF6 + O

SF 5+F SF 4 + 2F SF5 + F SF 5 +F SF4 + 2F 2O SOF4 + F

Table 3.1: Chemical reaction during the etching process

Figure 3.3: Etching process by SF6 and O2 [Zim]

3.4 Oxide formation

Silicon dioxide (SiO2 ) is the native oxide of Si and it is process compatible with the Si technology. It has a very high specic resistance of around 1014 to 1016 cm at room temperature. There are two procedures to form SiH4 on Si: deposition and thermal oxidation. During the deposition gases like silane (SiH4 ) and O2 are led onto the substrate at temperatures of around 300 C to 800 C. The gases get cracked and the oxide is formed on the surface. The benets of the deposition in comparison to oxidation are the constant deposition rate and the low process temperatures. For the thermal oxidation temperatures over 1000 C are necessary. Here the Si substrate acts as supplier of the Si. This is a transformation process of the Si surface in an O2 environment to SiH4 . With increasing thickness of the SiH4 , the oxygen has to diuse through the already formed oxide to the interface. There is a distinction between dry and wet oxidation. In the dry oxidation of Si the wafer reacts with O2 to SiH4 . In the wet oxidation of Si, water vapor is owing on the Si surface.

3 Basics and procedures for the manufacturing of semiconductor devices

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At high temperatures, water cracks into pure hydrogen (H2 ) and in an OH-group. This diuses much faster through the already formed oxide due to the smaller size in comparison to the O2 molecule in the dry oxidation process. Therefore, the wet oxidation has up to three times higher growth rate than the dry oxidation. The oxide layer of the dry oxidation is however a denser oxide, which is resulting in higher breakdown eld strengths.

3.5 Metallization
There are two families of deposition processes described in the literature, the chemical and physical deposition techniques. These methods are used for the reproducible production of layers with no or only dened amount of impurities for variety of applications. Single crystalline or polycrystalline lms can be used as insulator, passivation, conductive layer or semiconductor heterojunction (deposition of a semiconductor onto one of dierent material, such as Si-Ge). The process step of metallization, necessary in this student laboratory, is performed by a method belonging to the physical vapor deposition (PVD). These procedures include the molecular beam epitaxy (molecular beam epitaxy, MBE), the evaporation and the sputtering. The MBE requires ultra-high vacuum and is for pure metal coating unprotable and costly. In the process of evaporation the material that is deposited on the wafer is heated in a melting crucible, boat or lament until it evaporates and the metal vapor condensates on the substrate. A variant of this process is that an electron beam is used to vaporize the target material. Because of the low deposition rate and the poor edge coverage, this procedure is primarily used for the complete wafer surface metallization, such as the back side of wafers. In the method of sputtering, which is used in this laboratory, ions hit out particles from the target (here: aluminum (Al)) and they condensate similar to the evaporation process on the substrate. As actinometric gas (gas which is ionized and passes its energy trough collision) argon and helium is used. The ionization of gases is done by plasma. Plasma can be generated by electromagnetic elds and electrostatic excitation and the charge carriers in it are increasing avalanche. The plasma is thus a formation of electron gas and ion gas. Since the charge carriers are generated in spatially close to each other, plasma is quasineutral. Plasma is the ionized state of matter and, in addition to solid, liquid and gaseous it is regarded as the fourth state. The most common occurrence in space is plasma. In everyday life for example we nd plasma in uorescent lamps.

3.6 Annealing
There are two kinds of metallic contacts on semiconductors: Schottky contacts and ohmic contacts. Besides on heavily doped layers, as deposited metal contacts show usually Schottky

3 Basics and procedures for the manufacturing of semiconductor devices

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behavior and without thermal annealing the contact show rectifying properties as a P-N junction. In order to create an ohmic contact the metal-semiconductor layer needs to be annealed. Here Al is used as metal contact. The wafers are heated up with at 5 C/min to 470 C and remained at this temperature for 60 min. After this the temperature is cooled down with 5 C/min. By slow cooling down process internal stresses and defects of the crystal structure, caused by previous processes can be healed.

3.7 Four-terminal sensing

The created doping concentration can be measured by using the so-called four-terminal sensing (also 4-wire sensing or 4-point probes method). In gure 3.4 the principle of this measurement is outlined. In this method, the resistance of a sample is measured by a sensor head with four probe tips which is placed on the surface. The four probe tips are arranged in series with a constant distance s of usually 0.5 to 1.5 mm. By the two outer contacts a low current is supplied in the range some milliampere, to keep the heating and thus a change in the electrical layer properties as small as possible. With the inner contacts, the voltage drop is measured. From these values, the sheet resistance is determined, by taking the potential lines in the semiconductor and the sample geometry into account.

Figure 3.4: Principle of the four-terminal sensing [Zim] It is dierentiated whether the sample thickness d is big or small in comparison to the probe tip spacing s. In our case d s and thus the equipotential regions are concentric cylinders perpendicular to the surface. The current paths are approximately perpendicular to these planes and thus, the current density can be taken as

3 Basics and procedures for the manufacturing of semiconductor devices

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J=

I 2rd

where r corresponds to the radius of each traversed region. For the electric eld it follows: E =J The voltage between the points 2 and 3 is calculated with the path integral of the electric eld strength E. The factor 2 takes into account the incoming and outgoing electric eld. V23 = 2
3 I 1 E ds = 2 ( )dr 2d r 2 2 2s I 1 I I =2 dr = (ln 2s ln 2) = ln 2 2d s r d d

(3.3) (3.4) (3.5)

This gives the sheet resistance as: Rs = V23 = d I ln 2

From the sheet resistance the carrier concentration can be concluded by means of the socalled "Irvine Curves". In Figure 3.5 dierent Si Irvine curves are shown. The graphs are for N and P doped material and the doping type, with innite and nite doping source. The abscissa shows the ohmic resistance multiplied by the junction depth xj in m.

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Figure 3.5: Irvine curves for dierent dopants and doping proles

4 Overview of the manufacturing process

The target of this student laboratory is to fabricate a Si-based layer structure which corresponds to the four-layer structure of the thyristor. Si substrates are the base material for the thyristor. In this case, they have a polished, shinny and a matte, non-polished side, which is very helpful to distinguish later on in the process. The doping is done using a furnace. For this a special substrate carrier called boat is used, which is load with the wafer and the source discs as shown in gure 4.1. The boat is made from quartz or from Si.

Figure 4.1: Fully loaded wafer boat without source discs (left) and schematic side view of wafer boat with Si-wafers and source disks (middle and right) The principle process of the p-type doping with boron is that rst a thin layer of silicon boride (SiB) is grow on the wafer. This is used in the further process as a nite doping source in the diusion process. In this laboratory the p-doping of the gate and anode area are fabricated rst, followed by the cathode area. For resulting in dierent p-doping levels of the gate and anode area, they have to be processed in two dierent steps or the side of the wafer with the expected higher doping level has to be processed again as described in the following. After loading the wafer boat with substrates and source disks, here boron nitride (BN) as shown in gure 4.1 (middle and right) into the furnace, in a rst step the boron nitride discs are oxidized in an O2 /N2 atmosphere at 700 C to B2 O3 . The generated oxide deposits on the Si surface. Here, the Si-surface pointing to the BN disk will be coated. For the deposition on a single side, a dummy wafer can be used to shield one side or two Si-wafers can be placed with the sides to each other that should remain uncoated (gure 4.1 right). The created oxide on the Si-wafer is reduced with 2 H2 in the gas phase from B2 O3 to HBO2 , which is a boron glass. This H2 step denes the intended amount of B on the Si-surface and therefore the doping concentration in the Si. The HBO2 on the Si-surface is formed in a N2 environment for 20 min at 750C to a thin SiB and SiO2 lm. This

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4 Overview of the manufacturing process

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SiB layer is the source that provides the impurities at the Si/SiB interface [RUG75]. The created glasses are removed with hydrouoric acid (HF), but SiB can not be etched with HF, but it must be removed, since it serves as impurity source and would result in a too high doping concentration. An additional temperature step ("Low Temperature Oxidation" - LTO) is necessary. The boron and a thin layer of Si underneath are oxidized for one hour at 850 C in an O2 atmosphere and can be then etched with HF later on. Thereby a specic doping concentration can be achieved. Since the desired concentration has now been reached, the boron atoms are driven into the substrate by diusion. As explained before, the doping depth can be managed by temperature and time. In this laboratory the wafers are heated up in the furnace to 1200 C. After each process step a standard cleaning has to be performed. By the described steps the wafer will have a P-N junction with a depth of 40 m for the P-layer at both sides, as shown in the left image of gure 4.2. As mentioned before the two sides can be doped with dierent doping levels. If a heavily doped anode area is requested (for example for electrical contact issues), the process is similar to that of the gate area, since it is the same doping type but dier in the concentration. Here the H2 step to form a boron glass is not used and therefore more material is left on the Si-surface to achieve a higher p-type doping concentration. The n-type doping of the cathode is reached by phosphorus diusion. The source discs are of cerium pentaphosphate (SiP2 O7 ), which is a layer on a chemically inert substrate. The diusion process is similar to that of the anode and gate, but here no oxidation step of the source material is required. At diusion temperatures the active component SiP2 O7 cracks in SiO2 , which remains on the source disk and P2 O5 -gas, which adsorbs and reacts on the Si-wafer. Depending on the desired doping concentration the diusion process takes place at 975 C to 1025 C for 20-80 minutes in presence of the source discs. The result of this diusion processes is the desired four-layer structure of the thyristor (gure 4.2 right).

Figure 4.2: P-N junction (left) and four-layer structure (right) after diusion process

4 Overview of the manufacturing process

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To create the aimed device from the described four-layered structure some process steps, such as lithography, etching, metallization and oxidation are necessary. These steps will transfer 3D-structures with dened areas of metallization and oxidization to the structure. A complete overview of the steps is shown in gure 4.3.

Figure 4.3: Fabrication steps of a GCT [Zim]

5 FEM simulation
The used software is the FEM simulation program TCAD 8.0 (Technology Computer Aided Design) from Integrated Systems Engineering (ISE), which is now owned by Synopsys Inc. It consists of several sub-programs which can be all controlled with the main interface GENESISe. With the help of scripts easily simulations with automated pass through of parameters can be realized. In the following the used subroutines are described briey. But TCAD has much more features than presented here. MDraw With the help of MDraw the geometric dimensions with the corresponding connections, the doping prole as well as the sizes of the grid that represent the nite elements are dened. Here a graphic tools or a script can be used. Dessis Dessis is the current FEM simulation program. It enables to record currents and voltages or other parts of a network at dened times. The graphical evaluation of the electric circuit and of the points to be measured is done text-based. The disadvantage is that there is no debugging tool and no automatic syntax control available. Therefore is not guaranteed, if the simulation is successful or if it must be repeated. Further the script oers the possibility to signicantly inuence the physical and mathematical context such as: Temperature Maximum electron saturation Band gap energy dierence Recombinationeects Carrier lifetime Number of iterations The device is built up in two dimensions. Dessis assumes a depth of 1 m and converts the simulation results by using an AreaFactor. The AreaFactor is dened as follows: AreaFactor =
Area Of Semiconductor Width Of Semiconductor1m

21

5 FEM simulation

22

Inspect With this tool, the simulation results at dened contacts can be shown as graphics in a coordinate system. This is also possible in-situ during the simulation. Ligament Ligament is a tool which allows simulating the manufacturing processes for semiconductors such as diusion processes and etching processes. It is used to determine the required diusion times and temperatures. The scripts provided with Ligament are translated and simulated with the subroutine Dios. Tecplot Tecplot is a visualization program which shows the characteristics of dierent device parameters. Depending on the content of the loaded input data, diusion proles, potential proles, eld strength curves, etc. can be shown in cross sections of the device.

6 Clean Room
The central laboratory of technology belongs to the Chair of Electromagnetic Theory (ITHE), the Institute of Materials in Electrical Engineering (IWE 1) and the Institute for Power Electronics and Electric Drives (ISEA). To work in a clean room certain rules must be considered. In order to keep a constant level of cleanliness in the clean room, it is necessary to wear clean room suits. These are used primarily to protect the cleanroom from contamination. The suit may be in one piece or consist of several separate garments worn tightly together, like gloves, caps and overshoes. The clean room area is entered through a so-called air shower. Two doors are passed to get into the clean room where only one door is allowed to be open at one time. The area between these doors is usually around 1 m2 . As soon the door from the grey room is closed, the door to the clean room is rst looked and is set free to open after a several time (10 sec to 30 sec). Within this time air is blown from the side and taken away from the top. By this possible particles on the clothes can be removed. Clean rooms are divided into classes. These classes represent the average density of particles per m3 . For example, "class 1" clean rooms (1 partikel/m3 ) have the highest level. Standard cleanroom classes are "class 1000" cleanroom and "class 100" cleanroom.

6.1 Preparation
The ISEA is using three rooms in the laboratory. They are needed for wet chemical cleaning, for plasma etching and the furnace processes. Because it is not an industrially used cleanroom, here in this clean room at the beginning of the work it is to ensure that the valves for DI-water and the required gases and acids for cleaning of the substrates are opened.

6.2 Wafer Cleaning

The processing of semiconductors requires perfect cleaned wafer surfaces, to guarantee reproducible results and device performance. Impurities that are not removed will diuse deep into the Si wafer in the many fabrication steps, since some of them occur at high temperatures. This leads to unwanted doping types and concentrations. Therefore sophisticated cleaning procedures have been developed. For the cleaning procedure additional protective clothing is necessary. As acids like HF, hydrochloric acid (HCl) and sulfuric acid (H2 SO4 ) are used for the wet chemical cleaning.

23

6 Clean Room

24

Since 1971, the so-called "RCA Clean" became a standard wet chemical cleaning process, which is named after the company "Radio Corporation of America" [MOK06]. This method consists of two dierent processes, the "RCA 1" and the "RCA 2". For heavily contaminated wafers the so-called "Piranha-etch" is done rst. In the following the dierent etch steps are described briey [MOK06]] [SPA06b]. Piranha etching With this acid mixture organic contaminations can be removed. For this the Si wafer will be left ten minutes in this solution. This mixture consists of: H2 O2 (25%) : H2 SO4 (97%) 1: 2 RCA 1 These etch step removes also mainly organic contaminants. It consists of H2 O2 , ammonium hydroxide (NH4 OH) and DI-water and is used in the following ratio: H2 O2 (25 %) : NH4 OH(25 %) : H2 O 1: 1: 2 The H2 O2 oxidizes the wafer surface and the particles on it, by this the adhesion forces decrease between particles and wafer. The particles move into solution and the wafer surface is protected by the oxide layer from recontamination. At the same time, the ammonium hydroxide etches the wafer surface and undercuts the particles [ASS07]. The duration of this cleaning step is ten minutes. RCA 2 In combination with H2 O2 hydrochloric acid (HCl) is a very eective solution for the removal of metallic contaminations. It is used the following ratio: HCl(30 %) : H2 O2 (25 %) : H2 O 1: 1: 2 HF-Dip Since by H2 O2 , which is used in all described cleaning steps, SiO2 is formed on the wafer, it must be removed by using HF. The duration of this process depends on the thickness of the oxide layer. The etching speed of 5% HF (5% HF in DI water) is about 50 nm/min at room temperature [BOG67]. The SiO2 is thereby converted into a soluble complex salt [RUG75]:

6 Clean Room SiO2 + 6HF H2 SiF6 + 2H2 O

25

Since SiO2 is strongly hydrophilic, but pure Si in contrary hydrophobic, this behavior can be used as an indicator for a successful cleaning. For the processing of the PNPN structure in this student laboratory always the same cleaning procedure is used between each fabrication step. The acid mixtures and etch duration are used as following: 1. Piranha etching 2. Rinsing with DI-water 3. HF dip for 3 min 4. Rinsing with DI-water 5. RCA 1 cleaning 6. Rinsing with DI-water 7. HF dip for 3 min 8. Rinsing with DI-water 9. RCA 2 cleaning 10. Rinsing with DI-water 11. HF dip for 3 min 12. Rinsing with DI-water

6.3 Safety instructions

The work with acids requires special attention. In direct contact with the skin they lead to burning of the skin or even eating through. Here especially the dangers of HF are described. This acid etches locally at the area of touch. It penetrates the skin very quickly and cause serious etching of the deeper skin. Here especially the binding with magnesium and calcium ions is very critical. Without calcium the local nerves are not able to transmit any information. Therefore no pain is felt at all and the symptoms may get visual hours later (Figure 6.1). This results in acute life-threatening metabolic disorder or liver and kidney failure. The lethal dose for humans is 70 - 140 mg/kg body weight. Road map for rst aid: 1. Emergency Service Request 2. Pay attention to self-protection (protective clothing, acid-proof gloves) 3. Move injured person from area of danger 4. Remove contaminated clothing 5. Wash/rinse aected area with a lot of water 6. Person with breathlessness to lie with upper body in higher position

6 Clean Room

26

7. Initiate resuscitation at apnea

Figure 6.1: Acid burn with HF

7 Experiment 1: Introduction into the properties and fabrication of GCTs

The student laboratory starts with an introduction into the properties and fabrication of GCTs which will be performed interactive. The participating students have to be prepared by having an overview about this device and its fabrication by using the chapters 1 to 6. The fundamental basics of GCTs and the fabrications steps are discussed briey including the introduction into the simulation and the clean room. To have a better overview real devices and their housing are presented to understand the device properties and especially its fabrication.

27

8 Experiment 2: Introduction into the device simulation tools

In the following the work with TCAD 8 is described. These instructions will be needed for the device simulation.

Figure 8.1: Crosssection of the Simulated GCT In the simulation with TCAD only a section of the whole device is simulated. This section includes the used dimensions and doping concentrations is shown in Figure 8.2. The used dopants are phosphorus for the n-doping and boron for the p-doping.

8.1 Introduction into the device simulation tools

To start TCAD 8, a X-Win32 server needs to be started. The UNIX server can be found under Start\Progamme im ISEA\Tools\X-Win32\X-Win32.

28

8 Experiment 2: Introduction into the device simulation tools

29

TCAD is located under Start\Progamme im ISEA\Elektrotechnik\TCAD 8\GENESISe. First, create a folder with your group number in the directory: Desktop\My Computer \X:\Sim\5001_Thyristorbau_bn \IHR GRUPPENORDNER. Then start TCAD. After a loading time a folder tree can be seen, select than the created folder. GENESISe GENESISe is the main interface to access the various subroutines. The geometric dimensions, connections and doping proles are recorded in a text le using MDraw. To work with the programs a new project must be created. Create additionally a folder and label it with your group name. The project needs to be activated for editing. For this select it and then click on the Activate-Button, see Figure 8.2.

Figure 8.2: Creation of a project in TCAD MDraw To start MDraw, open the Toolbox and drag MDraw into the left part of this window (Figure 8.3). Do the same with Dessis. Select the MDraw icon and click in the menu bar Edit\input\preferences. Change the setting "Excecution Mode" in "Start in batch mode". Run MDraw by clicking in the menu bar Edit\input\Boundary. If the Unix Sever is not active, then MDraw can not be started. If the server runs a window will appear asking for a connection to a host, in this case select "Immer so verfahren and click Ja". Afterwards the graphical interface of MDraw will be started. With MDraw the two-dimensional side prole will be created and then converted into three-dimensional with a depth of 1 m. It can not

8 Experiment 2: Introduction into the device simulation tools

30

simulate rotation symmetric components. On the left side there is a bar which provides the dierent tools. In the downer part there are tools to change the graphical appearance. Here options are presented with which various prole levels or an auxiliary grid can be shown or hide. The two lowest points Doping and Boundary oer the possibility to distinguish between the doping/diusion tools and the geometric tools.

Figure 8.3: To start MDraw it has to be introduced into the simulated process Boundary The geometric dimensions will be developed graphically and then stored in a text le. For a very precise description of the dimensions there is in the tool bar the button "exact Coordinates". By this the exact coordinates of a point can be typed in. With the help of "Add Rectangle", "Add Point" and "Move Point", the device can be represented as in Figure 8.4. In Boundary mode also the connection points like anode, cathode and base can be dened. To set a contact it must be rst dened in the toolbar in the window "Contacts" and then selected. With "Set/Unset Contacts" the contact point is set to the dened place. Doping The assignment of doping concentrations to the device can be performed in the "Doping mode". In Table 8.1 the individual functions of the tools are listed up. Substrate First the substrate must be doped using the "Add Constant P". tool. For this the complete area of the side prole has to be selected. After this a window like in Figure 8.5 appears.

8 Experiment 2: Introduction into the device simulation tools

31

205 m Gate -175 m

Kathode 10m

515 m

Anode- 325 m

Figure 8.4: The shape and dimensions of the structure to be created Tool Add Constant P. Add Analytic P. Add Renement Build Mesh Eect Generates homogenous doping To position the deposited impurities Here the grid size will be determined Creates the doping prole and shows it a graphic

Table 8.1: Tool overview in Doping-mode.

The donor concentration of the base material is around 1 1014 cm3 . In the menu bar under View\List of Proles the properties can be seen and edited subsequently. Also the coordinates need to be corrected. Gate, anode and cathode Since the doping proles of anode, cathode and gate are dened by high-temperature processes, they have not homogeneous concentrations (see Chapter 3). Create with the command Add Analytic P. rst the anode contact. Pull the vector arrow over anode contact. Correct the settings if necessary in the appearing window. Take from Figure 8.1 the doping depths and concentrations. Add after that the cathode and gate area (see chapter 2.5). After the doping proles have been created, a grid has to be dened for each region. Use for this the command "Add Renement". Under View\List of Renements, it is possible to carry out subsequent changes. You can change the duration and the accuracy of the FEM simulation. The smaller/ner the grid is selected, the longer the calculation takes and also more precise the results are. Build Mesh With the button Build Mesh the grid is generated and displayed. Doping concentrations are associated with dierent colors. Under "Functions" in the menu bar dierent views

8 Experiment 2: Introduction into the device simulation tools

32

Figure 8.5: Setting of the substrate background carrier concentration are available. In addition further display options are in the toolbar. Figure 8.1 shows the nished device in BoronActiveConcentration.

8.1.1 Device Simulation

By using the basics of the previous chapters (5 and 8.2) set the spatial points and the impurity concentration of the thyristor. In order to understand the electrical behavior a theoretical electric circuit will be established in Dessis and simulated with DUT (Device Under Test). Basic functions of Matlab are used for a better evaluation of the simulation results in the second part of the experiment. 8.1.1.1 Structure of the network Dessis oers the Mixed-Mode. There it is possible to place the physical semiconductor device simulation on FEM-basis into a circuit of ideal devices, which are dened by analytical equations. In Figure 8.6 the power supply on the left hand side reects the low voltage source. When DUT is running, the current of the power source ows directly through it. While switching it o the current commutated to the diode D and continues to charge rst the capacitor CCl which is preloaded by nominal voltage with a constant current and Uc . The capacity was set to 24 nF. When linear voltage increase according to Ic = C dd t the capacitor voltage reaches the voltage Vblock , the diode DCl starts to conduct. Since the internal resistance of the ideal voltage source, the voltage will not rise further. The voltage source has to be adjusted to the desired maximum voltage magnication. Here a Vblock

8 Experiment 2: Introduction into the device simulation tools

33

value of 1.2 kV is used. Before the actual switching procedure and for a proper working the capacitor must be preloaded (here: 1 kV). This is done by turning on the current source rst (here: 400 A) while the GCT is switched o. If the voltage source is also turned on, the capacitor voltage starts rising and after charging the capacitor the GCT is turned on. The capacitor voltage remains constant now and after settling all levels (around 20 s), the actual turn o sequence can be carried out. The contacting of the gate is as shown in Figure 8.6 with a 2 Ohm resistance RG to limit the current during power up. When turning on the other hand, this resistance is bridged through the diode DG , because then the voltage source VG is switched to -20 V and the current direction points out of the gate.

Figure 8.6: External circuit of the DUT during the simulation Task 1. To characterize the device, build up the virtual test bench shown in Figure 8.6. In the le "des.cmd" there is the section "Solve" in which the static, transient and quasitransient operations can be solved. In the following the necessary commands are presented. Most important commands are summarized here. They are sucient to meet the tasks. In addition there is a manual under Start\Progamme im ISEA\Elektrotechnik\TCAD 8\Online Manuals Manuals available. Set (n0=0): This forces the potential of a node n0 to 0 V. unset (n0): Cancels the Set command. Vsource_pset V_0 (n1 gr) {pwl=(0 0)}: Creates an ideal voltage source with the name of V_O from input node n1 to the grounding point gr. The parameters pwl will be described in the next. Isource_pset I_0 (gr n1) {pwl=(0 0)}: Produces an ideal current source with the name I_0 from input node gr to the grounding point n1. The parameters pwl will be described in the next.

8 Experiment 2: Introduction into the device simulation tools {pwl = (0 0 1e-6 2e-6 3e-6 4e-6

34

500 1000 500 0)

Table 8.2: Example Code

Resistor_pset R (n2 n3) {resistance=1}: Creates resistance R with value of 1 between points n2 and n3 Diode_pset D1 (n1 n2): Creates diode D1 with the anode n1 and the cathode n2. Capacitor_pset C (n1 n2) {capacitance=1e-6}: Creates ideal capacitor C with 1F between nodes n1 and n2. # Comments: Include line comments Transient ( InitialTime=0 FinalTime=1000 InitialStep=10 MinStep=1 MaxStep=5) { statement }: Since a transient (time-dependent) simulation is performed, the calculation must be based on cycle time.

Figure 8.7: Generated curve with code from Table 8.2 With the parameter pwl (piece-wise-linear) of the voltage and current source it is possible to dene time-dependent constant voltages/currents. Referring to a voltage source the example code in Table 8.2 generates the curve shown in Figure 8.7. For clarity, as shown in the example Table 8.1, the times (the rst parameter) and the voltages/currents should be below each other. The rst value indicates the time and the "e-6" for the order of

8 Experiment 2: Introduction into the device simulation tools

35

magnitude "106 " (=s). The second value gives the voltage in volts or the current in amperes, depending on which source is implemented. Tasks 1. The thyristor should have an area of 1 cm2 . Calculate the "Area Factor" and paste it into the "des.cmd" le. 2. What are the tasks of the various devices of the test bench (the capacitor CCL and the diode DCL were introduced on basis of numerical convergence problems, so they are negligible)? 3. How should be the time characteristics of the source in order to get a useful measurement of the device? 4. Program the network according Figure 8.6! The nodes and names of the components are dened and should be used. 5. Write a reasonable Solve -section! 6. Start the simulation!

9 Experiment 3: Device and Process simulation

9.1 Inspect, Tecplot
Inspect Inspect can be nd in the main interface of GENESISe symbolized by an oscilloscope. While the simulation data is recorded and therefore already available, the data can be accessed through Family Editor. In Figure 9.1 the main window of Family Editor is shown. On the right side, the various stages of the simulation are shown and on the left side the results of the simulation. With the left mouse button the icons can be dragged into the programs Inspect and Tecplot. These will then run with the loaded data. Inspect plots the data. For this variables can be addressed to the X-axis and to the Y-axis. The operation is intuitive. More information can be found under Start\Progamme im ISEA\Elektrotechnik\TCAD 8\Online Manuals - Inspect. Tecplot To work with Tecplot the command Plot ( Time = ( 400e-6)) has to be added in the Solve section of the Dessis-le for a plot of all points in the Plot section at 400 s. In Tecplot three dimensional data can be displayed, e.g. E-elds or thermodynamic stresses.

Tasks Create by using Matlab, Tecplot and Inspect the following graphs: 1. Current and voltage behavior during switching on/o (Inspect) 2. Energy losses during switching on/o (Inspect) 3. Electric eld strengths in the device, at constant current (Tecplot) 4. Recombination eects/lifetime of charge carriers (Inspect) 5. Carrier concentrations as function of the current (Inspect) 6. Current density in the device (Tecplot)

36

9 Experiment 3: Device and Process simulation

37

Figure 9.1: Main window of Family Editor

9.2 Process simulation

GENSESISe oers the possibility to simulate furnace processes and to create new furnace processes by using the simulation results. The goal of this experiment is not to create a complete program but to give a brief insight into the principles of the program and show how furnace processes will be developed. Ligament and Dios Open in GENESISe the program folder Ofenprozesssimulation_bn. To see the progress in Ligament add in ISE Tool Flow Editor the program Ligament. To start click on Edit\Input\Commands. Ligament provides a clear arranged graphical interface to create a script, which includes furnace process operations. This script is passed to Dios, which simulates the processes. In Figure 9.2 the graphical user interface of Ligament is shown. For comparison: In Dessis the

9 Experiment 3: Device and Process simulation

38

script must be written itself, otherwise the operation of the simulation programs is the same. It is also possible to write the script directly in Dios, or rewrite without using ligament.

Figure 9.2: Furnace process simulation in Ligament

Tecplot Tecplot is a visualization program which illustrates additionally the data obtained by the simulation. Depending on the content of the loaded input data, diusion proles, potential proles, eld strength curves, etc. can be shown as cross sections of the device. To open, click in the interface of Genesis on Tecplot and to download the simulated results from Dios click on Datei\Importieren. Select the DF-ISE Loader and load the les n1_dio.dat.gr and n1_dio.grd.gr. Figure 9.3 shows simulated doping prole of the device in two dimensions. The doping level is represented by the color. By a cut at any X position of the device the doping prole is shown as a graph. It is necessary that the X-position is within the device, in this case between 0 m and 10 m. For the cut, go to Tools \ISE TCAD Tools. Under Utilities\x-Normal Cut the X position for the cut has to be given. In addition, under Variables the types of impurities can be changed.

9 Experiment 3: Device and Process simulation

39

Figure 9.3: Doping prole simulated by Tecplot.

Tasks 1. Calculate with the help of Ligament and Dios the diusion times t1473k at 1200 C to achieve, at the desired depth of the gate. Compare t1473k with diusion times at 1000 C and 1350 C. 2. What problems occur at 1350 C?

10 Experiment 4: Clean room and safety introductions, start of thyristor fabrication; substrate preparation and doping
The Central Laboratory is located in the Otto-Blumenthal Str. 3 next to the Walter Schottky Haus. Here all the experimental work will be done. First there will be an introduction into the safety and behavior in a clean room. At the beginning you will receive a batch card. This is a kind of schedule including all fabrication steps. In this card the process status of each step has to be documented. For dierent deposition/diusion processes (Chapter 3.1 and 4) there are specic boats used. Table 10.1 shows for which process which boat is used: identier boot name WQE03312204-001 BN - HT process name bn-depo.prz Reaktiv.prz WQE03312204-002 phosphorus ph-depo.prz WQE03312204-004 BN-975 depo_975.prz LTO&DIFF.prz LTO.prz Table 10.1: List of available boats for the dierent diusions processes.

40

10 Experiment 4: Clean room and safety introductions, start of thyristor fabrication; substrate preparation and doping

41

In Figure 10.1 the junction depths are shown as a function of the deposition temperatures. There have been various measurements performed and then extrapolated with Matlab. The temperature was varied, therefore the diusion process for all deposition temperatures is the same.

60 55 50
Junction Depth in m
Measured Model Polynomisch (Measured)

45 40 35 30 25 20 800

900

1000

1100

1200

1300

Temperature in C

Figure 10.1: Junction depth as function of deposition temperature The graph in Figure 10.2 shows the boron concentration of the anode as a function of the deposition temperature. It was measured after the diusion, without changing the diusion process. This graph results from the measurement of the sheet resistance and from the direct comparison with the Irvine curves. Remark Take into account that the diusion process is variable. Furthermore, it can be assumed that the surface concentration is independent of the diusion process.

10 Experiment 4: Clean room and safety introductions, start of thyristor fabrication; substrate preparation and doping

42

1,00E+20

Surface Concentration in cm^-3

1,00E+19

1,00E+18

1,00E+17 800

850

900

950

1000

1050

1100

1150

1200

1250

1300

Deposition Temperature in C

Figure 10.2: Surface concentration as function of deposition temperature after diusion Tasks: 1. Perform a standard cleaning according to the batch card. 2. Determine from the Figures 10.1 and 10.1 the required deposition temperature. Consider the remark! 3. Perform the gate and anode deposition.

11 Experiment 5: Four-point, diusion depth, oxide layer growth and metallization

At least one of the doped samples needs to be characterized before continuing with the fabrication. It is import to measure the sheet resistance of the doped layer and to verify if the doping depth is in a sucient range. The measurement of the sheet resistance is done by the method of the four-terminal sensing according Chapter 3.7. For the determination of the doping depth the wafer has to be cut rst into pieces. The sample that will be measured is then xed on a customized mount (see Figure 11.1, left). This mount holds the sample surface 3-4 tilted and is placed in the polishing tool shown in the right image of Figure 11.1.

Figure 11.1: Customized sample mount with sample (left) and polishing tool (right). The oxide layer (insulating layer) is very important to separate the gate and the anode area. The oxide layer is deposited on the whole substrate (see Figure 4.3, starting at number 4). Afterwards it is patterned that and covered completely with aluminum. Because it take too long if the whole work is done in here, the etching and cleaning step between the oxide layer and the metallization is not done here. Tasks 1. Measure the sheet resistance of the gate of one wafer and determine the doping level! 2. Perform a standard cleaning for the remaining wafer. 3. What happens to the wafer if they have not been processed for a longer time?

43

11 Experiment 5: Four-point, diusion depth, oxide layer growth and metallization 4. Dice a wafer and wafer dummy into equal squares! 5. Prepare the pieces for the polishing process! 6. Grind the pieces of the wafer/dummy wafer!

44

7. Treat the polished surfaces with HF under UV light! What change occurs on polished surface? 8. Describe the principles of the oxide layer growth!

12 Experiment 6: Lithography, etching and measurement of the etch prole

In order to reach each contact area of the device, some material needs to be removed. For the gate contact it is necessary to get direct access to the p-type doped area. In chapter 3.2 and 3.3 the patterning of a wafer is described. Subject of this experiments is the fabrication of the contact area of the gate and the subsequent verication. 1. Prepare the substrates by chemical cleaning! 2. Describe how to achieve a pattern on a wafer! 3. Create the pattern based on a mask onto the wafer (coating, photolithography, plasma etching (pumpdown takes long?))! 4. Measure the etched prole (tool for measurement will be introduced). (Tencor) 5. Create you own mask and verify it according to instructions, that will be given.

45

13 Experiment 7: Visit Inneon, last experimental steps

To have a better insight into the industrial production of GCTs and to process steps not available at the institute, an industrial production site will be visited.

46

14 Experiment 8: Device measurement

To have a better insight into the industrial production of GCTs and to have access to process steps not available at the institute, an industrial production site will be visited. 1. Record with an oscilloscope the characteristic of the thyristor with a maximum current of 20 A and a maximum voltage of 100 V. 2. What are the dierences in comparison to the simulated results?

47

15 Experiment 9: Presentation
This student laboratory will be nished with a presentation prepared by each group. The groups will be informed about topic of the presentation.

48

List of Figures
1.1 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.3 3.4 3.5 4.1 4.2 4.3 6.1 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9.1 9.2 9.3 Applications elds of power devices [ISEA] . . . . . . . . . . . . . . . . . . . PNPN structure of a thyristor [ISEA] . . . . . . . . . . . . . . . . . . . . . . Space charge regions with the corresponding I-V-characteristics for a) reverse, b) blocking, c) conducting [ISEA] . . . . . . . . . . . . . . . . . . . . . . . . Switching of the thyristor at suciently high reverse current in the forward mode [ISEA] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The four layer structure of the thyristor replaced by two transistors. Right image shows the equivalent circuit diagram of a thyristor as a pair of tightly coupled bipolar junction transistors.[ISEA] . . . . . . . . . . . . . . . . . . . Structure of four-layer sequence of a thyristor including the contacts . . . . . Diusion behavior for innite (left) and nite (right) dopant source [Zim] . . Photomask for thyristor process (right) and dierence of positive and negative resist (right) [Zim] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Etching process by SF6 and O2 [Zim] . . . . . . . . . . . . . . . . . . . . . . Principle of the four-terminal sensing [Zim] . . . . . . . . . . . . . . . . . . . Irvine curves for dierent dopants and doping proles . . . . . . . . . . . . . Fully loaded wafer boat without source discs (left) and schematic side view of wafer boat with Si-wafers and source disks (middle and right) . . . . . . . P-N junction (left) and four-layer structure (right) after diusion process . . Fabrication steps of a GCT [Zim] . . . . . . . . . . . . . . . . . . . . . . . . Acid burn with HF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crosssection of the Simulated GCT . . . . . . . . . . . . . . . . . Creation of a project in TCAD . . . . . . . . . . . . . . . . . . . To start MDraw it has to be introduced into the simulated process The shape and dimensions of the structure to be created . . . . . Setting of the substrate background carrier concentration . . . . . External circuit of the DUT during the simulation . . . . . . . . . Generated curve with code from Table 8.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3 5 6 8 11 12 13 15 17 18 19 20 26 28 29 30 31 32 33 34 37 38 39 41

Main window of Family Editor . . . . . . . . . . . . . . . . . . . . . . . . . . Furnace process simulation in Ligament . . . . . . . . . . . . . . . . . . . . . Doping prole simulated by Tecplot. . . . . . . . . . . . . . . . . . . . . . .

10.1 Junction depth as function of deposition temperature . . . . . . . . . . . . .

49

List of Figures 10.2 Surface concentration as function of deposition temperature after diusion . 11.1 Customized sample mount with sample (left) and polishing tool (right). . . .

50 42 43

List of Tables
3.1 8.1 8.2 Chemical reaction during the etching process . . . . . . . . . . . . . . . . . . Tool overview in Doping-mode. . . . . . . . . . . . . . . . . . . . . . . . . . Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 31 34 40

10.1 List of available boats for the dierent diusions processes. . . . . . . . . . .

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Bibliography
[MiCh1] MicroChemicals: Lithographie, Theorie und Anwendung von Fotolacken, Entwicklern, tzchemikalien und Lsemitteln., MicroChemicals GMBH, Ulm, Deutschland, 2007 Bayrische Gemeindenfallversicherungsverband Hchste Vorsicht beim Umgang mit Flusssure!, http : //www.bayerguvv.de/download/uva1011 7.pdf

[GUVV]

[Vollmer] Dr. Michael Vollmer: Flusssure - Fluorwassersto !, http : //www1.tu darmstadt.de/pvw/dezi v/a/info/vollmer.ppt [MiCh2] MicroChemicals: Substratreinigung und Haftvermittlung, http : //www.microchemicals.com/technische_infos/substrat_reinigung _haftung_fotolack.pdf Josef Lutz: Halbleiter- Leistungsbauelemente, Springer Verlag, Berlin 2006, Deutschland ISEA: Bauelemente Nachdruck zum Vorlesungsskript aus dem Sommersemester 2005, ISEA, Aachen, Juni 2007 Jella Zimmermann: Design, Simulation und Prozessaufbau einer DUAL-GCT Struktur, ISEA Diplomarbeit, Aachen, Mrz 2009 Michael Bragard: Entwurf und Realisierung eines DUAL-GCT Hochleistunghalbleiters, ISEA, Aachen, Oktober 2006

[Lutz] [ISEA] [Zim] [Bra]

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