SPCA701A

DIGITAL VIDEO ENCODER FOR VIDEOCD

GENERAL DESCRIPTION
The SPCA701A is designed specifically for VideoCD, video games and other digital video systems, which require
the conversion of digital YCrCb (MPEG) data to analog NTSC/PAL video. The device supports a glue-less
interface to most popular MPEG decoders. The SPCA701A supports worldwide video standards, including
NTSC (N America, Japan) PAL-B, D, G, H, I (Europe, Asia). Furthermore, the SPCA701A operates with a
single 2x clock and can be powered with a single 3.3V supply. The composite analog video signal is output
simultaneously onto two outputs. Therefore, it allows one output to provide base-band composite video while

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PIN DESCRIPTION (Table 1.)

Mnemonic PIN No. Type Description
DATA[7:0] 21 - 28 I YCrCb pixel inputs. They are latched on the rising edge of CLK. YCrCb
input data conform to CCIR 601.
CLK 29 I Pixel clock input.
V219.054t7Tc0.8(054 658.088 ref129.054 658.062 0t902 13(219.0.054 658.062 0-7.8(e)i 658.062 0t94 658.062 782 0.6 -3

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Mnemonic PIN No. Type Description

CVBSY 4 O Composite/Luminance output. This is a high-impedance current source
output. The output format can be selected by the PAL pin. The
CVBSY can drive a 37.5  load. If unused, this pin must be connected
directly to GND.
CVBSC 11 O Composite/Chroma output. This is a high impedance current source
Output. The output format can be selected by the PAL pin. The pin
can drive a 37.5  load. If unused, this pin must be connected directly
to GND.

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Table 3. Configuration Register Settings

Mode Register Name Set to 0 Set to 1 Comments
EFIELD The VSYNC pin will output The VSYNC pin will This is only used at
normal vertical output field signal. Low master mode.
synchronization signal. at VSYNC pin for even
field, high for odd field
PAL625 525-line operation will be The 625-line operation This is only used at
select will be select master mode
YCSWAP Do not swap Y and Cr/Cb Swap Y and Cr/Cb ----
sequence

CLOCK TIMING
A clock signal with a frequency twice the luminance sampling rate must be present at the CLK pin. All setup and
hold timing specifications are measured with respect to the rising edge of this signal.

PIXEL INPUT TIMING

PIXEL SEQUENCE
Multiplexed Y, Cb, and Cr data is input through the DATA[7:0] inputs. By default, the input sequence for active
video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc., in accordance with CCIR-656. This pattern
begins during the first CLK period after the falling edge of HSYNC* (regardless of the setting of SLAVE/MASTER
mode). The order of Cb and Cr can be reversed by setting the CBSWAP pin. Figure 1 illustrates the timing.
If the pixel stream input to the SPCA701A is off by one CLK period, the SPCA701A can lock to the pixel stream
by setting the YCSWAP register. This would solve the problem of having the Y and Cr/Cb pixels swapped.

Figure 1. Pix Sequence

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VIDEO TIMING
The width of the analog horizontal sync pulses and the start and end of color burst is automatically calculated and
inserted for each mode according to CCIR-624-4. Color burst is disabled on appropriate scan lines.
Serration and equalization pulses are generated on appropriate scan lines. In addition, rise and fall times of
sync, and the burst envelope are internally controlled. Video timing figures follow the text in this section.

SYNC AND BURST TIMING

Table 4 lists the resolutions and clock rates for the various modes of operation.
Table 5 lists the horizontal counter values for the end of horizontal sync, start of color burst, end of color burst,
front porch, back porch, and the first active pixel for the various modes of operation. The front porch is the
interval before the next expected falling HSYNC* when outputs are automatically blanked. The horizontal sync
width is measured between the 50% points of the falling and rising edges of horizontal sync. The start of color
burst is measured between the 50% point of the falling edge of horizontal sync and the first 50% point of the color
burst amplitude (nominally +20 IRE for NTSC and 150 mV for PAL-B, D, G, H, I above the blanking level). The
end of color burst is measured between the 50% point of the falling edge of horizontal sync and the last 50% point
of the color burst envelope (nominally +20 IRE for NTSC and 150 mV for PAL-B, D, G, H, I above the blanking
level).

Table 4. Field Resolutions and Clock Rates for Various Modes of Operation
Operating Mode Active pixels Total Pixels CLK Frequency (MHz)
NTSC CCIR601 720 x 240 858 x 262 27
PAL-B,D,G,H,I 720 x 288 864 x 313 27

Table 5. Horizontal Counter Values for Various Video Timings

Horizontal Duration of Back
Operation Mode Front porch (a) Start of Burst (c)
Sync Width (b) Burst (d) porch (e)
NTSC CCIR601 20 63 72 34 127
PAL-B CCIR601 20 63 76 30 142
Notes: (1) The unit is the number of luminance pixel.

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VERTICAL BLANKING INTERVALS

For NTSC, scan lines 1-9 and 263-272, inclusive, are always blanked. There is no setup on scan lines 10-21
and 273-284 inclusive. All displayed lines in the vertical blanking interval (10-21 and 273-284 for interlaced
NTSC; 7-13 and 320-335 for interlaced PAL-B, D, G, H, I) are forced to blank. For PAL-B, D, G, H, I, scan lines
1-6, 311-318, and 624-625, inclusive, during fields 1, 2, 5, and 6, are always blanked. During fields 3, 4, 7, and
8, scan lines 1-5, 311-319, and 624-625, inclusive, are always blanked.

DIGITAL PROCESSING
Once the input data is converted into internal YUV format, the UV components are low-pass filtered with a filter.

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Figure 2. Interlaced 525-Line (NTSC) Video Timing

523 524 525 1 2 3 4 5 6 7 8 9 10 22

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Figure 3a. Interlaced 625-Line (PAL) Video Timing

620 621 622 623 624 625 1 2 3 4 5 6 7 22 23 24

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Figure 3b. Interlaced 625-Line (PA L) Video Timing

Start
of
VSYNC

620 621 622 623 624 625 1 2 3 4 5 6 7 22 23 24

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PIXEL INPUT RANGES AND COLORSPACE CONVERSION

YC INPUTS (4:2:2 YCRCB)
Y has a nominal range of 16-235; Cb and Cr have a nominal range of 16-240, with 128 equal to zero. Values of
0 and 255 are interpreted as 1 and 254 respectively. Y values of 1-15 and 236-254, and CrCb values of 1-15
and 241-254, are interpreted as valid linear values. NTSC mode with setup disabled has 2% less black-to-white
range than NTSC mode with setup enabled.

DAC CODING
White is represented by a DAC code of 400. For PAL-B, D, G, H, I, the standard blanking level is represented
by a DAC code of 120. For NTSC, the standard blanking level is represented by a DAC code of 114, 1 IRE is
equivalent to a DAC code of 2.857.

OUTPUTS
All digital-to-analog converters are designed to drive standard video levels into an equivalent 37.5  load.
Unused outputs should be connected directly to ground to minimize supply switching currents. Either two
composite video outputs or Y/C S-Video outputs are available (selectable by the SVIDEO pin). If the SLEEP pin

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COMPONENT PLACEMENT
Components should be placed as close as possible to the associated pin. The optimum layout enables the
SPCA701A to be located as close as possible to the power supply connector and the video output connector.

POWER AND GROUND PLANES

For optimum performance, a common digital and analog ground plane is recommended. Separate digital and
analog power planes are recommended. The digital power plane should provide power to all digital logic on the
PC board, and the analog power plane should provide power to all SPCA701A power pins, VREF circuitry, and
COMP decoupling. At least a 1/8-inch gap is required in between the digital power plane and the analog power
plane. The analog power plane should be connected to the digital power plane (VCC) at a single point through a
ferrite bead, as illustrated in Figure 4, Table 6. This bead should be located within 3 inches of the SPCA701A.
The bead provides resistance to switching-currents, acting as a resistance at high frequencies. A low-
resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001.

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Figure 4. Typical Connection Diagram (Internal Voltage Reference)

Analog Power Plane

SPCA701A VAA L1
+3.3V (VCC)
C4

C2,C3
COMP
VREFIN C6 C1
VREFOUT
C5
Ground
GND (Power Supply
RESET

Connector)

FSADJUST

L2 (2)
CVBS/Y Buffer P RF Mod
+
To Video
L3 (2) Connector
CVBS/C Buffer P LPF
+
VAA
P
Schottky Diodes

DAC Output To Filter

Schottky Diodes

GND Regulated +5V

LPF

22pF 22pF 1k
75 10
H RF
75 Modulator (1) RF
ZIN = 1K
1.8
H 1.8
H

82
270pF 330pF 270pF 330pF Audio

TRAP

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Table 6. Typical Parts List (Internal Voltage Reference)

Locations Description Vendor Part Number
C5 - 1, C7 0.1 F Ceramic Capacitor Erie RPE112Z5U104M50V
C6 47 F Capacitor Mallory CSR13F476KM
L1 Ferrite Bead - Surface Mount Fair-Rite 2743021447
L2, L3 Ferrite Bead(z < 300 @ 5MHz) ATC LCB0805, Taiyo Yuden BK2125LM182
RESET 1% Metal Film Resistor Dale CMF-55C
TRAP Ceramic Resonator Murata TPSx.xMJ or MB2 (where x.x = sound
carrier frequency in MHz)
Schottky Diodes BAT85 (BAT54F Dual) HP 5082-2305 (1N6263)
Siemens BAT 64-04 (Dual)
Note: Vendor numbers are listed only as a guide. Substitution of devices with similar characteristics will not affect

SPCA701A performance.

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PACKAGE INFORMATION

Model Number Package Ambient Temperature Range

SPCA701A 32-pin PLCC 0
- 70

NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to

improve the design and performance to supply the best possible product

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inches mm
Symbol
Min. Typ. Max. Min. Typ. Max.
A 0.1 - 0.14 2.54 - 3.56
A1 0.06 - 0.09 1.52 - 2.41
B 0.013 - 0.02 0.33 - 0.53
B1 0.026 - 0.03 0.66 - 0.81
D 0.485 - 0.49 12.3 - 12.57
D1 0.447 - 0.45 11.3 - 11.56
D2 0.39 - 0.43 9.91 - 10.92
E 0.585 - 0.59 14.8 - 15.11
E1 0.547 - 0.55 13.8 - 14.1
E2 0.49 - 0.53 12.5 - 13.46
e - 0.05 - - 1.27 -
N - - - - 32 -
Nd - - - - 7 -
Ne - - - - 9 -

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