CMOS Digital Integrated Circuits

Chapter 9 Dynamic Logic Circuits

9-1

Dynamic Logic Circuits

1. 2. 3. 4. 5.

Pass transistor circuits Voltage bootstrapping Synchronous dynamic circuit techniques Dynamic CMOS circuit techniques High-performance dynamic CMOS circuits

9-2

9.1 Introduction
Static v.s. Dynamic Static Logic Gates
Valid logic levels are steady-state operating points Outputs are generated in response to input voltage levels after a certain time delay, and it can preserve its output levels as long as there is power. All gate output nodes have a conducting path to VDD or GND, except when input changes are occurring.

Dynamic Logic Gates

The operation depends on temporary storage of charge in parasitic node capacitances. The stored charge does not remain indefinitely, so must be updated or refreshed. This requires establishment of an update or recharge path to the capacitance frequently enough to preserve valid voltage levels.
9-3

Static v.s. Dynamic (Continued)

Advantages of Dynamic Logic Gates Allow implementation of simple sequential circuits with memory functions. Use of common clock signals throughout the system enables the synchronization of various circuit blocks. Implementation of complex circuits requires a smaller silicon area than static circuits. Often consumes less dynamic power than static designs, due to smaller parasitic capacitances.

9-4

9.2 Basic Principles of Pass Transistor Circuits

Pass-Transistor Latch: Circuit and Operation
Soft note
D MP X Vx Cx ML Q MD Q

Operation

CK

CK = H, D=H or L : CX is charged up or down through MP, and X becomes H or L (depends on D input) since MP is on D and X are connected. CK = L: X is unchanged since MP is off and CX is isolated from D, and the charge is stored on capacitances CX. For X = H, Q = L and Q = H For X = L, Q = H and Q = L

Cost: 3 to 5 devices (very low)

9-5

Pass-Transistor Latch: Soft Node Concept

During CK = 1: Let D = 1, i.e. VD = VOH = VDD MP is conducting and charges CX to a weak 1 (VX = VDD VTD) Q = L (VQ<VTD) and Q = H(VQ=VDD). During CK = 0: Logic-level VX is preserved through charge storage on CX. However, VX starts to drop due to leakage. What value does VX have to deteriorate to no longer like a stored ? Example (see p359~359, Kang and Leblebici): For an inverter with VDD = 5V, VT,n = 0.8V , VOL = 2.9V and VIH = 2.9V, initial VX =4.2 V. But due to leakage currents, this will decline over time. When it declines below VIH(2.9V), then a logic 0 out of the inverter can no longer guaranteed. Thus, to avoid an erroneous output, the charge stored in CX must be restored or refreshed to its original level before VX declines below 2.9 V.
9-6

Logic 1 Transfer: VX(t=0)=0V, Vin=VOH=VDD, CK=0 VDD

Soft note Vin MP Vx X Cx

Basic Principles of Pass Transistor Circuits Logic 1 Transfer

Vin=VDD D

S MP

ID X

Vx Cx

Fig. 9.1

CK

CK

VGS = VDD - VX, VDS = VDD - VX = VGS. Therefore, VDS> VGS VT,MP MP is in saturation.
CX

Fig. 9.2

2 dVX = kn (V DD V X VT ,MP) 2 is subject to substrate bias effect and Note that the VT,MP dt

therefore, depends on the voltage level VX. We will neglect the substrate bias effect for simplicity.

9-7

Integrating the above equation with t from 0 t and VX from 0 VX, we have
2C dt = X kn 0
t VX

Basic Principles of Pass Transistor Circuits Logic 1 Transfer (Cont.)

(V
0

dVX 2 DD V X V T ,MP)
VX

Therefore,

1 = 2CX kn V DD V X VT ,MP 0

1 1 t = 2CX kn V V V V V DD X T , MP DD T , MP
and,
k n (V DD V T ,MP ) t 2C X V X (t ) = (V DD V T ,MP ) ( ) 1 + k n V DD V T ,MP t 2C X

9-8

Basic Principles of Pass Transistor Circuits Logic 1 Transfer (Cont.)

VX Vmax Vmax=VDD-VT,MP

0 approaches a limit value V VX rises from 0V and max = VX(t)|t= = VDD-VT,MP, but it can not exceed this value, since the pass transistor will turn off at this point (VGS=VT,MP). Therefore, it transfers a weak logic 1. The actual Vmax by taking the body effect into account is, V max = V DD V T 0,MP 2 F + V max 2 F and tcharge = time to VX = 0.9Vmax,

Fig. 9.3

t
9 - 9 Body

charge

1 1 2C X k n V DD 0.9V max V T ,MP V DD V T ,MP

Effect: Reduce VX, and Increase tcharge

9 - 10

9 - 11

Basic Principles of Pass Transistor Circuits: Logic 0 Transfer Logic 0 Transfer: VX(t=0)=Vmax= VDD VT,MP, Vin=VOL=0V, CK= 0 VDD
Soft note X Cx CK Vin MP Vx

Vin=0

S MP

ID X

Vx Cx

CK

VGS = VDD, VDS = Vmax = VDD VT,MP. Therefore, VDSVGS VT,MP MP is in linear region.

Fig. 9.6

CX

dVX kn [ ( = 2 V DD VT ,MP)V X V 2 X] dt 2

Note that the VSB=0. Hence, there is no body effect for MP (VT,MP= VT0,MP). But the initial condition VX(t=0)=VDD VT,MP contains the threshold voltage with body effect. To simplify the expressions, we will use VT,MP in the following.
9 - 12

Basic Principles of Pass Transistor Circuits Logic 0 Transfer (Cont.)

Integrating the above equation with t from 0 t and VX from VT,MP VX, we have
t VX

dt =
0

2CX dVX 2 [ ( 2 kn V DDV T ,MP V DD VT ,MP)V X V X ]

VX

2(V DD VT ,MP) V X CX = ln kn (V DD VT ,MP) VX V DDVT ,MP

Therefore,

t=

2 (V DD V T , MP ) V X CX ln k n (V DD V T , MP ) VX

and,

(t) =

2 (V 1+ e

tk n (V

DD

V
DD

T , MP
T , MP

)/ C X

9 - 13

Basic Principles of Pass Transistor Circuits Logic 0 Transfer (Cont.)

VX drops from Vmax = VDD-VT,MP, to 0V. Hence, unlike the charge-up case, it transfers a strong logic 0. fall = time of VX drops from 0.9Vmax to 0.1Vmax, fall = t90% t10%
CX [ln(19) ln(1.22)] = kn (V DD VT ,MP) CX = 2.74 kn (V DD VT ,MP)
VX Vmax Vmax=VDD-VT,MP

where,

(2 0.9 )(V DD V T ,MP ) CX ln t 90% = k n (V DD V T ,MP ) 0.9 (V DD V T , MP ) = t10% = CX ln (1.22 ) k n (V DD V T ,MP ) k n (V DD V T ,MP ) CX 1.9 ln 0.1

Fig. 9.7

9 - 14

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage
At t = 0, CK=0, VX= Vmax, Vin =0. The charge stored in CX will gradually leak away, primarily due to the leakage currents associated with the pass transistor. The gate current of the inverter driver transistor is negligible.
Vin =0 MP CK=0

Ileakage Vx

Igate=0
Cx

Fig. 9.8
Ileakage VX CX

VCK=0 Vin=0 n+ p-type Si

9 - 15

Isubthreshold Ireverse

n+

Fig. 9.9

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.)
VCK=0 Vin=0 n+
p-type Si

Ileakage VX n+ CX

Isubthreshold Ireverse Ileakage

Vx Cj(VX)

Ileakage= Isubthreshold + Ireverse

Cin= Cgb + Cpoly + Cmetal Cin CX= Cin + Cj

Isubthreshold

Ireverse

Drain-substrate pn-junction

Fig. 9.10

Isubthreshold is the subthreshold current for the pass transistor with CK=0. Ireverse is the reverse current for the source/drain pn junction at node X Cj (VX) : due to the reverse biased drain-substrate junction, a function of VX Cin: due to oxide-related parasitics, can be considered constants.
9 - 16

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.)
Ileakage Isubthreshold
Cj

Ileakage= Isubthreshold + Ireverse

Vx

Cin= Cgb + Cpoly + Cmetal

Ireverse

Cin CX= Cin + Cj

Drain-substrate pn-junction

The total charge stored in the soft node can be expressed as, Q = Qj (VX) + Qin where Qin = CinVX The total leakage current can be expressed as the time derivative of the total soft-node charge Q
I leakage = dQ dt dQ j (V X ) dQ in = + dt dt dQ j (V X ) dV X = + C in dV X dt dt dV X

9 - 17

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.)
Where
dQ j (V X ) dV X = C j (V X ) = AC j 0 AC j 0 SW + V 1+ X 1+ V X

0 SW

0 =

kT ND N A ln q ni2

0SW =

kT ND N ASW ln q ni2

Therefore,

AC j 0 PC j 0 SW + + C in dV X I leakage = dt V V 1+ X 1+ X 0 0 SW

We have to solve the above differential equation to estimate the actual charge leakage time from the soft node.
9 - 18

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.) A quick estimate of the worst-case leakage behavior
Assume that the minimum combined soft-node capacitance is CX,min = Cgb + Cpoly + Cmental + Cdb,min Cdb,min is the minimum junction capacitance, obtained when VX=Vmax The worst-case holding time (thold) is the shortest time for VX to drop from its initial logic-high value to the logic threshold voltage due to leakage. thold = Qcritical,min/Ileakage,max where Vth
Qcritical,min =CX,min (Vmax-VDD/2)

9 - 19

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.)
Example 9.2: Consider the soft-node structure shown below, which consists of the drain (or source, depending on current direction) terminal of the pass transistor, connected to the polysilicon gate of an nMOS driver transistor via a metal interconnect. Question: is to estimate thold if VDD=5V and the soft-node is initially charged to Vmax.
MP CK 3 1 MP 4 1 CK
diffusion

Vx Cx

M1 soft node 6 5 5 2 3
metal polysilicon

6 2 M1 4 1 2

9 - 20

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.)
Material parameters: VTO = 0.8V = 0.4V1/2 |2F| = 0.6V 0 = 0.88V 0SW = 0.95V Ileakage,max = 0.85 pA COX = 0.065 fF/m2 Cmetal = 0.036 fF/ m2 Cpoly = 0.055 fF/ m2 Cj0 = 0.095 fF/ m2 Cj0SW = 0.2 fF/m
3 1 MP 4 1 CK 6 5 5 6 2 M1 4 1 2

Soft-node Capacitance Calculation

2 diffusion metalpolysilicon 3

Oxide-related (constant) parasitic capacitances Cgb = COXWLmask = 0.065 fF/m2 (4 m2 m) = 0.52 fF Cmetal = CmetalWLmetal = 0.036 fF/m2 (5 m5 m) = 0.90 fF Cploy = CpolyWLpoly = 0.055 fF/m2 (36+6+2 m2) = 2.42 fF
9 - 21

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.)
Parasitic junction capacitance By zero-bias unit capacitance values in the previous slide, we have Cbottom = AbottomCj0 = 0.095 fF/m2 (36 m2 + 12 m2 ) = 4.56 fF Csidewall = Cj0SWPsidewall = 0.2 fF/m2 (30 m) = 6.00 fF Therefore Cdb,max = Cbottom + Csidewall = 4.56 fF + 6.00 fF = 10.56 fF The minimum drain junction capacitance is achieved as the junction is biased with Vmax. We need to find Vmax to determine Cdb,min Vmax = 5.0 - 8.0 - 0.4 ( 0.6+ Vmax - 0.6 ) C bottom C sidewall + C db,min = Vmax = 3.68 V V 1 + X ,max 1 + V X ,max 0 0 SW Therefore,
= 4.56 6.0 + = 4.71 fF 3.68 3.68 1+ 1+ 0.88 0.95

9 - 22

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.)
Combining the Oxide-related (constant) parasitic capacitances with the parasitic junction capacitance, CX,min can be got as CX,min = Cgb + Cpoly + Cmental + Cdb,min = 0.52 + 2.42 + 0.90 +4.71 = 8.55 fF The amount of the critical charge drop is Qcritical = CX,min(VX,min-VDD/2)=8.55 (3.682.5)=10.09 fC Finally, thold = Qcritical /Ileakage,max=11.87ms The worst-case hold time for this structure is relatively long, even with a very small soft-node capacitance of 8.55fF. It means that the logic gate can be preserved in a soft node for a long time period when the leakage current is small.

9 - 23

9.3 Voltage Bootstrapping

The Voltage bootstrapping is a technique to overcome the threshold voltage drops of the output voltage levels in pass transistor gates or enhancement-load inverters and logic gates. Consider the following circuit with VXVDD M2 is in saturation. If Vin is low, the maximum output voltage is limited as Vout(max) = VX VT2(Vout)
VDD Vx M2 Vout Vin M1 Cout

Fig. 9.11
9 - 24

Voltage Bootstrapping (Cont.)

To overcome the voltage drop, the voltage VX must be increased. This can be achieved by adding a third transistor M3 into the circuit. CS and Cboot represent the capacitances which dynamically couple VX to the ground and to the output. The goal of the above circuit is to provide a high enough voltage VX to let Vout go to VDD instead of VDD-VT2(Vout).
VDD M3 Vx CS Vin M2 Cboot Vout M1 Cout

Fig. 9.12

Initially, let Vin=H M1 and M2 are on, and Vout=L. Now Vin goes to L M1 turns off, and Vout starts to rise. This change will be coupled to VX through the bootstrap capacitor, Cboot.
9 - 25

Voltage Bootstrapping (Cont.)

Let iCboot be the transient current through Cboot during the charge-up event, and let iCS be the current through CS. Assume iCS iCboot, we have iCS iCboot CSdVX/dt Cbootd(Vout-VX)/dt (CS+Cboot)dVX/dt CbootdVout/dt dVX/dt Cboot /(CS+Cboot) dVout/dt This expression can be integrated to give VX such that Vout will rise to VDD.

X DD

V T 3

dV

C boot C S + C boot
DD

DD OL

dV

out

= (V

V T 3) +

If Cboot >> CS, then for Vout rising to VDD, VX(max) 2VDD VT3 VOL > VDD VT2. for realistic values of the voltages. Thus, it is feasible to use the circuit to obtain Vout =VDD.

C boot (V C S + C boot

DD

V OL )

9 - 26

Voltage Bootstrapping (Cont.)

To overcome the threshold voltage drop at Vout, the minimum VX is VX(min) = VDD + VT2|Vout = VDD = [VDD-VT3(VX)]+Cboot /(CS+Cboot) (VDD-VOL) Therefore, the required capacitance ratio Cboot /(CS+Cboot) is

VT 2 Vout=VDD +VT 3 VX Cboot = CS + Cboot V DD VOL . VT 2 Vout=VDD +VT 3 VX Cboot = CS V DD VOL VT 2 Vout=VDD VT 3 VX

CS is the sum of the parasitic source-to-substrate capacitance of M3 and the gate-to-substrate capacitance of M2.
9 - 27

Voltage Bootstrapping (Cont.)

Cboot can be specifically constructed to control its value by using a transistor with the source and drain connected together at Vout and the gate attached to VX. Since its drain and source tied together, it simply acts as an MOS capacitor between VX and Vout. VDD
M3 Vx M2

Cboot Vout Vin M1

Fig. 9.13

See Kang and Leblebici at pp. 373 for a SPICE example.

9 - 28

9.4 Synchronous Dynamic Circuit Techniques

Dynamic Pass Transistor Circuits
The multi-stage synchronous circuit is shown below. The circuit consists of cascaded combinational logic stages interconnected through nMOS pass transistors. Its operation depends on temporary charge storage in the parasitic input capacitances.
A B Comb. Logic 1 Comb. Logic 2 Comb. Logic 3 F1 F2

1 1 2

1
t

Fig. 9.14

phase1

phase2

Fig. 9.15

1,2 non-overlapping clocks

Logic levels are stored on input capacitances during the inactive 9 - 29 clock phase.

Dynamic Pass Transistor Circuits Two-Phase Clock Dynamic Shift Register

Depletion-Load Dynamic Shift Register The max clock frequency is determined by signal propagation delay through one inverter stage. One half-period of the clock signal must be long enough to allow Cin to charge up or down, and Cout to charge to the new value. The logic-high input value is one VT0 lower than VDD.
VDD VDD VDD

Vout

Vin

Cin1

Cout1

Cin2

Cout2

Cin3

Cout3

Fig. 9.16
9 - 30

9 - 31

9 - 32

Dynamic Pass Transistor Circuits Enhancement-Load Dynamic Shift Register

Enhancement-Load Dynamic Shift Register 1

Instead of biasing load transistors with a constant gate voltage, a clock signal is applied to the gate of the load transistor power dissipation and silicon area are reduced. The power supply current flows only when the load devices are activated by the clock signal, the power consumption is lower than the depletion-load nMOS logic.
1
VDD

VDD

VDD

2
Vout

Vin

Cin1

Cout1

Cin2

Cout2

Cin3

Cout3

Fig. 9.19
9 - 33

Enhancement-Load Dynamic Shift Register 1 (Cont.) General Structure

VDD VDD

1
A B C nMOS Logic Stage 1 nMOS Logic Stage 2

1
Z

Fig. 9.20
General Circuit Structure of Ratioed Synchronous Dynamic Circuit

9 - 34

9 - 35

Enhancement-Load Dynamic Shift Register 1 (Cont.)

1=H 1
VDD

2
Vout1

VDD

1
Vout2

VDD

2
Vout3 Cin3 VDD Cout3

Vin

Cin1 VDD

Cout1

Cin2

Cout2 Vout2VOL VDD Vout2

2=H

2
Vout1

2
Vout3 Cin3 Vout3VOL Cout3

Vin

Cin1

Cout1 Vout1VOL

Cin2

Cout2

VOL kdriver/kload Ratioed Dynamic Logic. Cout1, Cin2 & Cout2, Cin3 interact Charge Sharing
9 - 36

Enhancement-Load Dynamic Shift Register 2

Enhancement-Load Dynamic Shift Register 2 The input pass transistor and the load transistor are driven by the same clock phase. The valid low-output voltage level VOL=0V can be achieved regardless of the driver-to-load ratio, this circuit is a ratioless dynamic logic.
1
VDD

VDD

VDD

Vout Vin Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

9 - 37

Fig. 9.21

Enhancement-Load Dynamic Shift Register 2(Cont.) General Structure

1
VDD VDD

2
Z

A B C nMOS Logic Stage 1 nMOS Logic Stage 2

Fig. 9.22
General Circuit Structure of Ratioless Synchronous Dynamic Circuit

9 - 38

Enhancement-Load Dynamic Shift Register 2 (Cont.)

1=H 1
VOH Cin1 Cout1 Vout1VOL VDD Vout1 Vin VOH Cin2 Cout2 Vout2 0V VDD Vout2 VOH0 Cout1 Vout10V Cin2 Cout2 Vout2VOH 0 Cin3

VDD

1
Vout2 0

VDD

Vout3 Cout3 Vout3VOH

Cin3

2=H

VDD Vout1

VDD

Vin

VOH Cin1

Vout3 Cout3 Vout3=VOH

VOL 0V Ratioless Dynamic Logic.

9 - 39

Enhancement-Load Dynamic Shift Register 2 (Cont.)

1=H
VDD Vout1 VOH Vin VOH Cin1 Cout1 Vout1=0V 0V Cin2 Cout2 Vout2= VOH

VDD

1
Vout2 0

VDD

Vout3 Cin3 Cout3 Vout3=?

Charge Sharing Cini << Couti-1 for i=2,3 Minimum Charge Sharing

9 - 40

Enhancement-Load Dynamic Shift Register 2 (Cont.) Charge Sharing

2=1 2=1
Va Cout2 Cin3

Vb=VOH
Vi1=0 Cin1

Vb=VOL 0
Vin1=1 Cin1 Cout1

Va Cin2

Charge Sharing

2 = 0: Qout2 = Cout2Vb and Qin3 = Cin3Va 2 = 1: Qtotal = Cout2Vb + Cin3Va and Ctotal = Cout2 + Cin3 The resulting voltage across Ctotal is VR = Qtotal / Ctotal = (Cout2Vb + Cin3Va )/ (Cout2 + Cin3) If Vb = VOH and Va << Vb VR Cout2VOH /(Cout2 + Cin3) VR VOH if Cin3 << Cout2
9 - 41

9.5 Dynamic CMOS Circuit Techniques CMOS Transmission Gate Logic

Each transmission gate is controlled by the clock signal and its complement. Therefore, the two-phase clocking need four clock signals. As in the nMOS structures, the CMOS dynamic circuit relies on charge storage in parasitic input capacitances during the inactive clock cycles.
1 2 1

A B C
9 - 42

F1 Stage 1 D
1 2

Stage 2
1

Fig. 9.23

Dynamic CMOS Transmission Gate Logic Shift Register

The basic building block of the shift register consists of a CMOS inverter, which is driven by a TG. CK=1Vin is transferred onto the parasitic input capacitance CX. The low on-resistance of TG results in A smaller transfer time compared to nMOS-only switches. No threshold voltage drop across TG soft node
CK

VDD

Vin
CK 9 - 43

VX CX

Vout Cy Fig. 9.24

The single-phase CMOS shift register is built by Cascading identical inverter units Driving each stage alternately with the CK and CK. Ideally: The odd-numbered stages are on as CK=1, while the evennumbered stages are off the cascaded inverter stages are alternately isolated. Practically: The CK and CK are not a truly nonoverlapping signal pair, since their waveforms have finite rise and fall times. One of the signals is generated by inverting the other the clock skew is unavoidable. True two-phase clocking is preferred over single-phase clocking.
CK CK CK

Dynamic CMOS Transmission Gate Logic Shift Register (Cont.)

V1
CK

V2
CK

V3
CK

V4

9 - 44

Fig. 9.225

Dynamic CMOS Precharge-Evaluate Logic Reduced Transistor Count VDD

Mp Vout C inputs nMOS Logic

Internal capacitance

Me

=0 Mp on and Me off C precharges to VDD (output is not available during precharge) =1 Mp off and Me on C selectively discharges to 0 (output is only available after discharge is complete)

precharge

evaluate precharge t t

Vout

9 - 45

Dynamic CMOS Precharge-Evaluate Logic An Example VDD

Mp Vout

A1 B1 A2 B2 A3

Me

Z is high when =0 Z=(A1 A2A3 +B1B2)

9 - 46

Fig. 9.26

Advantages

Dynamic CMOS Precharge-Evaluate Logic Advantages/Disadvantages

Need only N+2 transistors to implement a N-input gate. Low static power dissipation No DC current paths to place constraints on device sizing Input capacitance is same as pseudo nMOS gate. Pull-up time is improved by active switch to VDD.

Disadvantages
The available time of output is less than 50 % of the time. Pull-down time is degraded due to series active switch to 0. Logic output value can be degraded due to charge sharing with other gate capacitances connected to the output. Minimum clock rate determined by leakage on C. Maximum clock rate determined by circuit delays. Input can only change during the precharge phase. Inputs must be stable during evaluation; otherwise an incorrect value on an input could erroneously discharge the output node. (single phase P-E logic gates can not be cascaded) Outputs must be stored during precharge, if they are required during the next evaluate phase.
9 - 47

Dynamic CMOS Precharge-Evaluate Logic Cascading Problem

VDD VDD

Mp1 Vout1 1st stage nMOS Logic Me1

Mp2

Vout2

precharge evaluate t Vout1 does not switch from 1 to 0 fast enough t correct state erroneous state t

2nd 1 Me2

inputs

Vout Vout

Evaluate: Me1, Me2 ON Mp1, Me2 OFF Problem: All stages must evaluate simultaneously one clock does not permit pipelining of stages.
9 - 48

9.6 High Performance Dynamic CMOS Circuits Domino CMOS Logic

VDD VDD

Static inverter serves to buffer the logic part of the circuit from its output load
Vout

X nMOS Logic

inputs

precharge evaluate
1 t 9 - 49

=0 X precharges to VDD, and Vout = 0. =1 X remains high, and Vout remains low. X discharges to 0, and Vout changes from 0 to 1. Fig. 9.27

9 - 50

9 - 51

9 - 52

9 - 53

VDD

Domino CMOS Logic

VDD X1 X2 nMOS Logic

VDD

X3 nMOS Logic

inputs

nMOS Logic

X1 X2 X3

evaluate
precharge

evaluate teval t t t t

Max number gates limited: total propagation delay < teval

9 - 54

Domino CMOS Logic (Cont.)

VDD VDD X1 inputs nMOS Logic nMOS Logic X2 nMOS Logic VDD X3

The problem in cascading conventional dynamic CMOS occurs when one or more inputs make a 1 to 0 transition during evaluation. Domino circuits can fix the above problem During the evaluation, each buffer output can make at most one transition (from 0 to 1), and thus each input of all subsequent logic stages can also make at most one (0 to 1) 9 - 55 transition.

Domino CMOS Logic The Limitations

The static CMOS and domino gates can be used together, see Fig. 9.31. in Kang and Leblebici. The limitation: the number of inverting static logic stages in cascade must be even, to let the inputs of next domino stage can have only 0 to 1 transitions during the evaluation. Can implement only non-inverting logic Due to precharge use, can suffer from charge sharing during the evaluation which may cause erroneous outputs. The problem will be described in the next slide, and several solutions will be presented later.

9 - 56

Domino CMOS Logic Charge Sharing

VDD VDD VX N C2 0V(initially) C1

Vout

VX = VDDC1/(C1+C2) Keep C2 << C1 Fig. 9.32

Assume that all inputs are low initially, and the voltage across C2=0V During the precharge, C1 is charged to VDD If transistor N switches from 0 to 1 during the evaluation phase, the charge initially stored in C1 will be shared by C2. Therefore, the value of VX will reduced.
9 - 57

Domino CMOS Logic Reduce Charge Sharing Degradation of VX

VDD

weak pull-up pMOS

Vout

VX nMOS Logic

inputs

Push VX to VDD unless there is a strong pull-down path between Vout and ground

Fig. 9.33
9 - 58

Domino CMOS Logic Reduce Charge Sharing Degradation of VX (Cont.)

VDD

VX1 nMOS Logic VX2 nMOS Logic C2 C1

Use separate pMOS transistors to precharge all intermediate nodes Vout1 in nMOS pull-down tree which have a large parasitic capacitance. Effectively eliminate all charge sharing problems during evaluation Vout2 Allow implementation of multipleoutput domino structures. Can cause additional delay since the nMOS tree need to drain a larger charge to pull down VX

9 - 59

Another Way: Use a smaller threshold voltage the final stage output is not affected by lowering of VX trade off the pull-up speed (weaker pMOS transistor) Fig. 9.34

Domino CMOS Logic An Example of Using Separate pMOS Transistor

VDD VDD VX1 VA VB VX2 C2 C1 VDD Vout

9 - 60

Let C1 = C2 = 0.05pF. VX1 = 0, and VX2 = 0 at t=0 Without this extra pMOS transistor Precharge: VX1 VX2 Evaluation: VX1 = VDDC1/(C1+C2) = VDD/2 With this extra pMOS transistor Presharge: VX1 = VX2 Evaluation: VX1 = VDD See pp.392~393 for the HSPICE simulation result Note that there is a speed penalty for adding this extra pMOS precharge transistor.

Domino CMOS Logic An Example of Multiple-Output Domino Circuits

VDD

C4 P4 P3 P2 P1 C0 G1 G2 G3 G4 C3 C2 C1

Reduce transistor count C1=G1+P1C0 C2=G2+P2G1+P2P1C0 C3=G3+P3G2+P3P2G1+P3P2P1C0 C4=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1C0

9 - 61

Gi = Ai Bi Pi = Ai Bi
Fig. 9.35

FET Scaling in Domino CMOS Gates

The transient performance can be improved by adjusting the nMOS transistor sizes in the pull-down path to reduce the discharge time.
VDD

A B C D

Mp Vout

CL

R0
Me

0 C0

R1 1 C1 CL

9 - 62

Fig. 9.36

The nMOS Scaling in Domino CMOS Gates

V1=V0=VDDVDD after time T1 C0 C1 CL T1 =R0(C0+C1+CL)+R1(C1+CL) Let the last nMOS is increased by a fraction of k then C1 C1(1+k); R1 R1/(1+k) T1 =R0(C0+C1+CL)+R1(C1+CL)+(C1-R1CL/R0)k If CL<(R0/R1)C1 T1 decreases by decreasing the size of the last nMOS. R0/R1 is the number of series-connected nMOS minus one, times a factor that takes the many effects that makes a real nMOS different from a linear resistor, into account. Using the approximation =1/2, we conclude If CL<C1(N-1)/2 is satisfied, the overall delay can be reduced by decreasing the size of last nMOS. The above result can be iteratively applied to the other transistors, which leads to graded sizing of all nMOS devices. e-1
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R0

R1 1

NORA CMOS Logic (NP-Domino Logic)

VDD VDD VDD

nMOS Logic

pMOS Logic

nMOS Logic

to nMOS stage to pMOS stage nMOS stage all stages all stages nMOS stage precharge evaluate evaluate precharge pMOS stage pMOS stage pre-discharge pre-discharge

Advantages

Fig. 9.37

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An Inverter is not required at the output of stages Allow pipelined system architecture Disadvantages: Also suffer from charge sharing and leakage

NORA CMOS Logic (NP-Domino Logic) Examples

VDD VDD VDD

Fig. 9.38

=L: nMOS precharges to H, and pMOS predischarges to L. =LH: All cascaded nMOS and pMOS logic stages evaluate one after the other.
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NORA CMOS Logic (NP-Domino Logic) Examples (Cont.) Pipelined System Architecture: See Fig. 9.39 Use of CMOS2 latches (three state latches storing on logic inputs.) Zipper Logic: See Fig. 9.40 Identical to NORA except for weird clock signals that keep precharge devices weakly on to handle charge leakage and charge sharing

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Pipelined True Single-Phase Clock (TSPC) Dynamic CMOS

VDD VDD VDD VDD

nMOS Logic

pMOS Logic

to next N-block

N-block

P-block

Fig. 9.41

Using tristate inverters between stages decouples the stages and enables pipelined operation

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=L: nMOS blocks precharge to VDD pMOS blocks evaluate by selective pull-up to VDD =H: pMOS blocks pre-discharge to VDD nMOS blocks evaluate by selective pull-down to 0V is not used, no clock skew problem can arise. Provide similar performance to NORA structure

TSPC-Based Rising Edge-triggered D-type Flip-Flop

VDD VDD VDD VDD

Fig. 9.42

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Need only 11 transistors. Static Edge Triggered D Flip-flop (see Fig. 8.30) need 16 transistors. Common Advantages of dynamic Logic Styles Smaller area than fully static gates. higher speed: smaller parasitic capacitances. Glitch free operation if design carefully

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Summary
Full complementary static logic is best option in the majority of CMOS circuits. Noise-immunity is not sensitive to kn/kp Does not involve precharge of nodes Dissipate no DC power Layout can be automated Large fan-in gates lead to complex circuit structures (2N transistors) Larger parasitics Slower and higher dynamic power dissipation than alternatives No clock

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Summary (Cont.) Pseudo-nMOS static logic finds widest utility in large fan-in NOR gates. Require only N+1 transistors for N fan-in Smaller parasitics Faster and lower dynamic power dissipation than full CMOS Noise immunity sensitive to kn/kp Dissipate DC power when pulled down Not well suited for automated layout No clock
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Summary (Cont.)
CMOS domino logic should be used for low-power, high speed applications Require only N+k transistors for N fan-in, size advantages of pseudo-nMOS. Dissipate no DC power Noise immunity is not sensitive to kn/kp Use of clocks enables synchronous operation Rely on storage on soft node Require exhaustive simulation at all the process corners to insure proper operation Some of the speed advantage over static gates is diminished by the required per-charge (predischarge) time.
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