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    Orcad / Pspice Simulator - 7400 Library - 7408, 7432 & 7486 Simulation Settings: Analysis Type - Time Domain

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    santhoshi
    This document describes the design and simulation of half adder and full adder circuits. It explains the procedures to implement the circuits using OR, AND, and XOR logic gates in a PSpice simulator. Truth tables are provided for half adder and full adder. The circuits are simulated and the output waveforms are shown to match the manual truth tables, verifying the implementation of sum and carry functions for both half adder and full adder.

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    Orcad / Pspice Simulator - 7400 Library - 7408, 7432 & 7486 Simulation Settings: Analysis Type - Time Domain

    Uploaded by

    santhoshi
    364 views6 pages
    This document describes the design and simulation of half adder and full adder circuits. It explains the procedures to implement the circuits using OR, AND, and XOR logic gates in a PSpice simulator. Truth tables are provided for half adder and full adder. The circuits are simulated and the output waveforms are shown to match the manual truth tables, verifying the implementation of sum and carry functions for both half adder and full adder.

    Original Description:

    eee lab assessent on half adder and full adder

    Original Title

    19MIC0065

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    This document describes the design and simulation of half adder and full adder circuits. It explains the procedures to implement the circuits using OR, AND, and XOR logic gates in a PSpice simulator. Truth tables are provided for half adder and full adder. The circuits are simulated and the output waveforms are shown to match the manual truth tables, verifying the implementation of sum and carry functions for both half adder and full adder.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    364 views6 pages

    Orcad / Pspice Simulator - 7400 Library - 7408, 7432 & 7486 Simulation Settings: Analysis Type - Time Domain

    Uploaded by

    santhoshi
    This document describes the design and simulation of half adder and full adder circuits. It explains the procedures to implement the circuits using OR, AND, and XOR logic gates in a PSpice simulator. Truth tables are provided for half adder and full adder. The circuits are simulated and the output waveforms are shown to match the manual truth tables, verifying the implementation of sum and carry functions for both half adder and full adder.

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    You are on page 1of 6

    Ex. No.

    : 6 Date:
    Design of Half Adder and Full Adder Circuits

    Aim: To implement and simulate the Half Adder and Full Adder circuits.

    Apparatus/Tool required:
    ORCAD / PSpice simulator - > 7400 Library – 7408, 7432 & 7486
    Source Library - Digclock
    Simulation Settings: Analysis Type - Time Domain
    Run to time: 4ms (for Half Adder)
    Run to time: 8ms (for Full Adder)
    Circuit Diagram:

    Half – Adder Circuit

    OFFTIME = 2mSDSTM1 U1A


    ONTIME = 2mS CLK
    DELAY =
    1
    3 S = A B
    STARTVAL = 0 2
    OPPVAL = 1
    7486
    OFFTIME = 1mSDSTM2
    ONTIME = 1mS CLK
    DELAY =
    STARTVAL = 0
    OPPVAL = 1
    U2A
    1
    3 C = A .B
    2

    7408

    Full – Adder Circuit

    OFFTIME = 4mSDSTM3 U3A


    U4A
    ONTIME = 4mS CLK
    DELAY =
    1
    3 1 S = AB C
    STARTVAL = 0 2 3
    OPPVAL = 1 2
    7486
    OFFTIME = 2mSDSTM4 7486
    ONTIME = 2mS CLK
    DELAY =
    STARTVAL = 0
    OPPVAL = 1 U6A
    1
    OFFTIME = 1mSDSTM5
    ONTIME = 1mS CLK 2
    3
    C = (A  B).C + A·B
    DELAY = U7A
    STARTVAL = 0 7408 1
    OPPVAL = 1 3
    U5A 2
    1
    3 7432
    2

    7408
    Theory:

    Half Adder Circuit:

    Circuit Diagram:-
    OFFTIME = 2mSDSTM1 U1A
    ONTIME = 2mS CLK
    DELAY =
    1
    3 S = A B
    STARTVAL = 0 2
    OPPVAL = 1
    7486
    OFFTIME = 1mSDSTM2
    ONTIME = 1mS CLK
    DELAY =
    STARTVAL = 0
    OPPVAL = 1
    U2A
    1
    3 C = A .B
    2

    7408

    Truth Table:-

    A B S=AB C=A.B

    0 0 0 0
    0 1 1 0
    1 0 1 0
    1 1 0 1

    Model Timing Diagram:

    Half – Adder

    1
    Full Adder Circuit:-

    Circuit Diagram:-

    OFFTIME = 4mSDSTM3 U3A


    U4A
    ONTIME = 4mS CLK
    DELAY =
    1
    3 1 S = A  B C
    STARTVAL = 0 2 3
    OPPVAL = 1 2
    7486
    OFFTIME = 2mSDSTM4 7486
    ONTIME = 2mS CLK
    DELAY =
    STARTVAL = 0
    OPPVAL = 1 U6A
    1
    OFFTIME = 1mSDSTM5
    ONTIME = 1mS CLK 2
    3
    C = (A  B).C
    DELAY = U7A
    STARTVAL = 0 7408 1
    OPPVAL = 1 3
    U5A 2
    1
    3 7432
    2

    7408

    Truth Table:-

    A B C S=ABC C= (AB).C+A.B

    0 0 0 0 0
    0 0 1 1 0
    0 1 0 1 0
    0 1 1 0 1
    1 0 0 1 0
    1 0 1 0 1
    1 1 0 0 1
    1 1 1 1 1

    Model Timing Diagram:

    Full – Adder

    2
    Simulation Circuit Diagram and Output (Both Waveform and Truth Table):

    1)Half-Addder:-

    3
    2)Full-Adder:-

    4
    Procedure:
    1) First create a Orcad Pspice project.
    2) Next create Half-Adder and Full-Adder using eval library and digiclock
    source.
    3)Create the Half-Adder and The Full-Adder using the logic gates:-
    OR(7432),AND(7408) and XOR(7486)
    4)For Half-Adder the on and off times of the 2 Digiclocks are 1us and 2 us
    Respectively.
    5)For Full-Adder the on and off times of the 3 digiclocks are 1us,2us and 4 us
    respectively.
    6) Create the schematic diagram with time domain analysis with 2us runtime
    for Half-Adder and 4us runtime for the Full-Adder.
    7) By seeing the waveforms of those circuits by using the toggle cursor we can
    conclude
    With the manual tables and they are equal.
    8)For Half-Adder:- a) S=AB (Sum)
    b) C=A.B (Carry)
    9)For Full-Adder:-a) S=ABC (Sum)
    b) C= (AB).C+A.B (Carry)

    Result:

    For Half-Adder:- a) S=AB (Sum)


    b) C=A.B (Carry)

    For Full-Adder:-a) S=ABC (Sum)


    b) C= (AB).C+A.B (Carry)

    Inference: We have implemented and simulated the Half-adder and Full-adder


    using the logic gates and verified the manual truth table with the toggle cursor
    Truth table.

    Reg. No: 19MIC0065 Name: S. SHAHATHAJ Date:

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