Vizio Jv50p Hdtv10a Plasma TV SM

Service Manual
Model #: VIZIO JV50P HDTV10A
V, Inc 320A Kalmus Drive Costa Mesa, CA 92626 TEL : +714-668-0588 FAX :+714-668-9099
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Confidential
Table of Contents
CONTENTS Sections 1. Features 2. Specifications 3. On Screen Display 4. Factory Preset Timings 5. Pin Assignment 6. Main Board I/O Connections 7. Theory of Circuit Operation 8. Waveforms 9. Trouble Shooting 10. Block Diagram 11. Spare parts list 12. Complete Parts List 1-1 2-1 3-1 4-1 5-1 6-1 7-1 8-1 9-1 10-1 11-1 12-1 PAGE
Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3. Assembly Explosion Drawing Block Diagram
VIZIO JV50P HDTV10A Service Manual
VINC
COPYRIGHT 2000 V, INC. ALL RIGHTS RESERVED.
Service Manual
VIZIO JV50P HDTV10A
IBM and IBM products are registered trademarks of International Business Machines Corporation. Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc. VINC and VINC products are registered trademarks of V, Inc. VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards Association (VESA). Energy Star is a registered trademark of the US Environmental Protection Agency (EPA). No part of this document may be copied, reproduced or transmitted by any means for any purpose without prior written permission from VINC. FCC INFORMATION This equipment has been tested and found to comply with the limits of a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy, and if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that the interference will not occur in a particular installation. If this equipment does cause unacceptable interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures -- reorient or relocate the receiving antenna; increase the separation between equipment and receiver; or connect the into an outlet on a circuit different from that to which the receiver is connected. FCC WARNING To assure continued FCC compliance, the user must use a grounded power supply cord and the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized changes or modifications to Amtrak products will void the users authority to operate this device. Thus VINC Will not be held responsible for the product and its safety. CE CERTIFICATION This device complies with the requirements of the EEC directive 89/336/EEC with regard to Electromagnetic compatibility. SAFETY CAUTION Use a power cable that is properly grounded. Always use the AC cords as follows USA (UL); Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric Appliance Control Act); or an AC cord that meets the local safety standards.
VIZIO JV50P HDTV10A Service Manual
Chapter 1
Features
1. Built in TV channel selector for TV viewing 2. Simulatnueous display of PC and TV images 3. Connectable to PCs analog RGB port 4. Built in HDTV, composite video, HDMI ,ATV out and DTV out , Audio AUX IN 5. Built in auto adjust function for automatic adjument of screen display 6. Smoothing function enables display of smooth texts and graphics even if image with resolution lower than 1366x768 is magnified 7. Picture In Picture (PIP) function to show TV or VCR/DVD images 8. Power saving to reduce consumption power too less than 3W 9. On Screen Display: user can define display mode (i.e. color, brightness, contrast, sharpness, backlight), sound setting, PIP, TV channel program, aspect and gamma or reset all setting. 10. RF Modulation: Direct Sequence Spreading Spectrum (DSSS) 11. TX/RX distance: 10Meters (indoor with free space) min. 12. RX channel: 4 channels in 5.8GHz ISM band with auto scan and synchronization functions. 13. Support 16bit, 32/44.1/48KHz digital audio transmission and receiving. 14. User unique ID pairing function. 15. RF channel Carrier Frequency: Channel No. Center Frequency 1 5745MHz 2 5765MHz 3 5785MHz 4 5805MHz
CONFIDENTIAL DO NOT COPY
Page 1-1 File No. SG-0228
Chapter 2
Specification
1. PDP CHARACTERISTICS PDP50X4 (50WXGA PDP MODULE)

Item Active Screen Size Outline Dimension Display Area Pixel Pitch Cell Pitch Pixel Format Number of Gradations Peak Brightness Contrast Ratio 50 inch diagonal 1190(H) 700(V) 58(D) 1mm 1106.5(H) 622.1(V) 0.5mm 810 (H) 810 (V) 270 (H) 810 (V) (Green Cell basis) 1366(H) 768(V) (1pixel=3 RGB cells) (R)1,024 (G)1,024 (B)1,024 colors Typical 1,500cd/ (1/100 White Window pattern at center) Average 130:1 (In a bright room with 100Lux at center) Typical 15,000:1 (In a dark room 1/100 White Window pattern at center) Viewing Angle(L/R/U/D) Free Power Consumption Weight Max. 400 W (Full-White) 20.40.5 Kg (Net 1EA) Specification
2.Input Connectors RJ11, D-SUB15PIN (MINI, 3rows), HDMIX3, RCAX2 (component), RCAX2 (AUDIO in), RCAX2 (composite), RCAX2 (AUDIO in), Tuner, SPDIF IN(Optical Audio) 3.Output Connectors Stereo RCA Jack (Analog audio out) , SPDIF Out (Optical Audio) 4. POWER SUPPLY Power Consumption: 550W MAX Power OFF: to less than 3W MAX
SUBWOOFER POWER SUPPLY
Power Consumption: 70W MAX Sleep mode(or TV off): to less than 3W MAX
5.Speaker Output 10W (max) X3 Wireless Speaker : (1) Rear Right 10W(max) (2) Rear Left 10W(max) (3) Subwoofer 20W(max) 6. ENVIRONMENT 7-1. Operating Temperature: 5c~35c (Ambient) 7-2. Operating Humidity: Ta= 35 C, 90%RH (Non-condensing) 7-3. Operating Altitude: 0 - 14,000 feet (Non-Operating) 7. DIMENSIONS (Physical dimension) Width: 1241.0mm Height: 856.3mm Depth: 291.2mm 8. WEIGHT (Physical weight)
a. TV net 52.6kg b. Spk net 8.0kg c. TV and spk gross 72.0kg
9.Please pay attention to the followings when you use this PDP module. 9-1. MOUNTING PRECAUTIONS (1) You must mount a module using holes arranged in four corners or four sides. (2) You should consider the mounting structure so that uneven force (ex. Twisted stress) is not applied to the module. And the case on which a module is mounted should have sufficient strength so that external force is not transmitted directly to the module. (3) Please attach the surface transparent protective plate to the surface in order to protect the polarizer. Transparent protective plate should have sufficient strength in order to the resist external force. (4) You should adopt radiation structure to satisfy the temperature specification.
(5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former generates corrosive gas of attacking the polarizer at high temperature and the latter causes circuit break by electro-chemical reaction. (6) Do not touch, push or rub the exposed polarizes with glass, tweezers or anything harder than HB pencil lead. And please do not rub with dust clothes with chemical treatment. Do not touch the surface of polarizer for bare hand or greasy cloth.(Some cosmetics are detrimental to the polarizer.) (7) When the surface becomes dusty, please wipe gently with absorbent cotton or other soft materials like chamois soaks with petroleum benzene. Normal-hexane is recommended for cleaning the adhesives used to attach front / rear polarizers. Do not use acetone, toluene and alcohol because they cause chemical damage to the polarizer. (8) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer causes deformations and color fading. (9) Do not open the case because inside circuits do not have sufficient strength. 9-2. OPERATING PRECAUTIONS (1) The spike noise causes the mis-operation of circuits. It should be lower than following voltage : V=200mV(Over and under shoot voltage) (2) Response time depends on the temperature. (In lower temperature, it becomes longer.) (3) Be careful for condensation at sudden temperature change. Condensation makes damage to polarizer or electrical contacted parts. And after fading condensation, smear or spot will occur. (4) When fixed patterns are displayed for a long time, remnant image is likely to occur. (5) Module has high frequency circuits. System manufacturers shall do sufficient suppression to the electromagnetic interference. Grounding and shielding methods may be important to minimize the interference.
9-3. HANDLING PRECAUTIONS FOR PROTECTION (1) The protection film is attached to the bezel with a small masking tape. When the protection film is peeled off, static electricity is generated between the film and polarizer. This should be peeled off slowly and carefully by people who are electrically grounded and with well ion-blown equipment or in such a condition, etc. (2) When the module with protection film attached is stored for a long time, sometimes there remains a very small amount of glue still on the bezel after the protection film is peeled off. (3) You can remove the glue easily. When the glue remains on the bezel surface or its vestige is recognized, please wipe them off with absorbent cotton waste or other soft material like chamois soaked with normal-hexane.
Chapter 3
Main unit button
Power MENU CH CH VOL + VOL Input
On Screen Display
On Screen Display
TV Source
A. PICTURE
a. PICTURE MODE (CUSTOM/ STANDARD / MOVIE / GAME) b. BACKLIGHT (0~100) c. BRIGHTNESS (0~100) d. CONTRAST (0~100) e. COLOR (0~100) f. TINT (-32~32) g. SHARPNESS (0~100) h. COLOR TEMPERATURE (CUSTOM/COOL/NORMAL/WARM) i. ADVANCED VIDEO i-1. DNR(OFF/LOW/MEDIUM/STRONG) i-2. BLACK LEVEL EXTENDER (ON/OFF) i-3. WHITE PEAK LIMITATOR (ON/OFF) i-4 CTI(OFF/LOW/MEDIUM/STRONG) i-5 FLESH TONE (ON/OFF) i-6 ADAPTIVE LUMA (ON/OFF)
B. AUDIO
a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. SPEAKERS (ON/OFF) f. Wireless SPEAKERS (ON/OFF) g. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h. SPEAKER SETTING h-1. SPEAKER LOCATION( Auto / Left / Center /Right / Rear Right / Sub Woofer / Rear Left ) h-2. TRIM h-2-1. Left(0~100) h-2-2. Right(0~100) h-2-3. Rear Left(0~100) h-2-4. Rear Right(0~100) h-2-5. Center(0~100) h-2-6. Sub Woofer(0~100) h-3. SPEAKER DISTANCE SETUP h-3-1. TV (0~15ft.) h-3-2. Rear Left(0~15ft.) h-3-2. Rear Right(0~15ft.)
C. TV
a. TUNER MODE (ANTENNA/CABLE) b. AUTO SEARCH (RUN) c. SKIP CHANNEL (TABLE) d. Digital Audio Out (Off / Dolby Digital / PCM) e. TIME ZONE (HAWALL/EASTTERN/INDIANA/CENTRAL/MOUNTAIN/ARIZONA/PACIFIC/ALASKA) f. Daylight Saving(ON/OFF)
D. SETUP
a. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. ANALOG CC (OFF/CC1/CC2/CC3/CC4) d. DIGITAL CC(OFF/SERVICE1/ SERVICE2/ SERVICE3/ SERVICE4/ SERVICE5/ SERVICE6) e. DIGITAL CC STYLE e-1. CAPTION STYLE (AS BROADCASTER/CUSTOM) e-2. FONT SIZE(SMALL/MEDIUM/LARGE) e-3. FONT COLOR (GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE) e-4. FONT OPACITY (SOLID/TRANSLUCENT/TRANSPARENT) e-5. BACKGROUND COLOR (GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE) e-6. BACKGROUND OPACITY (SOLID/TRANSLUCENT/TRANSPARENT) e-7. WINDOW COLOR (GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE) e-8. WINDOW OPATITY (SOLID/TRANSLUCENT/TRANSPARENT) f. Image Cleaner g. RESET ALL SETTING
E. PARENTAL
a. PASSWORD a-1. CHANNEL BLOCK a-2. TV RATING a-3. MOVIE RATING a-4. BLOCK TV UNRATED a-5. ACCESS CODE EDIT
RGB Mode
A. PICTURE ADJUST
a. AUTO PICTURE (Run) b. BACKLIGHT (0~100) c. BRIGHTNESS (0~100) d. CONTRAST (0~100) e. COLOR TEMPERATURE(CUSTOM, 6500K,9300K) f. H-SIZE (0~255) g. H-POSITION (0~100) h. V-POSITION (0~100) i. FINE TUNE (0~31)
B. AUDIO
a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. SPEAKERS (ON/OFF) f. Wireless SPEAKERS (ON/OFF) g. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h. SPEAKER SETTING h-1. SPEAKER LOCATION ( Auto / Left / Center / Right / Rear Right / SubWoofer / Rear Left ) h-2. TRIM h-2-1. Left(0~100) h-2-2. Right(0~100) h-2-3. Rear Left(0~100) h-2-4. Rear Right(0~100) h-2-5. Center(0~100) h-2-6. Sub Woofer(0~100) h-3. SPEAKER DISTANCE SETUP h-3-1. TV (0~15ft.) h-3-2. Rear Left(0~15ft.) h-3-2. Rear Right(0~15ft.)
CONFIDENTIAL DO NOT COPY Page 3-4 File No. SG-0228
C. SETUP
a. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. Image Cleaner d. RESET ALL SETTING
HDMI MODE
A. PICTURE
a. PICTURE MODE (CUSTOM/ STANDARD /MOVIE / GAME) b. BRIGHTNESS (0~100) c. CONTRAST (0~100) d. COLOR (0~100) e. TINT (-32~32) f. SHARPNESS (0~100) g. COLOR TEMPERATURE (CUSTOM/COOL/NORMAL/WARM) h. ADVANCED VIDEO h-1. DNR(OFF/LOW/MEDIUM/STRONG) h-2. BLACK LEVEL EXTENDER (ON/OFF) h-3. WHITE PEAK LIMITATOR (ON/OFF) h-4 CTI(OFF/LOW/MEDIUM/STRONG) h-5 FLESH TONE (ON/OFF) h-6 ADAPTIVE LUMA (ON/OFF)
B. AUDIO
a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. SPEAKERS (ON/OFF) f. Wireless SPEAKERS (ON/OFF) g. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h. SPEAKER SETTING h-1. SPEAKER LOCATION ( Auto / Left / Center / Right / Rear Right / SubWoofer / Rear Left )
h-2. TRIM h-2-1. Left(0~100) h-2-2. Right(0~100) h-2-3. Rear Left(0~100) h-2-4. Rear Right(0~100) h-2-5. Center(0~100) h-2-6. Sub Woofer(0~100) h-3. SPEAKER DISTANCE SETUP h-3-1. TV (0~15ft.) h-3-2. Rear Left(0~15ft.) h-3-3. Rear Right(0~15ft.)
C. SETUP
a. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. Image Cleaner d. RESET ALL SETTING
Video Sources
AV1AV2COMPONENT1COMPONENT2
A. PICTURE
a. PICTURE MODE (CUSTOM/ STANDARD /MOVIE / GAME) b. BRIGHTNESS (0~100) c. CONTRAST (0~100) d. COLOR (0~100) e. TINT (-32~32) f. SHARPNESS (0~100) g. COLOR TEMPERATURE(CUSTOM/COOL/NORMAL/WARM) h. ADVANCED VIDEO h-1. DNR(OFF/LOW/MEDIUM/STRONG) h-2. BLACK LEVEL EXTENDER (ON/OFF) h-3. WHITE PEAK LIMITATOR (ON/OFF) h-4 CTI(OFF/LOW/MEDIUM/STRONG) h-5 FLESH TONE (ON/OFF) h-6 ADAPTIVE LUMA (ON/OFF)
B. AUDIO
a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. SPEAKERS (ON/OFF) f. Wireless SPEAKERS (ON/OFF) g. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h. SPEAKER SETTING h-1. SPEAKER LOCATION( Auto / Left / Center / Right / Rear Right / SubWoofer / Rear Left ) h-2. TRIM h-2-1. Left(0~100) h-2-2. Right(0~100) h-2-3. Rear Left(0~100) h-2-4. Rear Right(0~100) h-2-5. Center(0~100) h-2-6. Sub Woofer(0~100) h-3. SPEAKER DISTANCE SETUP h-3-1. TV (0~15ft.) h-3-2. Rear Left(0~15ft.) h-3-3. Rear Right(0~15ft.)
C. SETUP
a. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. Analog CC(Off/CC1/CC2/CC3/CC4) d. Image Cleaner e. RESET ALL SETTING
D. PARENTAL
a. PASSWORD a-1. CHANNEL BLOCK a-2. TV RATING a-3. MOVIE RATING a-4. BLOCK TV UNRATED a-5. ACCESS CODE EDIT
Chapter4
Factory preset timings
This timing chart is already preset for the TFT LCD analog & digital display monitors.
Resolution 640x480 640x480 800X600 800x600 800X600 1024x768 1024X768 720x400 1366X768 Remark: Refresh rate 60Hz 75Hz 60Hz 75Hz 85Hz 60Hz 75Hz 70Hz 60 P: positive Horizontal Frequency 31.5kHz 37.5kHz 37.9kHz 46.9kHz 53.7kHz 48.4kHz 60.0kHz 31.46kHz 47.7KHZ N: negative Vertical Frequency 59.94Hz 75.00Hz 60.317Hz 75.00Hz 85.06Hz 60.01Hz 75.03Hz 70.08Hz 60.00HZ Horizontal Polarity N N P P P N P N P Vertical Polarity N N P P P N P P N Pixel Rate 25.175MHz 31.500 MHz 40.000 MHz 49.500 MHz 56.250 MHz 65.000 MHz 78.750 MHz 28.320 MHz 85.500 MHz
Native Resolution
Resolution 1366X768
Refresh rate 60Hz
Horizontal Frequency 47.7kHz
Vertical Frequency 60Hz
Horizontal Polarity P
Vertical Polarity N
Pixel Rate 85.5MHz
Chapter5
Pin Assignment
The PDP analog display monitors use a 15 Pin Mini D-Sub connector as video input source. Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Red Green Blue Ground Ground R-Ground G-Ground B-Ground +5V for DDC Ground No Connection (SDA) H-Sync (Composite Sync) V-Sync (SCL)
Description
1 6 11
5 10 15
RGB Signal:
a. Sync Type TTL (Separate / Composite) or Sync. On Green b. Sync polarity Positive or Negative c. Video Amplitude RGB: 0.7Vp-p d. Frequency H: support to 30K~70KHz V: support to 50~85Hz e. Pixel Clock: support to 110MHz f. Connector type: 15-pin D-Sub, female g. Impedance: 75
HDMI CONNECT PIN ASSIGNMENT:

PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SIGNAL ASSIGNMENT TMDS Data2+ TMDS Data2 Shield TMDS Data2TMDS Data1+ TMDS Data1 Shield TMDS Data1TMDS Data0+ TMDS Data0 Shield TMDS Data0TMDS Clock+ TMDS Clock Shield TMDS ClockCEC Reserved (N.C on device) SCL SDA DDC/CEC Ground +5V Power Hot Plug Detect
HDMI Signal (HDMI):

a. Pin Assignment Refer to HDMI Pin Assignment b. Type A c. Polarity Positive or Negative d. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i)
F-Type TV RF connector NTSC system

a. Signal level Analog 1Vp-p typical b. Frequency 55~801 MHz
ATSC system
a. IF-output level 1Vp-p minimum b. Frequency 57~803 MHz
QAM system (supporting clear QAM)

a. IF-output level 1Vp-p minimum b. Frequency 57~849 MHz
AV/Composite Video (CVBS) Connector

a. Frequency: H: 15.734KHz V: 60Hz (NTSC) b. Signal level: Video ( Y + C ):1Vp-p Sync (H+V):0.3V below Video (Y+C) c. Impedance: 75 d. Connector type: RCA Jack Component video Connector a. Frequency: H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) b. Signal level: Y: 1Vp-p Pb: 0.350Vp-p Pr: 0.350Vp-p c. Impedance: 75 d. Connector type: RCA Jack
Analog audio in
a. Signal level 1.0Vrms b. Impedance: 47K c. Frequency: 30Hz-20KHz d. Connector type: RCA L/R Analog Audio out a. Signal level: 2.0Vmax b. Impedance: 560 c. Frequency Response: 30Hz-20KHz (exclude wireless on mode) d. Connector type: RCA L/R:
Digital audio out

a. Peak emission wavelength: 630 690 m b. Transmission Speed: 13.2M pbs c. Connector type: Optical fiber transmitter
Digital audio in
a. Peak emission wavelength: 650nm b. Transmission Speed: 16M pbs c. Connector type: Optical fiber receiver
Chapter 6
Main Board I/o Connections
J10 CONNECTION (MAIN TO PANEL PSU) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description VS_ON PDP_12VFAN PDP_12VSC GND GND GND GND GND GND PDP_5VSC PDP_5VSC PDP_5VSC PDP_5VSB RLY_ON ACD
J12 CONNECTION (MAIN TO AUDIO BOARD) Pin 1 2 3 4 5 6 7 8 Description AUDIO_CT DACGND AUDIO_OUTR AMP_MUT AUDIO_OUTL DACGND GND ACD
J13 CONNECTION Pin 1 2 Description +5V GND
J9 CONNECTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description AMBER WHITE OIRI 5VSB 5VSB GND GND ADIN-1 ADIN-2 DV33SB HPL_IN GND HPR_IN HPIN_DET
J14 CONNECTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description +5V PGND NC NC TX_SGND ID_Trigge NC NC NC NC TX_Mute NC NC ACD_mute AO1LRCK AO1SDATA1 AO1BCK AO1MCLK
J7 CONNECTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description GND GND A7P A7N CK2P CK2N A6P A6N A5P A5N A4P A4N A3P A3N CK1P Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Description CK1N A2P A2N A1P A1N A0P A0N LVDS_ROTATE LVDS_OPTION GND GND GND LVDSVDD LVDSVDD LVDSVDD
AUDIO BD I/O CONNECTIONS OF TV

J1 CONNECTION (MAIN BOARDAUDIO BOARD) Pin 1 2 3 4 5 6 7 8 Description CT COM R mute L SGND GND AC_detect
J2 CONNECTION (POWER BOARDADUIO BOARD) Pin 1 2 3 4 Description +24V +24V GND GND
J3 CONNECTION (AUDIO BOARDEMI BOARD) Pin 1 2 3 4 5 6 WAFER INFORMATION Description ROUT+ GND CTOUT+ GND LOUT+ GND
Pin1
EMI BD I/O CONNECTIONS

J1 CONNECTION (AUDIO BOARDEMI BOARD) Pin 1 2 3 4 5 6 Description ROUT+ GND CTOUT+ GND LOUT+ GND
J2 CONNECTION (EMI BOARDSPEAKERS) Pin 1 2 3 4 5 6 Description ROUT+ GND CTOUT+ GND LOUT+ GND
WAFER INFORMATION
Pin1
Pin1
AUDIO BD I/O CONNECTIONS OF SUBWOOFER

J1 CONNECTION (RX MODULEAUDIO BOARD) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Audio BD Description VCCIO PGND RS PGND SGND NC LS NC PGND NC Mute NC NC CH/ID NC LED- NC SYSTEM_MUTE Module Description VCCIO PGND - PGND UGND TEST - - - - Mute - - CH/ID - - - GPIO
J2 CONNECTION (POWERAUDIO BOARD) Pin 1 2 3 4 5 6 7 Description GND 5V AC_detect GND GND 24V+ 24V+
J3 CONNECTION (AUDIO BOARDI/O BOARD) Pin 1 2 3 4 Description LOUT+ LGND ROUT+ RGND
J4 CONNECTION (AUDIO BOARDSUBWOOFER) Pin 1 2 Description SWOUT+ SWOUT-
J5 CONNECTION (AUDIO BOARDLED BOARD) Pin 1 2 Description GND +5V
J6 CONNECTION (AUDIO BOARDI/O BOARD) Pin 1 2 3 Description CH/ID GND GND
WAFER INFORMATION
Pin1
Pin1
Pin1
CONNECTOR BD I/O CONNECTIONS

J1 CONNECTION (TOPBOTTOM) Pin 1 2 3 4 5 6 7 J2 CONNECTION (TOPBOTTOM) Pin 1s 1t 2s 2t WAFER INFORMATION Description LS- LS+ RS- RS+ Description RS+ RS- LS+ LS- Switch+ Switch- GND
Blue circle : 1s Red circle : 1t Green circle : 2s Brown circle : 2t
Pin1
Chapter 7
Theory of Circuit Operation
The operation of D-SUB 15pin route

The D-SUB 15pin is input analog signal to the MT5372 transfer A/D converter then generates the vertical and horizontal timing signals for display device.
The operation of HDMI CON route

Then transfer to the MT5372, the MT5372 generates the vertical and horizontal timing signals for display device.
The operation of HDTV & Component route

HDTV & Component signal is input to the MT5372 then MT5372 generates the vertical and horizontal timing signals for display device.
The operation of Video & S-Video route

The Video and S-Video signal is transmission signal to the MT5372 then MT5372 generates the vertical and horizontal timing signals for display device.
The operation of TV route

TV signal is processes to the tuner and output to MT5372 then MT5372 generates the vertical and horizontal timing signals for display device. Audio is processes to the tuner output to SIF circuit and output to MT5372.Then MT5372 process to MT8291 and output to Audio Board transfer to speaker.
The operation of DTV route

DTV signal is processes to the tuner and transmission to MT5112 and output signal to MT5372 generates the vertical and horizontal timing signals for display device.
The operation of Audio AUX In route

Audio optical signal is processes to the CS8416 generates I2S audio signal transmission to MT5372 . Then MT5372 process to MT8291 and output to Audio Board transfer to speaker.
The operation of keypad

There are 7 keys to control and select the function of VX32L and also has one LED to indicate the status of operation. They are Power, , + -, Input, OSD.
MT5372 Application MT5372 is a highly integrated video and audio single chip processor for emerging HDTV-Ready LCD TV. It includes one 3D/2D TV Decoder recovering the best image from CVBS, and in addition, its analog input also support popular S-Video, Component, VGA video source. On-chip advanced motion adaptive de-interlacer (MDDitm) converts accordingly the interlace video into smooth non-flicking progressive motion pictures. With on-chip advanced 2D Graphic processor,MT5372 provides customers with high quality UI adding significant end product value. Flexible scalar provides wide adoption to various LCD panel for different video sources. Its on-chip audio processor decodes whole world standard audio signals from tuner with lip sync control, delivering high quality post-processed sound effect to customers. On-chip microprocessor and reference FW reduces the system BOM and shortens the schedule of UI design by high-level C program. With truly SOC design, MT5372 offers our customers the real cost-effective high performance HDTV-ready solution.
1. Video input
a. Input Multiplexing
1.component X2 2.composite X2 3.HDMI X3 4.VGA X1 5.RF&DTV X1
b. Input formats:
1.support HDTV 480i/480p/720p/1080p 2.support Y/C signal 1VP-P/75 3.support 480i/408p/720p/1080i/1080p 4.support VGA input up to 1366x168@60HZ 6.support RF NTSC system Frequency 55~801MHZ;DTV 480i/480p/720p/1080p 2. Decoder TVD 1.Single 2nd generation TV decoder 2.Automatic TV standard detection supporting NTSC, NTSC-4.43, 3.Enhanced 2nd generation NTSC Motion Adaptive 3D comb filter 4.Motion Adaptive 3D Noise Reduction 5.Embedded VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS 6.Supporting Macro vision detection YPbPr 1.Supporting HDTV 480i/480p/576i/576p/720p/1080i input 2.Smart detection on Scart function for European region VGA 1.Supporting various VGA input timings up to SXGA (1280x1024@75Hz). 2.Supporting Separate/Composite/SOG sync types
Digital port 1.1 digital port supporting DVI 24-bit RGB or CCIR-656/601 digital video input format 2.1 additional 8 bit digital port for ITU656 video format VBI 1.Dual VBI decoders for the application of V-Chip/Closed-Caption/XDS/ Teletext/WSS/VPS 2.Supporting external VBI decoder by YPrPb input 3.VBI decoder up to 1000 pages Teletext.
3. Support Formats: Support NTSC, NTSC-4.43 Automatic Luma / Chroma gain control Automatic TV standard detection NTSC Motion Adaptive 3D comb filter Motion adaptive 3D Noise Reduction VBI decoder for closed-caption/XDS/Teletext/WSS/VPS Macro vision detection 4. 2D-Graphic/OSD processor Embedded two backend RGB domain OSD planes and one YUV domain OSD plane. to support Main/PIP Teletext/Close-caption functions together with setup menu 1.Supporting alpha blending among these two planes and video 2.Supporting Text/Bitmap decoder 3.Supporting line/rectangle/gradient fill 4.Supporting bitblt 5.Supporting color Key function 6.Supporting Clip Mask 7.65535/256/16/4/2-color bitmap format OSD, 8.Automatic vertical scrolling of OSD image
9.Supporting OSD mirror and upside down
5. Microprocessor interface When power is supplied and power key is pressed then the rest circuit lets Reset to low state that will reset the MT5372 to initial state. After that the Reset will transits to high state and the MT5372 start to work that microprocessor executes the programs and configures the internal registers. The execution speed of CPU is 162 MHz. PIP/POP HARDWARE LIMITION:
Main SUB DTV/TV AV Component RGB HDMI AUX IN 6. Video processor

1.Color Management Fully 10-bit processing to enhance the video quality Advanced flesh tone and multiple-color enhancement. (For skin, sky, and grass) Gamma/anti-Gamma correction Advanced Color Transient Improvement (CTI) Saturation/hue adjustment 2.Contrast/Brightness/Sharpness Management Sharpness and DLTI/DCTI Brightness and contrast adjustment Black level extender White peak level limiter Adaptive Luma/Chroma management
DTV/TV
AV
Component
RGB
HDMI
AUX IN
3.De-interlacing 2nd generation advanced Motion adaptive de-interlacing Automatic detect film or video source 3:2/2:2 pull down source detection Main/PIP 2 independent de-interlacing processor 4.Scaling 2nd generation high resolution arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X Advanced linear and non-linear Panorama scaling Programmable Zoom viewer Picture-in-Picture (PIP) Picture-Out-Picture (POP) 5.Display Advanced dithering processing for LCD display with 6/8/10 bit output 10bit gamma correction Supporting alpha blending for Video and two OSD planes Frame rate conversion 6.Seamless performance comparing demonstration function Support Left/Right video processing comparing function without additional resources (DRAM) for customers demonstration. All the video functions (De-interlace/3D comb/NR/Flesh tone/CTI) can be included 7. DRAM Usage
1.For features of 5372, Dual for enhance features support, and single 8x16 DDR for simple function support Lists are the comparison chart between function support lists of (2xDDR) and (1xDDR)
2.For single DDR,5372only support 1080i bob mode de-interlacing. (Non-3D de interlace) 3.With single DDR, it is suggested not to support PIP/POP features. Due to DDR Bandwidth limitation on PIP when single DDR.
MT8291 Application
The MT8291 is highly integrated stereo audio CODEC.The MT8291 performs stereo analog-to-digital and two digital-to-analog conversions with single-ended analog voltage input and output. Its up to 24bit serial values at sample rates up to 192kHz.A7:1 stereo input multiplexer and automatic level control are included. The PGA is available for line inputs and provides gain/attenuation of 21dB in 0.5 steps. The two DAC outputs reach 2Vrms at 12V supply, they also include headphone, two Left/Right line outputs with volume gain/attenuation -127dB to +12dB and digital de-emphasis function. Sampled data is transmitted by the serial audio interface at rates from 32kHz to 192kHz.For audio clock application, the MT8291 supports master, slave modes and three data formats in serial interface. Individual two I2S clock and data supported different sample rates for ADC and DAC parts simultaneously, then output from DAC1 and DAC2 independently.
BLOCK DIAGRAM
Feature List
24-bit Sigma- Delta ADC and DAC Allows 2Vrms input swing into ADC part ADC up to 96 kHz sampling rates 90 dB ADC dynamic range Automatic Gain Control (AGC) 90 dB DAC dynamic range DAC up to 192 kHz sampling rates Two channels of ADC and four independent channels of DACs (two L/R line outputs and a headphone output) Supports two sets of I2S clocks and data inputs independently System clocks: 128Fs, 192Fs, 256Fs, 384Fs, 512Fs, 768Fs Selectable serial audio interface formats:left justified, right justified and I2S up to 24 bits +3.0V to +3.6V digital power supply +8.2V to +13.2V analog power supply 7-channel input multiplexer with ADC programmable gain amplifiers (PGAs) gain from +21dB to 21dB in 0.5dB step Two individual sets of I2S ports simultaneously support different sample rates for the ADC and DACs and then output from DAC1 and DAC2 independently
CONTROL INTERFACE TIMING - 2 WIRE PORT
Figure. Control Port Timing
AUDIO INTERFACE TIMING1

AVDD=12V,DVDD=3.3V,ADCGND/DACGND=0V, Ta= 25 C, fs=48kHz, MCLK=256fs, 24bit data, Master Mode
Figure. Master Mode Timing
AUDIO INTERFACE TIMING2

AVDD=12V,DVDD=3.3V,ADCGND/DACGND=0V, Ta= + 25 C, fs=48kHz, MCLK=256fs, 24bit data, Slave Mode
Figure. Slave Mode Timing
3. HDCP Decryption HDCP decryption contains all necessary logic to decrypt the incoming audio and video data. The decryption process is entirely controlled by the host microprocessor through a set sequence of register reads and wires through the DDC channel. Pre-programmed HDCP keys and key Selection Vector are used in the decryption process. A resulting calculated to an XOR mask during each clock cycle to decrypt the audio/video data in sync with the host. 4.General Feature List :
1 . Host CPU: 1. ARM 926EJ 2.16K I-Cache and 16K D-Cache 3. 8K Data TCM and 8K instruction 4. JTAG ICE interface 5. Watch Dog timers 2 . Transport Demuxer : 1. Support 3 independent transport stream inputs 2. Support serial/parallel interface for each transport stream input 3. Support ATSC , DVB , and MPEG2 transport stream inputs. 4. Programmable sync detection. 5. Support DES/3-DES De-scramble. 6. 96 PID filter and 128 section filters. 7. Support TS recording via IEEE1394 interface. 3 . MPEG2 Decoder : 1. Support dual MPEG-2 HD decoder or up to 8 SD decoder. 2. Complaint to MP@ML , MP@HL and MPEG-1 video standards. 4 . JPEG Decoder : 1. Decode Base-line or progressive JPEG file.
5 . 2D Graphics : 1. Support multiple color modes. 2. Point , horizontal/vertical line primitive drawing. 3. Rectangle fill and gradient fill functions. 4. Bitblt with transparent , alpha blending , alpha composition and stretch. 5. Font rendering by color expansion. 6. Support clip masks. 7. YCrCb to RGB color space transfer. 6 . OSD Display : 1. 3 linking list OSDs with multiple color mode. 2. OSD scaling with arbitary ratio from 1/2x to 2x.
3. Square size , 32x32 or 64x64 pixel , hardware cursor.

7 . Video Processing : 1. Advanced Motion adaptive de-interlace on SDTV resolution. 2. Support clip 3. 3:2/2:2 pull down source detection. 4. Arbitrary ratio vertical/horizontal scaling of video , from 1/15X to 16X. 5. Support Edge preserve. 6. Support horizontal edge enhancement. 7. Support Quad-Picture. 8 . Main Display : 1. Mixing two video and three OSD and hardware cursor. 2. Contrast/Brightness adjustment. 3. Gamma correction. 4. Picture-in-Picture( PIP ). 5. Picture-Out-Picture( POP ). 6. 480i/576i/480p/576p/720p/1080i output 9 . Auxiliary Display : 1. Mixing one video and one OSD. 2. 480i/576i output.
10 . TV Encoder : 1. Support NTSC M/N , PAL M/N/B/D/G/H/I 2. Macrovision Rev 7.1.L1 3. CGMS/WSS. 4. Closed Captioning. 5. Six 12-bit video DACs for CVBS , S-video or RGB/YPbPr output. 11 . Digital Video Interface : 1. Support SAV/EAV. 2. Support 8/16 for SD/HD digital video input. 3. Support 8/16/24 bits digital output for main display. 4. Support 8 bits digital output for aux display. 12 . DRAM Controller : 1. Support 64Mb to 1Gb DDR DRAM devices. 2. Configurable 32/64 bit data bus interface.
3. Support DDR266 , DDR333 , DDR400 , JEDEC specification compliant SDRAM.

13 . Peripheral Bus Interface : 1. Support NOR/NAND flash. 2. Support CableCard host control bus. 14 . Audio : 1. Support Dolby Digital AC-3 decoding. 2. MPEG-1 layer I/II , MP3 decoding. 3. Dolby prologic II. 4. Main audio output : 5.1ch + 2ch ( down mix ) 5. Auxiliary audio output : 2ch. 6. Pink noise and white noise generator. 7. Equalizer. 8. Bass management. 9. 3D surround processing include virtual surround. 10. Audio and video lip synchronization. 11. Support reverberation. 12. SPDIF out. 13. I2S I/F.
15 . Peripherals : 1. Three UARTs with Tx and Rx FIFO , two of them have hardware flow control. 2. Two serial interfaces , one is master only the other can be set to master mode or slave mode. 3. Two PWMs. 4. IR blaster and receiver. 5. IEEE1394 link controller. 6. IDE bus : ATA/ATAPI7 UDMA mode 5 , 100MB/s. 7. Real-time clock and watchdog controller. 8. Memory card I/F : MS/MS-pro ,SD ,CF ,and MMC 9. PCMCIA/POD/CI interface 16 . IC Outline : 1. 471 Pin BGA Package.
2. 3.3V/1.2V dual Voltage. MX29LV320BTTC (Flash) Application : The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory.
The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV320AT/B offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV320AT/B has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV320AT/B uses a command register to manage this functionality. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29LV320AT/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.
BLOCK DIAGRAM
BUS OPERATION--1
Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.00.5V, VHH=11.5-12.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,DOUT=Data OUT Notes: 1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. 2.The sector group protect and chip unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Chip Unprotection" section. 3.If WP/ACC=VIL, the two outermost boot sectors remain protected. If WP/ACC=VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP/ACC=VHH, all sectors will be unprotected. 4.DIN or Dout as required by command sequence, data polling, or sector protection algorithm. 5.Address are A20:A0 in word mode (BYTE=VIH), A20:A-1 in byte mode (BYTE=VIL).
BUS OPERATION--2
Notes: 1.Code=00h means unprotected, or code=01h protected. 2.Code=99 means factory locked, or code=19h not factory locked.
WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of memory , the system must drive WE and CE to VIL, and OE to VIH.An erase operation can erase one sector, multiple sectors , or the entire device. A "sector address" consists of the address bits required to uniquely select a sector. Writing specific address and data commands or sequences into the command register initiates device operations. Table A defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the Automatic Select command sequence, the device enters the Automatic Select mode. The system can then read Automatic Select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more information.ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.
TABLE A. MX29LV320AT/B COMMAND DEFINITIONS
Legend:
X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse. PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse. SA=Address of the sector to be erased or verified. Address bits A20-A12 uniquely select any sector. ID=22A7h(Top), 22A8h(Bottom)
Notes:
1.All values are in hexadecimal. 2.Except when reading array or Automatic Select data, all bus cycles are write operation. 3.The Reset command is required to return to the read mode when the device is in the Automatic Select mode or if Q5 goes high. 4.The fourth cycle of the Automatic Select command sequence is a read cycle. 5.The data is 99h for factory locked and 19h for not factory locked. 6.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third cycle of the command sequence, address bit A20=0 to verify sectors 0~31, A20=1 to verify sectors 32~70 for Top Boot device. 7.Command is valid when device is ready to read array data or when device is in Automatic Select mode. 8.The system may read and program functions in non-erasing sectors, or enter the Automatic Select mode, when in the erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 9.The Erase Resume command is valid only during the Erase Suspend mode.
STANDBY MODE
MX29LV320AT/B can be set into Standby mode with two different approaches. One is using both CE and RESET pins and the other one is using RESET pin only. When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc 0.3V. Under this condition, the current consumed is less than 0.2uA (typ.). If both of the CE and RESET are held at VIH, but not within the range of VCC 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (ICC2) is required even CE = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes. When using only RESET, a CMOS standby mode is achieved with RESET input held at Vss 0.3V, Under this condition the current is consumed less than 1uA (typ.). Once the RESET pin is taken high, the device is back to active without recovery delay.In the standby mode the outputs are in the high impedance state, independent of the OE input.MX29LV320AT/B is capable to provide the Automatic Standby Mode to restrain power consumption during readout of data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To active this mode, MX29LV320AT/B automatically switch themselves to low power mode when MX29LV320AT/B addresses remain stable during access time of tACC+30ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 0.2uA (CMOS level). RESET OPERATION 01The RESET pin provides a hardware method of resetting the device to reading array data. When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS0.3V, the standby current will be greater.The RESET pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory.
If RESET is asserted during a program or erase operation, the RY/BY pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/BY pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 14 for the timing diagram.
WRITE PROTECT (WP)

The write protect function provides a hardware method to protect boot sectors without using VID. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two "outermost" 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in Sector/Sector Group Protection and Chip Unprotection". The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K Byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Group Protection and Chip Unprotection". Note that the WP/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
SOFTWARE COMMAND DEFINITIONS :

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 3 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device (whenapplicable). All addresses are latched on the falling edge of WE or CE, whichever happens later. All data are latched on rising edge of WE or CE, whichever happens first.
WRITE OPERATION STATUS

The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY.Table B and the following subsections describe the functions of these bits. Q7, RY/BY, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
Table B. Write Operation Status
Notes: 1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle. 2.Performing successive read operations from any address will cause Q6 to toggle. 3.Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit. However, successive reads from the erase-suspended sector will cause Q2 to toggle.
Fig C. COMMAND WRITE OPERATION
Fig D. READ TIMING WAVEFORMS
Fig E. RESET TIMING WAVEFORM
DDR SDRAM (NT5DS16M16CS-5T) Application:

Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access.Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Block Diagram (16Mb x 16)
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Pin Configuration - 400mil TSOP II (x4 / x8 / x16)
Mode Register Operation
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result.
Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation.
Extended Mode Register Definition
Truth Table a: Commands
1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects ,Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.) 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Precharge feature (non-persistent), A10 low disables the Auto Precharge feature. 5. A10 LOW: BA0, BA1 determine which bank is precharged.A10 HIGH: all banks are precharged and BA0, BA1 are Dont Care. 6. This command is auto refresh if CKE is high; Self Refresh if CKE is low. 7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are Dont Care except for CKE. 8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts 9. Deselect and NOP are functionally interchangeable.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0,BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = dont care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = dont care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.The refresh addressing is generated by the internal refresh controller. This makes the address bits Dont Care during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8s (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down.When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are Dont Care during Self Refresh operation. The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
Operations:
Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is disabled. During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). The following timing figure entitled Read Burst: CAS Latencies (Burst Length=4) illustrates the general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble . Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure entitled Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8).A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data is shown in timing figure entitled Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4). Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on following:
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
Read Command
Writes
Write bursts are initiated with a Write command, as shown in timing figure Write Command on following: The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled. During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and tDQSS(max)). Timing figure Write Burst (Burst Length = 4) on page 33 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored.Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained.
The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture).
Write Command
Data Input (Write)
Data Output (Read)
Optical Receiver CS8416 Application:

The CS8416 is a monolithic CMOS device which receives and decodes audio data according to the AES3,IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8416 utilizes an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the CS8416. Input data is either differential or single-ended. A low jitter clock is recovered from the incoming data using a PLL. The decoded audio data is output through a configurable,3-wire serial audio output port. The channel status and Q-channel subcode portion of the user data are assembled in registers and may be accessed through an SPI or IC port. Three General Purpose Output (GPO) pins are provided to allow a variety of signals to be accessed under software control. In hardware mode, dedicated pins are used to select audio stream inputs for decoding and transmission to a dedicated TX pin. Hardware mode also allows direct access to channel status and user data output pins. Figure A and Figure B show the power supply and external connections to the CS8416 when configured for software and hardware modes. Please note that all I/O pins, including RXN and RXP[7:0], operate at the VL voltage.
TYPICAL CONNECTION DIAGRAMS
Figure A. Typical Connection Diagram - Software Mode
Figure B. Typical Connection Diagram - Hardware Mode
S/PDIF RECEIVER
The CS8416 includes an AES3/SPDIF digital audio receiver. The receiver accepts and decodes bi-phase encoded audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver consists of an analog differential input stage, driven through analog input pins RXP0 to RXP7 and a common RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data. External components are used to terminate the incoming data cables and isolate the CS8416. These components are detailed in Appendix A: External AES3/SPDIF/IEC60958 Receiver Components on page 51. Figure 9 shows the input structure of the receiver.
If RXP[7:0] is selected by either the receiver MUX or the TX passthrough MUX, N=1. If RXP[7:0] is selected by both the receiver MUX and the TX passthrough MUX, N=2. If RXP[7:0] is not selected at all, N=0 (i.e. high impedance). Figure. Receiver Input Structure
8:2 S/PDIF Input Multiplexer

The CS8416 employs a 8:2 S/PDIF input multiplexer to accommodate up to eight channels of input digital audio data. Digital audio data may be single-ended or differential. Differential inputs utilize RXP[7:0] and a shared RXN. Single ended signals are accommodated by using the RXP[7:0] inputs and AC coupling RXN to ground.All active inputs to the CS8416 8:2 input multiplexer should be coupled through a capacitor as these inputs are biased at VL/2 when selected. These inputs are floating when not selected. Unused multiplexer inputs should be left floating or tied to AGND. The recommended capacitor value is 0.01 F to 0.1 F.The recommended dielectrics for the AC coupling capacitors are C0G or X7R.The input voltage range for the input multiplexer is set by the I/O power supply pin, VL. The input voltage of the RXP[7:0] and RXN pins is also set by the level of VL. Input signals with voltage levels above VL or below DGND may degrade performance or damage the part.
Software Mode
The multiplexer select line control is accessed through bits RXSEL[2:0] in control port register 04h. The multiplexer defaults to RXP0. The second output of the input multiplexer is used to provide the selected input as a source to be output on a GPO pin. This pass through signal is selected by TXSEL[2:0] in control port register 04h. This singleended signal is resolved to full-rail, but is not de-jittered before it is output.
Hardware Mode
In hardware mode the input to the decoder is selected by dedicated pins, RXSEL[1:0].The pass through signal is selected by dedicated pins, TXSEL[1:0] for output on the dedicated TX pin.This single-ended signal is resolved to full-rail, but is not de-jittered before it is output.Selectable inputs are restricted to RXP0 to RXP3 for both the receiver and the TX output pin. These inputs are selected by RXSEL[1:0] and TXSEL[1:0] respectively.
OMCK System Clock Mode

A special clock switching mode is available that allows the OMCK clock input to automatically replace RMCK when the PLL becomes unlocked. This is accomplished without spurious transitions or glitches on RMCK. In Hardware mode this feature is enabled by a transition (rising edge active) on the OMCK pin after reset. Therefore to not enable the clock switching feature in Hardware mode, OMCK should be tied to DGND or VL. However, in Hardware mode, once the clock switching feature has been enabled, it can only be disabled by resetting the part. In Software mode the automatic clock switching feature is enabled by setting SWCLK bit in Control1 register to a 1. Additionally in Software mode, OMCK can be manually forced to output on RMCK by using the FSWCLK bit in the Control0 register.When the clock switching feature is enabled, OSCLK and OLRCK are derived from the OMCK input when the clock has been switched and the serial port is in master mode. When clock switching is enabled and the PLL is not locked, OLRCK will be OMCK/256 and OSCLK will be OMCK/4. When the PLL loses lock,the frequency of the VCO drops to ~500 kHz. When this system clock mode is not enabled, the OSCLK and OLRCK will be based on the VCO when the PLL is not locked. Table 2 shows an example of output clocks based on clock switching being enabled or disabled.
Table. Clock Switching Output Clock Rates
Clock Recovery and PLL Filter

Please see Appendix C: PLL Filter on page 55 for a general description of the PLL, selection of recommended PLL filter components, and layout considerations. Figure 5 and Figure 6 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter.
GENERAL PURPOSE OUTPUTS

Three General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in configuring the CS8416. Fourteen signals are available to be routed to any of the GPO pins. The outputs of the GPO pins are set through the GPOxSEL[3:0] bits in the Control2 (02h) and Control3 (03h) registers. All GPO pins default to GND after reset. GPO pins may be configured to provide the following data:
Table. GPO Pin Configurations Notes: 16. Frequency = 25 MHz Max, duty cycle not guaranteed, target duty cycle = 50% @ FS = 48 kHz.
CS8416 Block Diagram.
MP7720/7722 Application
In JV50P TV the MP7720 is a mono 10W Class D Audio Amplifier and the MP7722 is a stereo 10W Class D Audio Amplifier. It has each output power of 10 W at 24V supply into a 6 ohm load.
TYPICAL APPLICATION for MP7720
TYPICAL APPLICATION for MP7722
1. DESCRIPTION The MP7722 utilizes a single ended output structure capable of delivering 2 x 20W into 4 speakers. MPS Class D Audio Amplifiers exhibit the high fidelity of a Class A/B amplifier at efficiencies greater than 90%. The circuit is based on the MPS proprietary variable frequency topology that delivers low distortion, fast response time and operates on a single power supply.
2. Output power measurement

The output power as a function of the supply voltage is measured on the output pins at THD = 10%,in the JV50P TV Vcc=24V so we can see as shown in the following figure output.
3. Mute/Enable Function
The MP7722 EN inputs are active high enable controls. To enable the MP7722, drive EN with a 2.0V or greater voltage. To disable the Amplifier, drive it below 0.4V. While the MP7722 is disabled, the VDD operating current is less than 10A and the output driver MOSFETs are turned off. The MP7722 requires approximately 500ms from the time that EN is asserted (driven high) to when the amplifier begins normal operation.
MP7782 Application
In JV50P TV the MP7782 is a mono, 50W Class D Audio Amplifier. It has output power of 1 x50 W into 6 ohm with 24V supply. TYPICAL APPLICATION
DESCRIPTION The MP7782 utilizes a full bridge output structure capable of delivering 50W into 6 speakers. As in all other MPS Class D audio amplifiers, this device exhibits the high fidelity of a Class AB amplifier with an efficiency of 90%.
Chapter8
Waveforms
PC MODE(1366X768 60HZ) CH1 H-sync (R209); CH2 H-sync (L52)
CH1 V-sync (R213); CH2 V-sync (L53)
CH1 R (R203) CH1 R (C95)
CH1 B (R199) CH1 B (C92)
CH1 G (R195) CH1 G (C89)
AV&TV MODE (AV1/AV2/TV) VIDEO CH1 TV
CH1
AV1
CH1
AV2
COMPONENT MODE CH1 YPBPR1_Y
CH1 YPBPR2_Y
HDMI 1 CH1 RX1; CH2 RX1-B
Audio BD of TV Input Level: 100mV , Frequency: 1KHz (L and R and CT) 1. CH1: C200 + ; CH2: J3 PIN3
2. CH1: C108 -
CH2: U1 PIN7
3. CH1: ZD2 PIN2 ; CH2: ZD2 PIN1 [signal on]
[signal off]
CH1: C271 +
CH2: J3 PIN3
[signal off]
5. CH1: C192 + [Power on]
CH2: EN1
[Power off]
Audio BD of Subwoofer Input Level: 100mV , Frequency: 1KHz (LS and RS) 50Hz (Subwoofer) 1. CH1: C200 + ; CH2: J3 PIN3
2. CH1: C108 -
CH2: U1 PIN7
[signal off]
4. CH1: C170 +
CH2: J4 PIN2
[signal off]
6. CH1: C192 + [Power on]
CH2: EN1
[Power off]
7. CH1: R154 [Power on]
CH2: C142 +
[Power off]
8. CH1: R228 [Power off]
; CH2: EN1
Chapter 9
Trouble shooting
MONITOR DISPLAY NOTHING (PC MODE)
Start
N0
1. 2. 3. 4.
LED is lighted
Is Power board output +5VSB &DV12? Is J10 connector good? Is DC-DC OK? Is U1 (+5V) working ok?
Yes
N0
LED is lighting?
It is in power saving 1. Check video cable 2. Is the timing supported? 3. Check sync input 4. Check VGA SOG rout if analog (SOG)
Yes
N0
Is backlight on?
1.Check J10 PIN14 2.Is Power Board ok?
Yes Yes N0
U14 no data out?
It means data to LVDS 1.Is J7 connecting OK? 2.Check J1 +5V & +12V 3.Is panel ok? 4. Check P3 D-sub Input correct 5. Check analog input route
Yes
END
(TV, COMPOSITE VIDEO ) IS NOT DISPLAY CORRECTLY
Start
N0
Input signal good?
1.Check video 2.Check DVD player

Yes N0
U14 input correct?
1.Check P11(VIDEO) signal 2.Check signal between U14 (IF IN AV mode) 3.Check Tuner & U13 (IF TV mode)
Yes N0
U14 output correct?
1. Check U14 :DV33&DV12&AV15&AV12 2. Check X1 is OK?
Yes N0
LVDS output correct?
1.Check LVDS LINE 2.Check U14 clock (27MHz) 3.Check LVDS 5V or 12V
Yes
1.Chcak J7 Connect is good? 2.Is panel working ok?
END
(COMPONENT) IS NOT DISPLAY CORRECTLY
Start
N0 Input signal good?
1.Check video 2.Check hosts setting
Yes N0
P1 input correct?
1.Check signal between P1 2.Check power 12V& 5v
Yes N0 U14 input correct?
1.Check signal between U14&P1 2.Check U14 Clock (27MHZ) 3.Check U14 :DV33&DV12&AV15&AV12
Yes N0
LVDS output correct ?
1.Check U14 2. Check LVDS 5V or 12V
Yes
1.Is J7 connected good? 2.Is panel working ok?
END
(HDMI) IS NOT DISPLAY CORRECTLY
Start
N0 Input signal good?
1.Check video 2.Check hosts setting
N0 U22 input correct?
1.Check p6 & p7& P13 connect 2.Check U22 signal
Yes N0 U14 no data out ?
1.Check U14 power 2.Check between signal U22 and U14 3.Check U14 clock 27MHZ
Yes
1.Is J7 connected good? 2.Is panel working ok?
Yes
END
ROUBLE OF DC-DC CONVERTER
Start
Yes N0 J10 PIN10,11,12
The voltage is about + 5V 1.Check power board 2.Check power cable connection J10
Yes N0 J10 PIN 2,3
The voltage is about + 12V while power switch on 1.J10 connection good 2.Check J10 Pin2,3 transform +5V_TUNER 3.Check power board
Yes N0 U1 pin 5 6 7 8
The voltage is about +5V while power switch on 1.J10 connection good 2. Check U14 OPWRSB & OPCTRL2 Pin
Yes N0
U4,U2 pin2
The voltage is about
+3.3V
Yes N0 U10 pin2
+2.6V
Yes N0 U33 pin2
+3.3V
Yes N0 U7 pin2
+1.2V
Yes
U9 pin2
+1.5V
Yes
U35 pin2
+3.3V
END
TROUBLE OF DDC READING
Start
Yes N0
Analog DDC
Support DDC1/2B 1.Analog cable ok? 2.Check signal (U21 to P3) 3.Check U21 Voltage 4.Is compliant protocol?
Yes
N0
HDMIDDC
Support DDC1/2B 1.Analog cable ok? 2.Check signal (U23 to P6) 3.Check signal (U25 to P7) 4.Check signal (U26 to P13) 5.Is compliant protocol?
Yes
END
(TV_SIDE, AUDIO) IS NOT DISPLAY CORRECTLY

Start
N0
Input signal good?
1. Check Audio source 2. Check the player of source

Yes N0
J1 input correct?
1. Check signal of Main Board 2. Check signal of Audio Board (J1) 3. Check the wire of Main Board to Audio Board
Yes N0
1. Check the output volt of U1 and U2.

U1.U2 output correct?
Yes N0
U7.U8 signal correct?
1. Check C200(Ch R) and C201(Ch L) and C271 (Ch CT)
Yes N0 U7.U8 Volt correct?
1. Check VCC of U7 and U8. 2. Check 1/2VCC of U7 and U8 (R202.R203.R271). 3. Check ZD2(Ch R) and ZD3(Ch L) and ZD4 (Ch CT)
Yes N0 U7.U8 output correct?
1. Check feedback resistor and capacitor.
Yes
END
(SUBWOOFER_SIDE, AUDIO) IS NOT DISPLAY CORRECTLY

Start
N0
Input signal good?
1. Check Audio source 2. Check the player of source

Yes N0
J1 input correct?
1. Check signal of Main Board 2. Check signal of Audio Board (J1) 3. Having TX and RX module or not?
Yes N0
1. Check the output volt of U1 ~ U6.

U1~U6output correct?
Yes N0
U7.U8 signal correct?
1. Check C200(Ch R) and C201(Ch L) and C170 (Ch SW) and C171 (VB)
Yes N0 U7.U8 Volt correct?
1. Check VCC of U7 and U8. 2. Check 1/2VCC of U7 (R202.R203). 3. Check ZD2(Ch R) and ZD3(Ch L) and ZD4 (Ch CT)
Yes N0 U7.U8 output correct?
1. Check feedback resistor and capacitor.
Yes
END
Chapter 10
System Block Diagram
Block Diagram
LG50 X4 panel
Speaker
Digital Video bus
Power Board
AC IN
Audio Board
J14 TX Connect
J9
J7
J10
J12
Main Board
U12
J4 P1 P2 P11 Tuner AVX2 P10 P9
Keypad/IR Board
P5
P14
P13
P7
P6
P8
P3 P4
YPBPRX2 RCAX2 RJ11 AUX IN HDMIX3 RCA RGB earphone
SPDIF out Audio OUT
The TV system block diagram is powered by power board that transforms AC source of 100V~240V AC +/- 10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. The main board receives different types of video signal into the MT5372 Ic. Afterward, the MT5372 Ic process the signals control the various functions of the monitor and outputs control signal, video signal and power to the LG50 X4 panel to be displayed. The power send to the panel is first processed by the inverter. The function of the inverter is to step up the voltage supplied by the main board to the power that is needed to light up the lamps in the panel. Simultaneously, the digital video signals are processed in the panel and the outcome determines the brightness, pixel on/off and the color displayed on the panel. The analog video signals of YPbPr, TV, PC and A/V all video signals are translated from analog signals into MT5372 generates the vertical and horizontal timing signals for display device. The analog audio of YpbPr, TV, PC and A/V is transmitting to the MT8291 processed. The purpose is process the input audio signal to control volume, bass, treble, surround, and balance. All functions are controllable by the main board. Plus, all functions in the IC boards are programmable using I2C Bus.
Main Board Block Diagram
TV_AMP Board Block Diagram
RX_AMP Board Block Diagram

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Service Manual

Model #: VIZIO JV50P HDTV10A

VIZIO JV50P HDTV10A Service Manual

VIZIO JV50P HDTV10A Service Manual

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1. PDP CHARACTERISTICS PDP50X4 (50WXGA PDP MODULE)

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Factory preset timings

Refresh rate 60Hz

Horizontal Frequency 47.7kHz

Vertical Frequency 60Hz

Pixel Rate 85.5MHz

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HDMI CONNECT PIN ASSIGNMENT:

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HDMI Signal (HDMI):

F-Type TV RF connector NTSC system

QAM system (supporting clear QAM)

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AV/Composite Video (CVBS) Connector

Digital audio out

Main Board I/o Connections

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J13 CONNECTION Pin 1 2 Description +5V GND

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AUDIO BD I/O CONNECTIONS OF TV

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EMI BD I/O CONNECTIONS

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