Clocking

Figure by MIT OCW.

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Why Clocks and Storage Elements?

Inputs

Combinational Logic

Outputs

Want to reuse combinational logic from cycle to cycle

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Digital Systems Timing Conventions

All digital systems need a convention about when a receiver can sample an incoming data value
synchronous systems use a common clock asynchronous systems encode data ready signals alongside, or encoded within, data signals synchronous systems, on next clock edge (after hold time) asynchronous systems, acknowledge signal from receiver

Also need convention for when its safe to send another value

Data

Data Ready Acknowledge Asynchronous

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Clock Synchronous
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Large Systems

Most large scale ASICs, and systems built with these ASICs, have several synchronous clock domains connected by asynchronous communication channels
Clock domain 1 Clock domain 2 Clock domain 3

Chip A

Asynch. Chip C channel Clock domain 4

Clock domain 6 Chip B

Clock domain 5

Well focus on a single synchronous clock domain today

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Clocked Storage Elements

Transparent Latch, Level Sensitive

Clock D Q Transparent Latched data passes through when clock high, latched when clock low D Clock Q

D-Type Register or Flip-Flop, Edge-Triggered

Clock D Q

data captured on rising edge of clock, held for rest of cycle D Clock Q

(Can also have latch transparent on clock

low, or negative-edge triggered flip-flop)

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Building a Latch

0 D 1 CLK

Latches are a mux, clock selects either data or output value

Q

CMOS Transmission Gate Latch

CLK

Usually have local inverter to generate CLK Q Optional output buffer

Optional input buffer D D

CLK

CLK
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Parallel N and P transistors act as switch, called a transmission gate

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Static CMOS Latch Variants

Clocked CMOS (C2MOS) feedback inverter

CLK

Weak feedback inverter so input can overpower it

CLK CLK CLK

D
CLK

Can be small, lower clock load, but sizing problematic

CLK

Output buffer shields storage node from downstream logic

Generally the best, fast and energy efficient

Q D
CLK

Has lowest clock load

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Pulldown stack overpowers cross-coupled inverters

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Latch Timing Parameters

Clock D Q TCQmin TCQmax TDQmin TDQmax Tsetup Thold

TCQmin/TCQmax

propagation inout when clock opens latch propagation inout while transparent usually the most important timing parameter for a latch define window around closing clock edge during which data must be steady to be sampled correctly
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TDQmin/TDQmax Tsetup/Thold

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The Setup Time Race

CLK CLK CLK

D
CLK

Setup represents the race for new data to propagate around the feedback loop before clock closes the input gate. (Here, were rooting for the data signal)

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Failing Setup

CLK CLK CLK

D
CLK

If data arrives too close to clock edge, it wont set up the feedback loop before clock closes the input transmission gate.

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The Hold Time Race

CLK CLK CLK

D
CLK

Q Added clock buffers to demonstrate positive hold time on this latch other latch designs naturally have positive hold time

Hold time represents the race for clock to close the input gate before next cycles data disturbs the stored value. (Here were rooting for the clock signal)
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Failing Hold Time

CLK CLK CLK

D
CLK

If data changes too soon after clock edge, clock might not have had time to shut off input gate and new data will corrupt feedback loop.
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Flip-Flops

Can build a flip-flop using two latches back to back

Master Slave
D Q

CLK
Master Transparent Slave Latched Master Latched Master Transparent

Slave Slave Transparent Latched

CLK

On positive edge, master latches input D, slave becomes transparent to pass new D to output Q On negative edge, slave latches current Q, master goes transparent to sample input D again
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Flip-Flop Designs

CLK CLK CLK CLK CLK

CLK

CLK

CLK

D
CLK CLK

Q Q

Can have true or complementary output or both

Transmission-gate master-slave latches most popular in ASICs

robust, convenient timing parameters, energy-efficient

Many other ways to build a flip-flop other than transmission gate master-slave latches
usually trickier timing parameters
only found in high performance custom devices

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Flip-Flop Timing Parameters

Clock D
Q
TCQmin TCQmax Tsetup Thold

TCQmin/TCQmax Tsetup/Thold

propagation inout at clock edge define window around rising clock edge during which data must be steady to be sampled correctly either setup or hold time can be negative

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Single Clock Edge-Triggered Design

TPmin/TPmax Combinational Logic

CLK

Single clock with edge-triggered registers most common design style in ASICs Slow path timing constraint Tcycle TCQmax + TPmax + Tsetup Fast path timing constraint TCQmin + TPmin Thold

can always work around slow path by using slower clock

bad fast path cannot be fixed without redesign! might have to add delay into paths to satisfy hold time
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Clock Distribution

Cant really distribute clock at same instant to all flip-flops on chip

Clock Distribution Variations in trace Network length, metal width and height, coupling caps Difference in clock arrival time is clock skew Local Clock Buffers

Central Clock Driver

Variations in local clock load, local power supply, local gate length and threshold, local temperature
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Clock Grids

One approach for low skew is to use a single metal clock grid across whole chip (Alpha 21064) Low skew but very high power, no clock gating

Clock driver tree spans height of chip. Internal levels shorted

together.

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Grid feeds flops directly, no local buffers

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H-Trees

Recursive pattern to distribute signals uniformly with equal delay over area

Uses much less power than grid, but has more skew In practice, an approximate H-tree is used at the top level (has to route around functional blocks), with local clock buffers driving regions
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Clock Oscillators

Where does the clock signal come from? Simple approach: ring oscillator

Odd number of inverter stages connected in a loop Problem:

What frequency does the ring run at?

Where are the clock edges relative to an external observer?

Free running, no synchronization with external channel

Depends on voltage, temperature, fabrication run,

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Clock Crystals

Fix the clock frequency by using a crystal oscillator Exploit peizo-electric effect in quartz to create highly resonant peak in feedback loop of oscillator Easy to obtain frequency accuracy of ~50 parts per million

Expensive to increase frequency to more than a few 100MHz

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Phase Locked Loops (PLLs)

Use a feedback control loop to force an oscillator to align frequency and phase with an external clock source.

External Clock

Frequency +/Phase Oscillator Comparator Circuit Generated Clock

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Multiplying Frequency with a PLL

By using a clock divider (a simple synchronous circuit) in the feedback loop, can force on-chip oscillator to run at rational multiple of external clock
External Clock

Frequency +/Phase Oscillator Comparator Circuit

Divide by N

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Intel Itanium Clock Distribution

Global Distribution Regional Distribution Local Distribution

GCLK Reference clock CLKP CLKN VCC/2 PLL Main clock DSK DSK

Regional Grid RCD

DSK

RCD

DLCLK OTB

DSK = Active deskew circuits, cancels out systematic skew PLL = Phase locked loop

Figure by MIT OCW.

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Skew Sources and Cures

Systematic skew due to manufacturing variation can be mostly trimmed out with adaptive deskewing circuitry
cross chip skews of <10ps reported

Main sources of remaining skew are temperature changes (low-frequency) and power supply noise (high frequency) Power supply noise affects clock buffer delay and also frequency of PLL

often power for PLL is provided through separate pins clock buffers given large amounts of local on-chip decoupling capacitance

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Skew versus Jitter

Skew is spatial variation in clock arrival times

variation in when the same clock edge is seen by two different flip-flops

Jitter is temporal variation in clock arrival times

variation in when two successive clock edges are

seen by the same flip-flop

Power supply noise is main source of jitter

From now on, use skew as shorthand for untrimmable timing uncertainty

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Timing Revisited

TPmin/TPmax Combinational Logic CLK1 CLK2

Skew eats into timing budget

Slow path timing constraint
Tcyc TCQmax + TPmax + Tsetup+ Tskew Fast path timing constraint TCQmin + TPmin Thold + Tskew
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worst case is when CLK2 is earlier/later than CLK1

worst case is when CLK2 is earlier/later than CLK1

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