Static Timing Analysis - Maharshi

Static Timing Analysis & Synthesis
Maharshi Bhattacharya
© Advanced VLSI Design Laboratory

Dynamic Vs. Static Timing
Analysis
 Dynamic timing analysis is not exhaustive and do not

cover all critical paths .
 Static timing analysis is highly exhaustive and fast.
 STA may include false paths into consideration as
critical path.
 In DTA there is no chance of false path being
interpreted.
 Main Objective in STA is meeting setup and hold
requirements.
Typical Chip Component
Leaf cells
Cells Interco-
Custom nnects
Block
Memory
Control Logic
Optimized core
STA Tool Requirements
 Every block must have a timing model.

 Synthesized logic is represented in terms of basic
cells ( NAND , NOR etc ) and delay information is in
the tech-library.
 Custom blocks are instantiated in the design and
they don’t have any netlist representation. Stamp
Modeling is used for these blocks.
 Interconnects are wires and delay of wires are
calculated from wire-load models.
Latches
Delay = It1
D
-q
clock Delay = It2

q
When Clock = 1 Clock to Q delay when enabled

= It1 + It2
When Clock = 0
So this explains why latch is transparent

Setup and Hold of Flops
D -QM
-Q
clock
Setup Time = 1st stage

Clock = 0 inverter delay ( only one )
Clock = 1 Hold = 2nd stage inverter
delay
Clock –2-q = Switch delay +
2nd stage inverter delay
Understanding clocks
 Clock Sources: Sources can be input

ports or internal pins .
 Period and Waveform: These are
mentioned by create_clock command.
Example :
create_clock clk –period 10 –waveform (
2, 6 }
clk
0 2 6 10 12 16 20
Clock Network
 Clock Uncertainty: Also called the skew.
Flop Flop Flop Flop

clk clka clkb
Uncertainty between two

Clock reaches Clock reaches at Clocks : set_clock_uncertainty
At time T Time T + δt <value> -from clka –to clkb
set_clock_uncertainty 0.1 clk
Clock Network ( cont …)
 Clock Latency:
• Source Latency: Propagation time from
original waveform to the clock definition point
in circuit.
• Network Latency: Propagation time from
clock definition point to the register clock pin.
• Clock latency is specified by
set_clock_latency command.
set_clock_latency –source 2.0 clk
Input and Output delays
Input delay
Clk-to-q delay
A B
Output delay
Output delay = clock latency+ clk-to-q delay + combo delay A + port delay
Input delay = port delay + combo delay B
Input setup time = input delay – intrinsic setup
Total path delay : Output delay + input delay = Td
Input and Output delays
( cont…)
Intrinsic setup
Launch edge Capture edge
Max. Time for logic propagation = Tp
Td <= Tp
Slack = Data Required time – Data arrival time
= Tp – Td >= 0
Note: For the capture edge clock skew will be considered.
Not shown here for simplicity.
Summary of clock definitions
 Commands used for clock definitions

 create_clock
 set_dont_touch_network
 set_clock_latency
 set_clock_uncertainty
 set_input_delay
 set_output_delay
Wire-load Models
 These are statistical data for calculating

interconnect net delays. Parameters
1 Unit Resistance
2.Unit Cap
cap 3. Slope
Delay = resistance*
Different capacitance
Plot for
Wire length
6 8
fan-out
Wire-load models ( cont …)
Wire Load mode selection
Top enclosed segmented

Top level wire-load = w1
Lower
Modules
Wire load
= w2
Wire-Load Models ( Example )
wire_load("R1_3M_AVERAGE") {
resistance : 1;
capacitance : 0.000140 ;
slope : 212 ;
fanout_length(1, 102);
}
Design Rule Constraints
 Maximum Transition: This is the longest

time for a net required for its driving pin to
change logic values.
 In tech-lib this is defined as max_transition.
 In design this value can be defined using
set_max_transition command.
 If there are both constraints defined design
compiler tries to meet the more restrictive
one.
Design Rule Constraints ( cont
…)
 Max Fanout: This is a DRC placed on

every driving pin of cell . This constraint
may be on the entire library or may be
specific to cells. fanout_load is set on
Fanout_load :2 The input pin of each
component
Z
Fanout_load:3
Set_fanout_load:3
Out1
max_fanout:10
Total fanout_load on pin Z >= 2+3+4+3 = 1
Fanout_load:4 set_max_fanout 8 find ( design , deg)
Design Rule Constraints ( cont
…)
 Maximum Capacitance: This is also DRC and allows

to control the capacitance of the nets directly.
 To set the capacitance use set_max_capacitance
command.
 Max transition and max load control the cap values
indirectly and has higher priorities than
max_capacitance .
Timing Exceptions
 FalsePath: These are valid paths which are

not simulated or executed.
1
1
0 0
set_false_path –from –to
SEL
Case Study: Timing Loop
module test ( b , c , out2 ); Loading design 'test'

Information: Timing loop
input b , c ; detected. (OPT-150)
output out2 ;
S_4/B S_4/Z
Warning: Disabling timing
wire out ;
wire out1; arc between pins 'B' and 'Z‘
wire out2 ; on cell 'S_4' to break
a timing loop (OPT-314)
assign out = (b & c );
assign out1 = ~ (out | b ) ;
assign out2 = out1 & c & out2 ;
endmodule
Timing Exceptions
• Multicyle
D Paths Huge Combinational Logic
Clock
set_multicylcle_path -2 –from ff1 –to ff2

Design Flow
STA
DESIGN ENTRY
Primetime
Sdf file
BACK ANNOTATION
SIMULATION
SYNTHESYS
NETLIST SDF
Design Compiler SCRIPT Ready for backend
Back Annotation
 Standard Delay Format ( SDF ) : This is the file

containing delay information on any circuit after
successful timing.
 SDF file contains two types of delay information:
1. Combinational Delays ( Point to Point )

2. Timing Check Delays ( Setup , Hold etc. )
Every Delay information has pattern like
{min:typ:max}
Back Annotation ( Cont …)
(CELL (CELL
(CELLTYPE "INT_FDPC")
(CELLTYPE "INT_NOT")
(INSTANCE out_reg}
(INSTANCE U168) (DELAY
(ABSOLUTE
(DELAY
(IOPATH (posedge CP) Q
(ABSOLUTE (1.954:1.954:1.954) (1.612:1.612:1.6
12))
(IOPATH A Z (0.512:0.512:0.512) (IOPATH (negedge CLR) Q ()
(0.568:0.568:0.568)) (1.112:1.112:1.112))
(IOPATH (negedge PRE) Q
) (2.074:2.074:2.074) ())
) )
)
) )
Example : SDF File
Back Annotation ( Cont …)
 What is Back Annotation ?
 This is the process of verification of the delays those
have been extracted in the sdf.
 Method:
– Open Primetime
– Read in the design netlist setting proper paths
– Read in the sdf.
– Report Annotated delays. ( report_annotated_delay and
report_annotated_check )
• Note: Only internal nets are annotated. Nets connected to ports
are not annotated.
• Write sdf file from primetime.
Stamp Models
Why Required ?
• Modeling timing of custom blocks
Components:
• Model File: This file describes the ports,
modes, and interface timing arcs.
• Data File:This file describes timing data with
respect to the mentioned timing arcs.
Stamp Models
 New Terms ?
 Timing Arcs:
1. Min/Max arcs: Specifies combinational path
directly.
2. Timing Check arcs: Setup/Hold , Clock period ,
clock latency etc.
• Every arc has a label and this label is
referenced in the data file.
Stamp Models ( Cont…)
 Timing Mode: Modes are labels that may

activate some set of timing arcs.
Example MODE: read ( COND : rw =1 )
activate the read timing path and associated
models.
Please See the Primetime Modeling User
Guide for example.
Concluding …
 Do not synthesize any circuit without

constraints.
 Clock is a global constraint.
 Must mention wire-load and operating
conditions.
 Back-Annotation is a must looking into post-
layout simulation.
THANKS

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Static Timing Analysis & Synthesis

© Advanced VLSI Design Laboratory

 Dynamic timing analysis is not exhaustive and do not

 Every block must have a timing model.

clock Delay = It2

When Clock = 1 Clock to Q delay when enabled

So this explains why latch is transparent

Setup Time = 1st stage

 Clock Sources: Sources can be input

 Clock Uncertainty: Also called the skew.

Flop Flop Flop Flop

Uncertainty between two

Launch edge Capture edge

Max. Time for logic propagation = Tp

 Commands used for clock definitions

 These are statistical data for calculating

Top enclosed segmented

 Maximum Transition: This is the longest

 Max Fanout: This is a DRC placed on

 Maximum Capacitance: This is also DRC and allows

 FalsePath: These are valid paths which are

set_false_path –from –to

module test ( b , c , out2 ); Loading design 'test'

set_multicylcle_path -2 –from ff1 –to ff2

 Standard Delay Format ( SDF ) : This is the file

1. Combinational Delays ( Point to Point )

 Timing Mode: Modes are labels that may

 Do not synthesize any circuit without

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