By:

Name: Sri Latha. B

Roll no:10
INTRODUCTION
 Routing congestion is a critical issue in deep submicron design
technology and it becomes one of the most challenging problems in
today's design flow.
 The interconnect has become a critical determiner of circuit
performance in the deep sub-micron regime.
 Circuit placement is starting to play an important role in today’s high
performance chip designs.
 In addition to wire length optimization, the issue of reducing
excessive congestion in local regions such that the router can finish
the routing successfully is becoming another important problem.
To achieve this better performance we need to have a better
design flow.
DESIGN FLOW
DESIGN EXPLORATION
Traditional floorplanning has always been more art than science.

Coming up with a floorplan manually is a relatively interactive and

time- consuming process.

Once the floorplan is done, the design then goes through the
place-and-route process, followed by signoff.
Iterations in a traditional floorplanning flow usually come at the place-
and-route or even signoff stage.
In comparison to a traditional floorplanning approach, design
exploration takes the floorplanning concept, streamlines it using
automatic floorplan synthesis.

Due to the added focus on analysis and refinement, floorplan iterations

can now be performed during the design exploration stage, which is
less expensive time-wise compared to iterations done later in the flow.
VLSI DESIGN
The goal of design exploration is to
answer the following questions:
• Will the design fit into the allocated area?

• What is the optimal die size for the design?

• Is the power plan robust enough to support the power

consumption of the design without causing iR drop or other
power rail issues?

• What does the design timing/area/power look like, at the early

stage where some modules are not ready yet?
 CONGESTION
Finding an optimal area allocation for the design is critical for
any design team.

Allocating too little area for the design leads to congestion

problems.

On the other hand, allocating too much area to the design is a

waste of precious die area
Global Bin Edge
Global Bin

Overflow on each edge =

Routing Demand - Routing Supply
0 (otherwise)


Total Overflow = overflow
all edges
Routing demand = 3
Assume routing supply is 1,
overflow = 3 - 1 = 2 .
CONGESTION OPTIMISATION
Module Description
& Netlist
Routing Estimation

Initial Placement
Congested Region
Identification

Iterative Improvement
Congested Region
Expanding
Congestion Reduction

Congestion Reduction
Valid Coordinates for
each cell
ROUTING ESTIMATION
Bounding Box Routing Estimation.
Based on the probability of having a wire
within a global bin covered by the bounding
box of net K:
bin(0,2)
For each yellow bin, the
Horizontal Routing
Demand of net K is:1/3

Net K Total Horizontal

Routing Demand of
net K :2
bin(0,0) bin(2,0)
INDENTIFYING CONGESTION REGIONS
A global bin is congested if one of its four global edges is
congested.
A maximum number of congested bins in one congested
region is set to prevent forming too large congested
regions.

Neighborhood Bin(i,j)
bins Congested
Reg_3

Congested
Reg_2

Congested
Reg_1
CONGESTED REGION EXPANSION
 For a single congested region, the larger the expansion
area is, the better the optimization result can be obtained
 However, the expansions of multiple congested regions
may lead to new congested regions.

Original Expansion
Congested Area
Region
CONGESTION REDUCTION TECHNIQUES

Congestion
Reduction

Integrated Post-processing
Technique Technique

Quadratic Simulated
Placement Annealing
Congestion
Reduction During
Placement
Partitioning Based
Placement
Why Is Placement Important?
 The circuit delay, power dissipation and area are dominated by the
interconnections.

- Circuit Placement becomes very critical in today’s high performance

VLSI design.

 The first phase in the VLSI design that determines the physical layout
of a chip.

- The quality of the attainable routing is highly determined by the

placement.
 CIRCUIT LAYOUT

Determine the location of D L W

modules. H
Connect the modules inside
L R

E
T
the boundary of a VLSI chip.

O
O
Typical Objectives:
Minimize the chip area
H E L L O
Minimize the interconnect
delay
W O R L D
NET MINIMISATION:

W
V

Z Z
X
X Z

Block Z is rotated to minimize

Y
the area needed to pad X to
the same height.
Blocks X and Z are
highly connected
Both blocks are locked to
prevent later rotation.
Circuit Layout - Partitioning

Task :
Partition circuit into several
sub-circuits.

Objectives :
Make the size of each
component within prescribed ranges
Minimize the number of connections between the
components.
 Block Placement Manner:
1. All non-locked blocks in the
partition are first randomly rotated
—this is the only non-deterministic
part of the physical phase.

Fig A Rows
2. We use mutations to even the row
widths. We need to remove blocks from
the longest row and add blocks to the
shortest row.
Use these four mutations: Grow Row,
Shrink Row, Grow Row by Rotating, and
Shrink Row by Rotating.
Fig B
Rows 3. After each mutation, the
rows are sorted by height,
alternating ascending /
descending, regardless of lock.

Fig c

4. Rows are paired off and squeezed to

create a tight layout. The trapezoids fit
together tightly.
Note: the only sources of white-
space are gaps between the trapezoids
and row unevenness.

Fig D
5. Finally, once all of the partitions have determined their best
individual layouts, they are stacked and the total floorplan is
analyzed and checked for the global best.
This completes one run.
Global Stats
Area: 997
Wire-length: 5874

Best Global Stats

Partitions
better? Area: 1003
Wire-length: 5512

Replace best
global stats and
store coords
Circuit Layout - Placement
In1 In1 In3
In2 1
5 In2 In
1 5 2
In3 4
In4 2 Out1
7 8 7 8 Out1
In5
In6 3
6 In5 3 6 4 In7
In7
4
In8 In8
In6

 Minimize the total estimated wire length of all

the nets.
 Minimize the interconnect congestion.
Standard Cell Layout Style
Feed through
Feature: Standard cell I/O Pads
 Row based layout
 Standard cells Routing
Channel
 Routing channel

Advantages:
 High productivity
 More efficient space
 Well-suited for automated design
COMPARISION
Congestion Comparison Wirelength Comparison

450
2.5E+07
400
350 2.0E+07
300
250 1.5E+07
200
1.0E+07
150
100 5.0E+06
50
0 0.0E+00 Ind1 Prim2 Bio Ind2 Avq.s Avq.l
Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Without congestoin reduction Without congestoin reduction

With-congestion reduction With-congestion reduction

Average Congestion imp: 51%

Average Wire length Increase: 3%
Average CPU Time Increase: 30%
CONCLUSIONS
A post-processing congestion reduction technique is implemented
and incorporated into the flat and hierarchical placement.
A post-processing technique can reduce the congestion of flat
placement largely by 51% on average with a slight increase of wire
length.
For hierarchical congestion-driven placement, it seems to be more
beneficial to incorporate the congestion reduction phase at the flat
level rather than within the levels of hierarchy.
The congestion improvement achieved by performing congestion
optimization at the flat level is 37% on average.