Code For Wap Security
Code For Wap Security
Code For Wap Security
Input Hash
Message Hi=f(Xi) Value
X Add Append Compression
G(Ht)
Padding Message Function Step 9: H((Ko (x) opad) II H((Ko (x) ipad)) II text)
Bits Length f(x)
Fixed opad
Kt
Temp Data 32-bit
Common Bus Interface Unit 5x32-bit Transformed
Control Data 160-bit
Control Unit Last
Figure 3: Proposed System Architecture Transformation
Unit
It is obvious that the HMAC proposed architecture is
Message Digest
built on the SHA-1 hash function that has been adopted 160-bit
by the WAP.
The control unit coordinates all the system operations Figure 4: SHA-1 Unit Architecture
according to an FSM diagram. Like the most of the The Transformed Data Register is used for temporary
system-on-chip designs the proposed HMAC architecture storage of the transformed data, after every
includes a simple common bus interface unit for transformation round is performed. SHA-1 hash function
communication with the external environment. Two specifies 80 common data transformation rounds in total.
internals buses, the address and the data bus of 8 and The SHA-1 Transformation Round is a specified mixed
128-bit respectively, have also been integrated. In logic and mathematic nonlinear transformation function.
addition an XOR block and a concatenation unit have The Last Transformation Unit finally modifies the
also been included in this proposed HMAC architecture. transformed data. This unit consists of 5 modulo adders
The concatenation unit is necessary for all the needed and modulo additions 232 are performed, between the
appending data procedures. Finally, some registers are input data and the five specified constants of 32-bit. In
used, for the appropriate constants, temporary data and this way, the message digest is finally produced. SHA-1
the used key storage reasons. The proposed HMAC sequentially processes 512-bit blocks and computes the
architecture is designed for a specified cryptographic 160-bit message digest. The purpose of Padding Unit is
function (SHA-1) that has been selected by WAP to make the total length of the desirable input data
protocol. Although, with minor modifications and with exactly a multiple of 512-bit. SHA-1 hash function
the addition of some extra registers, in the proposed sequentially process blocks of 512-bit when computing
HMAC architecture, the selected SHA-1 can easily be the message digest. The padded message is generated
replaced with any other hash function. It has been with the following described process: a logic “1”,
estimated that all the appropriate modifications to the followed by m “0”s, followed by a 64-bit integer are
proposed HMAC architecture that have been described appended to the end of the input data to produce a padded
above, would have finally an allocated resources penalty message of length 512*n. The 64-bit integer is equal to
increase at about 5-10 % of the total system covered area. the length of the input data message. A sequence of
The operating frequency of the proposed HMAC constants and some initialized processing data blocks are
architecture it’s time is equal to the frequency of the hash used in this hash function. The WT_Kt Constants
function unit (SHA-1 in our case). Furthermore, detailed Generator Unit supports these constants values.
information of the proposed architecture VLSI
implementation performance will be presented in the next
section 4. 4 VLSI IMPLEMENTATION RESULTS