AD9650
AD9650
AD9650
AD9650
FUNCTIONAL BLOCK DIAGRAM
DRVDD SPI
AD9650
16
Industrial instrumentation X-Ray, MRI, and ultrasound equipment High speed pulse acquisition Chemical and spectrum analysis Direct conversion receivers Multimode digital receivers Smart antenna systems General-purpose software radios
Figure 1.
Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9650 is available in a 64-lead LFCSP and is specified over the industrial temperature range of 40C to +85C.
GENERAL DESCRIPTION
The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data can be routed directly to the two external 16-bit output ports or multiplexed on a single 16-bit bus. These outputs can be set to either 1.8 V CMOS or LVDS.
PRODUCT HIGHLIGHTS
1. 2. 3. On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and test modes. Pin compatible with the AD9268 and other dual families, AD9269, AD9251, AD9231, and AD9204. This allows a simple migration across resolutions and bandwidth.
4.
5.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved.
08919-001
APPLICATIONS
PDWN OEB AGND SYNC NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES.
Data Sheet
ADC Architecture ...................................................................... 29 Analog Input Considerations ................................................... 29 Voltage Reference ....................................................................... 32 Channel/Chip Synchronization ................................................ 34 Power Dissipation and Standby Mode .................................... 34 Digital Outputs ........................................................................... 35 Timing ......................................................................................... 35 Built-In Self-Test (BIST) and Output Test .................................. 36 Built-In Self-Test (BIST) ............................................................ 36 Output Test Modes ..................................................................... 36 Serial Port Interface (SPI) .............................................................. 37 Configuration Using the SPI ..................................................... 37 Hardware Interface..................................................................... 38 Configuration Without the SPI ................................................ 38 SPI Accessible Features .............................................................. 38 Memory Map .................................................................................. 39 Reading the Memory Map Register Table............................... 39 Memory Map Register Table ..................................................... 40 Memory Map Register Descriptions ........................................ 42 Applications Information .............................................................. 43 Design Guidelines ...................................................................... 43 Outline Dimensions ....................................................................... 44 Ordering Guide .......................................................................... 44
REVISION HISTORY
1/11Rev. 0 to Rev. A Changes to Table 17 ........................................................................ 40 7/10Revision 0: Initial Version
Rev. A | Page 2 of 44
AD9650
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.35 V internal reference, DCS disabled, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1.35 V Mode) Load Regulation at 1.0 mA INPUT REFERRED NOISE VREF = 1.35 V ANALOG INPUT Input Span, VREF = 1.35 V Input Capacitance 2 Input Common-Mode Voltage REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD1 (1.8 V CMOS) IDRVDD1 (1.8 V LVDS) POWER CONSUMPTION DC Input Sine Wave Input1 (DRVDD = 1.8 V CMOS Output Mode) Sine Wave Input1 (DRVDD = 1.8 V LVDS Output Mode) Standby Power 3 Power-Down Power
1 2
Temp Full Full Full Full Full 25C Full 25C Full Full Full Full Full Full 25C
AD9650BCPZ-25 Min Typ Max 16 Guaranteed 0.2 0.5 0.4 2.5 1 +1.3 0.7 3 1.6 0.1 0.5 2 15 7 10 1.5 14 0.4 1.3
AD9650BCPZ-65 Min Typ Max 16 Guaranteed 0.2 0.5 0.4 2.5 1 +1.3 0.7 5 2.5 0.1 0.5 2 15 7 10 1.5 14 0.4 1.3
AD9650BCPZ-80 Min Typ Max 16 Guaranteed 0.4 0.70 0.4 2.5 +1.3 0.7 6 2.5 0.1 0.5 2 15 7 10 1.5 14 0.4 1.3
AD9650BCPZ-105 Min Typ Max 16 Guaranteed 0.4 0.7 0.4 2.5 1 +1.3 0.7 6 3 0.1 0.5 2 15 7 10 1.5 14 0.4 1.3
Unit Bits
% FSR % FSR LSB LSB LSB LSB % FSR % FSR ppm/C ppm/C mV mV LSB rms V p-p pF V k
2.7 11 0.9 6
2.7 11 0.9 6
2.7 11 0.9 6
2.7 11 0.9 6
Full Full Full Full Full Full Full Full Full Full
1.7 1.7
1.7 1.7
1.7 1.7
1.7 1.7
V V mA mA mA
254
408
537
675
mW mW mW mW mW
2.5
2.5
2.5
2.5
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK+ and CLK pins inactive (set to AVDD or AGND).
Rev. A | Page 3 of 44
AD9650
ADC AC SPECIFICATIONS
Data Sheet
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.35 V internal reference, DCS disabled, unless otherwise noted. Table 2.
Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30 MHz fIN = 70 MHz fIN = 141 MHz 2 SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30 MHz fIN = 70 MHz fIN = 141 MHz2 EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30 MHz fIN = 70 MHz fIN = 141 MHz2 WORST SECOND OR THIRD HARMONIC fIN =9.7 MHz fIN = 30 MHz fIN = 70 MHz fIN = 141 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30 MHz fIN = 70 MHz fIN = 141 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz fIN = 30 MHz fIN = 70 MHz fIN = 141 MHz TWO-TONE SFDR fIN = 7.2 MHz (7 dBFS ), 8.4 MHz (7 dBFS) fIN = 25 MHz (7 dBFS ), 30 MHz (7 dBFS) fIN = 125 MHz (7 dBFS ), 128 MHz (7 dBFS) CROSSTALK 3 ANALOG INPUT BANDWIDTH
1 2 3
25C 25C Full 25C 25C 25C 25C 25C 25C 25C 25C Full 25C 25C 25C 25C Full 25C 25C 25C 25C Full 25C 25C 25C 25C 25C Full 25C
82.2 80 81.5 78 81
82 81.2 80.7 79.2 75 13.5 13.2 13.0 12.9 94 93 91.5 88 86 79 94 93 88 87 86 79 105 105 97 97 97 97
82 82 80 78.5 75.1 13.5 13.2 13.0 13.0 95.5 92 87 86 79 95.5 92 87 86 79 105 105 97 97 97
dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
95 85 87
95 85 91.5 87
110 102 97
87 84 90 83 105 500 105 500 87 83 105 500 87 84 105 500 dBc dBc dBFS MHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Measurements made with a divide-by-4 clock rate to minimize the effects of clock jitter on the SNR performance. Crosstalk is measured with a 170 MHz tone at 1 dBFS on one channel and no input on the alternate channel.
Rev. A | Page 4 of 44
Data Sheet
DIGITAL SPECIFICATIONS
AD9650
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled, unless otherwise noted. Table 3.
Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT/OUTPUT (SDIO/DCS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (OEB, PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance Temperature Min Typ CMOS/LVDS/LVPECL 0.9 0.3 AGND 0.9 100 100 8 9 10 CMOS 0.9 AGND 1.2 AGND 100 100 12 1.22 0 10 40 26 2 1.22 0 92 10 26 2 1.22 0 10 38 26 5 1.22 0 90 10 26 5 2.1 0.6 134 +10 2.1 0.6 +10 128 2.1 0.6 135 +10 1 16 AVDD AVDD 0.6 +100 +100 20 2.1 0.6 +10 132 3.6 AVDD 1.4 +100 +100 12 Max Unit
V V p-p V V A A pF k
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
V V V V A A pF k V V A A k pF V V A A k pF V V A A k pF V V A A k pF
Rev. A | Page 5 of 44
AD9650
Parameter DIGITAL OUTPUTS CMOS ModeDRVDD = 1.8 V High Level Output Voltage IOH = 50 A IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 A LVDS ModeDRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode
1 2
Data Sheet
Temperature Min Typ Max Unit
1.79 1.75 0.2 0.05 290 1.15 160 1.15 345 1.25 200 1.25 400 1.35 230 1.35
V V V V mV V mV V
Rev. A | Page 6 of 44
Data Sheet
SWITCHING SPECIFICATIONS
AD9650
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled, unless otherwise noted. Table 4.
Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 DCS Enabled DCS Disabled CLK PeriodDivide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode Through Divide-by-8 Mode Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) 2 DCO to Data Skew (tSKEW) LVDS Mode Data Propagation Delay (tPD) DCO Propagation Delay (tDCO)2 DCO to Data Skew (tSKEW) CMOS Mode Pipeline Delay (Latency) LVDS Mode Pipeline Delay (Latency) Channel A/ Channel B Wake-Up Time 3 Out-of-Range Recovery Time
1 2
12 19 0.8
20 20
28 21
7.70 7.70
10.75 8.07
6.25 6.25
8.75 6.55
4.75 4.75
6.65 5.0
ns ns ns
Full Full
1.0 0.100
1.0 0.090
1.0 0.080
1.0 0.075
ns ps rms
2.8
3.5 3.1
4.2
2.8
3.5 3.1
4.2
2.8
3.5 3.1
4.2
2.8
3.5 3.1
4.2
ns ns
0.6 2.9
0 4.5
0.6 2.9
0 4.5
0.6 2.9
0 4.5
0.6 2.9
0 4.5
ns ns ns
0.1
+0.2 12 12/12.5
+0.5
0.1
+0.2 12 12/12.5
+0.5
0.1
+0.2 12 12/12.5
+0.5
0.1
+0.2 12 12/12.5
+0.5
ns Cycles Cycles
Full Full
500 2
500 2
500 2
500 2
s Cycles
Conversion rate is the clock rate after the divider. Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. A | Page 7 of 44
AD9650
TIMING SPECIFICATIONS
Table 5.
Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS 1 tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO
1
Data Sheet
Conditions SYNC to rising edge of CLK+ setup time SYNC to rising edge of CLK+ hold time Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge
Unit ns typ ns typ ns min ns min ns min ns min ns min ns min ns min ns min ns min
Timing Diagrams
N1 N VIN N+1 N+2
tA
N+3
N+4 N+5
tCH
CLK+ CLK
tCLK
tDCO
DCOA/DCOB
tSKEW
08919-002 08919-003
CH A/CH B DATA
N 13
N 12
N 11
N 10
N9
N8
tPD
N1 N VIN
tA
N+3 N+1
N+4 N+5
N+2
tCH
CLK+ CLK
tCLK
tDCO
DCOA/DCOB
tSKEW tPD
CH A/CH B DATA CH A CH B CH A CH B CH A CH B N 12 N 12 N 11 N 11 N 10 N 10 CH A N9 CH B N9 CH A N8
Rev. A | Page 8 of 44
Data Sheet
N1 N VIN N+1 N+2
AD9650
tA
N+3 N+4 N+5
tCH
CLK+ CLK
tCLK
tDCO
DCOA/DCOB
tSKEW
CH A/CH B DATA CH A CH B CH A CH B CH A CH B N 12 N 12 N 11 N 11 N 10 N 10 CH A N9 CH B N9 CH A N8
08919-003
tPD
CLK+
tSSYNC
SYNC
tHSYNC
08919-004
Rev. A | Page 9 of 44
Data Sheet
THERMAL CHARACTERISTICS
Rating 0.3 V to +2.0 V 0.3 V to +2.0 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 40C to +85C 150C 65C to +150C
The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package. Typical JA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces JA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces JA. Table 7. Thermal Resistance
Package Type 64-Lead LFCSP (CP-64-6)
1 2
JC1, 3 1.0
JB1, 4 9.2
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-STD 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).
ESD CAUTION
The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) + 0.2 V but should not exceed 2.1 V.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. A | Page 10 of 44
AD9650
CLK+ CLK SYNC D0B D1B D2B D3B D4B D5B DRVDD D6B D7B D8B D9B D10B D11B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD9650
PARALLEL CMOS TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D15A D14A D13A D12A D11A DRVDD D10A D9A D8A D7A
VIN+A VINA VIN+B VINB VREF SENSE RBIAS VCM CLK+ CLK SYNC D0A D1A D2A D3A D4A D5A D6A
Input Input Input Input Input/output Input Input/output Output Input Input Input Output Output Output Output Output Output Output
08919-005
NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
D12B D13B DRVDD D14B D15B ORB DCOB DCOA D0A D1A D2A DRVDD D3A D4A D5A D6A
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD9650
Pin No. 33 34 35 36 38 39 40 41 42 43 4 5 6 7 8 9 11 12 13 14 15 16 17 18 20 21 22 24 23 SPI Control 45 44 46 ADC Configuration 47 48 Mnemonic D7A D8A D9A D10A D11A D12A D13A D14A D15A ORA D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B D10B D11B D12B D13B D14B D15B ORB DCOA DCOB SCLK/DFS SDIO/DCS CSB OEB PDWN Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/output Input Input Input Description Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data (MSB). Channel A Overrange Output. Channel B CMOS Output Data (LSB). Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data (MSB). Channel B Overrange Output Channel A Data Clock Output. Channel B Data Clock Output.
Data Sheet
SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Output Enable Input (Active Low) in External Pin Mode. Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.
Rev. A | Page 12 of 44
Data Sheet
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VINB AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VINA VIN+A AVDD AVDD
AD9650
CLK+ CLK SYNC D0 D0+ D1 D1+ D2 D2+ DRVDD D3 D3+ D4 D4+ D5 D5+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD9650
PARALLEL LVDS TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR D15+ D15 D14+ D14 DRVDD D13+ D13 D12+ D12
VIN+A VINA VIN+B VINB VREF SENSE RBIAS VCM CLK+ CLK SYNC D0+ D0 D1+ D1 D2+ D2 D3+
Input Input Input Input Input/output Input Input/output Output Input Input Input Output Output Output Output Output Output Output
Rev. A | Page 13 of 44
08919-006
NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
D6 D6+ DRVDD D7 D7+ D8 D8+ DCO DCO+ D9 D9+ DRVDD D10 D10+ D11 D11+
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD9650
Pin No. 11 14 13 16 15 18 17 21 20 23 22 27 26 30 29 32 31 34 33 36 35 39 38 41 40 43 42 25 24 SPI Control 45 44 46 ADC Configuration 47 48 Mnemonic D3 D4+ D4 D5+ D5 D6+ D6 D7+ D7 D8+ D8 D9+ D9 D10+ D10 D11+ D11 D12+ D12 D13+ D13 D14+ D14 D15+ D15 OR+ OR DCO+ DCO SCLK/DFS SDIO/DCS CSB OEB PDWN Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/output Input Input Input
Data Sheet
Description Channel A/Channel B LVDS Output Data 3Complement. Channel A/Channel B LVDS Output Data 4True. Channel A/Channel B LVDS Output Data 4Complement. Channel A/Channel B LVDS Output Data 5True. Channel A/Channel B LVDS Output Data 5Complement. Channel A/Channel B LVDS Output Data 6True. Channel A/Channel B LVDS Output Data 6Complement. Channel A/Channel B LVDS Output Data 7True. Channel A/Channel B LVDS Output Data 7Complement. Channel A/Channel B LVDS Output Data 8True. Channel A/Channel B LVDS Output Data 8Complement. Channel A/Channel B LVDS Output Data 9True. Channel A/Channel B LVDS Output Data 9Complement. Channel A/Channel B LVDS Output Data 10True. Channel A/Channel B LVDS Output Data 10Complement. Channel A/Channel B LVDS Output Data 11True. Channel A/Channel B LVDS Output Data 11Complement. Channel A/Channel B LVDS Output Data 12True. Channel A/Channel B LVDS Output Data 12Complement. Channel A/Channel B LVDS Output Data 13True. Channel A/Channel B LVDS Output Data 13Complement. Channel A/Channel B LVDS Output Data 14True. Channel A/Channel B LVDS Output Data 14Complement. Channel A/Channel B LVDS Output Data 15True (MSB). Channel A/Channel B LVDS Output Data 15Complement (MSB). Channel A/Channel B LVDS Overrange OutputTrue. Channel A/Channel B LVDS Overrange OutputComplement. Channel A/Channel B LVDS Data Clock OutputTrue. Channel A/Channel B LVDS Data Clock OutputComplement. SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Output Enable Input (Active Low) in External Pin Mode. Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.
Rev. A | Page 14 of 44
AD9650
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS disabled, 1.35 V internal reference, 2.7 V p-p differential input, VIN = 1.0 dBFS, and 32k sample, TA = 25C, unless otherwise noted.
AD9650-25
0 20 40 60 80 100 120 140 0 2 4 6 8 10 12 FREQUENCY (MHz) 25MSPS 9.7MHz @ 1dBFS SNR = 82.4dB (83.4dBFS) SFDR = 95.8dBc 25MSPS 9.7MHz @ 6dBFS 20 SNR = 77.9dB (83.9dBFS) SFDR = 99dBc 0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
08919-108
Figure 11. AD9650-25 Single-Tone FFT with fIN = 9.7 MHz at 6 dBFS with Dither Disabled
25MSPS 9.7MHz @ 6dBFS 20 SNR = 77.4dB (83.4dBFS) SFDR = 101.3dBc 0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
08919-109
Figure 12. AD9650-25 Single-Tone FFT with fIN = 9.7 MHz at 6 dBFS with Dither Enabled
120 SFDR (dBFS) 100 SNR (dBFS) 80
AMPLITUDE (dBFS)
SNR/SFDR
60 SFDR (dBc) 40
20 SNR (dB)
08919-110
08919-113
0 100
90
80
70
60
50
40
30
20
10
Figure 13. AD9650-25 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Rev. A | Page 15 of 44
08919-112
08919-111
AD9650
120 SFDR (dBFS) DITHER ON 115
1200000 1400000
Data Sheet
110
SNR/SFDR (dBFS)
100 95 90
NUMBER OF HITS
105
200000 0
N+7
N+6
N+5
N+4
N+3
N+2
N+1
N1
N2
N3
N4
N5
N6
OUTPUT CODE
Figure 14. AD9650-25 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz with and Without Dither Enabled
100 95 90 85 60 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) SNR (40C) SNR (+25C) SNR (+85C) SFDR (40C) SFDR (+25C) SFDR (+85C) 40 SNR 20 120
100
SFDR
80
SNR (dBFS)
SFDR (dBc)
08919-115
10000
20000
30000
40000
50000
60000
OUTPUT CODE
Figure 15. AD9650-25 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 2.7 V p-p Full Scale
105
100
95 SFDR (dBc) 90
85 SNR (dBFS) 80
08919-216
15
20
25
30
35
40
45
50
10000
20000
30000
40000
50000
60000
OUTPUT CODE
Figure 16. AD9650-25 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 9.7 MHz
Rev. A | Page 16 of 44
08919-120
75 10
2.0
08919-119
0 300
08919-118
90
80
70
60
50
40
30
20
10
08919-114
N7
70 100
Data Sheet
450
AD9650
400 350 300 250 200 150 100 50 0 10 LVDS AND CMOS IAVDD (mA) TOTAL POWER LVDS (mW)
Rev. A | Page 17 of 44
AD9650
AD9650-65
0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 FREQUENCY (MHz) 65MSPS 9.7MHz @ 1dBFS SNR = 82.1dB (83.1dBFS) SFDR = 98.7dBc 0 20 40 60 80 100 120 140 0 5 10 15 20
Data Sheet
65MSPS 141MHz @ 1dBFS SNR = 78.5dB (79.5dBFS) SFDR = 79.2dBc
AMPLITUDE (dBFS)
08919-122
AMPLITUDE (dBFS)
25
30
FREQUENCY (MHz)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
08919-123
Figure 25. AD9650-65 Single-Tone FFT with fIN = 30.3 MHz at 6 dBFS with Dither Disabled
0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 FREQUENCY (MHz) 65MSPS 30.3MHz @ 6dBFS SNR = 76.9dB (82.9dBFS) SFDR = 100dBc
AMPLITUDE (dBFS)
08919-124
AMPLITUDE (dBFS)
20
25
30
FREQUENCY (MHz)
Figure 26. AD9650-65 Single-Tone FFT with fIN = 30.3 MHz @ 6 dBFS with Dither Enabled
Rev. A | Page 18 of 44
08919-127
08919-126
08919-125
Data Sheet
120 SFDR (dBFS) 100
SNR (dBFS), SFDR (dBc)
100 105
AD9650
SNR (dBFS) 80
95 SFDR 90
SNR/SFDR
85 SNR 80
20
08919-128
90
80
70
60
50
40
30
20
10
50
55
60
65
70
75
80
85
Figure 27. AD9650-65 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN =30.3 MHz
120 SFDR (dBFS) DITHER ON 115 110
Figure 30. AD9650-65 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 30 MHz
1400000 1200000 1000000
NUMBER OF HITS
SNR/SFDR (dBFS)
105 100 95 90 85 80 75 SNR (dBFS) DITHER OFF SNR (dBFS) DITHER ON SFDR (dBFS) DITHER OFF
N+7
N+6
N+5
N+4
N+3
N+2
N+1
N1
N2
N3
N4
N5
N6
OUTPUT CODE
Figure 28. AD9650-65 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30.3 MHz with and Without Dither Enabled
100 95 90 100 90 SFDR
4 6
80
INL ERROR (LSB)
70
SNR (dBFS)
85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) SNR (40C) SFDR (40C) SNR (+25C) SFDR (+25C) SNR (+85C) SFDR (+85C)
SFDR (dBc)
60 50 40 SNR 30 20 10
08919-130
10000
20000
30000
40000
50000
60000
OUTPUT CODE
Figure 29. AD9650-65 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 2.7 V p-p Full Scale
Rev. A | Page 19 of 44
08919-134
0 300
08919-133
90
80
70
60
50
40
30
20
10
08919-129
N7
70 100
08919-230
0 100
75 45
AD9650
2.0
TOTAL POWER (mW)/CURRENT (mA)
Data Sheet
700 600 500 400 300 LVDS AND CMOS IAVDD (mA) 200 CMOS IDRVDD (mA) 100 0 25 LVDS IDRVDD (mA) TOTAL POWER LVDS (mW)
1.5 1.0
10000
20000
30000
40000
50000
60000
35
45
55
65
75
85
95
105
OUTPUT CODE
Rev. A | Page 20 of 44
08919-234
2.0
Data Sheet
AD9650-80
0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 80MSPS 9.7MHz @ 1dBFS SNR = 82.2dB (83.2dBFS) SFDR = 95.8dBc
AD9650
0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 80MSPS 141MHz @ 1dBFS SNR = 79.3dB (80.3dBFS) SFDR = 79.2dBc
AMPLITUDE (dBFS)
08919-137
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
08919-138
AMPLITUDE (dBFS)
Figure 39. AD9650-80 Single-Tone FFT with fIN = 30.3 MHz at 6 dBFS with Dither Disabled
0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 80MSPS 30.3MHz @ 6dBFS SNR = 77dB (83dBFS) SFDR = 98.4dBc
AMPLITUDE (dBFS)
08919-139
AMPLITUDE (dBFS)
Figure 40. AD9650-80 Single-Tone FFT with fIN = 30.3 MHz at 6 dBFS with Dither Enabled
Rev. A | Page 21 of 44
08919-142
08919-141
08919-140
AD9650
120 SFDR (dBFS) 100
SNR (dBFS), SFDR (dBc)
Data Sheet
105
100
SNR (dBFS) 80
95 SFDR 90
SNR/SFDR
85 SNR
20
80
08919-143
90
80
70
60
50
40
30
20
10
65
70
75
80
85
90
95
100
Figure 41. AD9650-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30.3 MHz
120 SFDR (dBFS) DITHER ON 100
Figure 44. AD9650-80 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 30 MHz
1400000 1200000 1000000
SNR/SFDR (dBFS)
NUMBER OF HITS
40
20
N+7
N+6
N+5
N+4
N+3
N+2
N+1
N1
N2
N3
N4
N5
N6
OUTPUT CODE
Figure 42. AD9650-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30.3 MHz with and Without Dither Enabled
100 95 90 80 85 60 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) SNR (40C) SFDR (40C) SNR (+25C) SFDR (+25C) SNR (+85C) SFDR (+85C) SNR 40
INL ERROR (LSB)
120
100
SFDR
SNR (dBFS)
SFDR (dBc)
20
08919-145
10000
20000
30000
40000
50000
60000
OUTPUT CODE
Rev. A | Page 22 of 44
08919-149
0 300
08919-148
90
80
70
60
50
40
30
20
10
08919-144
N7
0 100
08919-146
0 100
75 60
Data Sheet
2.0
AD9650
800
TOTAL POWER (mW)/CURRENT (mA)
1.5 1.0
DNL ERROR (LSB)
700 600 500 400 LVDS AND CMOS IAVDD (mA) 300 200 CMOS IDRVDD (mA) 100 0 25 LVDS IDRVDD (mA) TOTAL POWER CMOS (mW)
10000
20000
30000
40000
50000
60000
35
45
55
65
75
85
95
105
115
125
OUTPUT CODE
Rev. A | Page 23 of 44
08919-248
2.0
AD9650
AD9650-105
0 20 40 60 80 100 120 140 0 10 20 30 40 50 FREQUENCY (MHz) 105MSPS 9.7MHz @ 1dBFS SNR = 81.7dB (82.7dBFS) SFDR = 90.7dBc 0 20 40 60 80 100 120 140 0 10 20 30 105MSPS 141MHz @ 1dBFS SNR = 79dB (80dBFS) SFDR = 81.1dBc
Data Sheet
AMPLITUDE (dBFS)
08919-152
AMPLITUDE (dBFS)
40
50
FREQUENCY (MHz)
AMPLITUDE (dBFS)
08919-153
AMPLITUDE (dBFS)
Figure 53. AD9650-105 Single-Tone FFT with fIN = 30.3 MHz @ 6 dBFS with Dither Disabled
0 20 40 60 80 100 120 140 0 10 20 30 40 50 FREQUENCY (MHz) 105MSPS 30.3MHz @ 6dBFS SNR = 75.7dB (81.7dBFS) SFDR = 96.2dBc
AMPLITUDE (dBFS)
08919-154
AMPLITUDE (dBFS)
10
20
30
40
50
FREQUENCY (MHz)
Figure 54. AD9650-105 Single-Tone FFT with fIN = 30.3 MHz @ 6 dBFS with Dither Enabled
Rev. A | Page 24 of 44
08919-157
08919-156
08919-155
Data Sheet
120 SFDR (dBFS) 100
SNR (dBFS), SFDR (dBc)
100 105
AD9650
SNR (dBFS) 80
95 SFDR 90
SNR/SFDR
85
SNR
20
80
08919-158
90
80
70
60
50
40
30
20
10
90
95
100
105
110
115
120
125
Figure 55. AD9650-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30.3 MHz
120 115 110 SFDR (dBFS) DITHER ON
Figure 58. AD9650-105 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 30 MHz
0 20 40 60 80 100 120 140 105MSPS 30.8MHz @ 7dBFS 25.4MHz @ 7dBFS SFDR = 86.6dBc (93.6dBFS)
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
70 100
90
80
70
60
50
40
30
20
10
10
20
30
40
50
FREQUENCY (MHz)
Figure 56. AD9650-105 Single Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30.3 MHz with and Without Dither Enabled
100 95 SFDR 90
SNR (dBFS)
Figure 59. AD9650-105 Two-Tone FFT with fIN1 = 25.4 MHz and fIN2 = 30.8 MHz
0 20 SFDR (dBc) 40
100 90 80 70
SFDR (dBc)
85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) SNR (40C) SFDR (40C) SNR (+25C) SFDR (+25C) SNR (+85C) SFDR (+85C)
60 50 40 30 SNR 20
SFDR/IMD3
10
08919-160
IMD3 (dBFS) 80 70 60 50 40 30 20 10
08919-163
0 300
140 90
Figure 60. AD9650-105 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 25.4 MHz, fIN2 = 30.8 MHz, fS = 105 MSPS
Rev. A | Page 25 of 44
08919-162
08919-258
0 100
75 85
AD9650
0 20 40 60 80 100 120 140 0 10 20 30 40 50 FREQUENCY (MHz)
200000
NUMBER OF HITS
Data Sheet
105MSPS 124.8MHz @ 7dBFS 128.3MHz @ 7dBFS SFDR = 83.8dBc
1200000
1000000
AMPLITUDE (dBFS)
800000
600000
400000
08919-164
N+8
N+7
N+6
N+5
N+4
N+3
N+2
N+1
N1
N2
N3
N4
N5
N6
N7
N8
08919-170
OUTPUT CODE
Figure 61. AD9650-105 Two-Tone FFT with fIN1 = 124.8 MHz and fIN2 = 128.3 MHz
0 20 SFDR (dBc) 40
SFDR/IMD3
80
70
60
50
40
30
20
10
10000
20000
30000
40000
50000
60000
OUTPUT CODE
Figure 62. AD9650-105 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 128.3 MHz, fIN2 = 124.8 MHz, fs = 105 MSPS
900 TOTAL POWER LVDS (mW)
TOTAL POWER (mW)/CURRENT (mA)
2.0 1.5 1.0
DNL ERROR (LSB)
800 TOTAL POWER CMOS (mW) 700 600 500 400 300 200 CMOS IDRVDD (mA) 100
08919-263
1.5 2.0
0 25
45
65
85
105
125
145
10000
20000
30000
40000
50000
60000
OUTPUT CODE
Rev. A | Page 26 of 44
08919-169
140 90
08919-168
Data Sheet
100 TYPICAL VCM
AD9650
SNR (dBFS)
90
SFDR (dBc)
80
SNR/SFDR
70
60
50
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
Figure 67. SNR/SFDR vs. Input Common Mode (VCM) with fIN = 30.3 MHz
Rev. A | Page 27 of 44
08919-171
40 0.80
Data Sheet
SENSE
350
08919-007
DRVDD
26k
08919-012
08919-008
DRVDD
AVDD
PAD
VREF 6k
08919-009
SCLK/DFS OR OEB
350 26k
08919-011
Rev. A | Page 28 of 44
08919-014
08919-013
AD9650
A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, Transformer-Coupled Front-End for Wideband A/D Converters, for more information on this subject (visit www.analog.com).
BIAS S CS VIN+x CPAR1 CPAR2 H CS VINx
08919-034
ADC ARCHITECTURE
The AD9650 architecture consists of a dual front-end sampleand-hold circuit, followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state.
S CFB
CPAR1 S
CPAR2 BIAS
CFB
For best dynamic performance, the source impedances driving VIN+x and VINx should be matched, and the inputs should be differentially balanced. An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The span of the ADC core is set by this buffer to 2 VREF.
Rev. A | Page 29 of 44
AD9650
Common-Mode Voltage Servo
In applications where there may be a voltage loss between the VCM output of the AD9650 and the analog inputs, the common-mode voltage servo can be enabled. When the inputs are ac-coupled and a resistance of >100 is placed between the VCM output and the analog inputs, a significant voltage drop can occur and the common-mode voltage servo should be enabled. Setting Bit 0 in Register 0x0F to a logic high enables the VCM servo mode. In this mode, the AD9650 monitors the common-mode input level at the analog inputs and adjusts the VCM output level to keep the common-mode input voltage at an optimal level. If both channels are operational, Channel A is monitored. However, if Channel A is in power-down or standby mode, the Channel B input is monitored.
Data Sheet
typically at very low levels and do not limit SFDR when the ADC is quantizing large-signal inputs, dithering converts these tones to noise and produces a whiter noise floor.
Small-Signal FFT
For small-signal inputs, the front-end sampling circuit typically contributes very little distortion, and, therefore, the SFDR is likely to be limited by tones caused by DNL errors due to random component mismatches. Therefore, for small-signal inputs (typically, those below 6 dBFS), dithering can significantly improve SFDR by converting these DNL tones to white noise.
Static Linearity
Dithering also removes sharp local discontinuities in the INL transfer function of the ADC and reduces the overall peak-topeak INL. In receiver applications, utilizing dither helps to reduce DNL errors that cause small-signal gain errors. Often this issue is overcome by setting the input noise 5 dB to 10 dB above the converter noise. By using dither within the converter to correct the DNL errors, the input noise requirement can be reduced.
Dither
The AD9650 has an optional dither mode that can be selected for one or both channels. Dithering is the act of injecting a known but random amount of white noise, commonly referred to as dither, into the input of the ADC. Dithering has the effect of improving the local linearity at various points along the ADC transfer function. Dithering can significantly improve the SFDR when quantizing small-signal inputs, typically when the input level is below 6 dBFS. As shown in Figure 78, the dither that is added to the input of the ADC through the dither DAC is precisely subtracted out digitally to minimize SNR degradation. When dithering is enabled, the dither DAC is driven by a pseudorandom number generator (PN gen). In the AD9650, the dither DAC is precisely calibrated to result in only a very small degradation in SNR and SINAD.
AD9650
VIN ADC CORE DOUT
ADA4938-2
DITHER DAC
AD9650
15 VIN+x VCM
08919-035
0.1F 120
08919-058
33 200 15pF
PN GEN
DITHER ENABLE
Large-Signal FFT In most cases, dithering does not improve SFDR for large-signal inputs close to full scale, for example, with a 1 dBFS input. For large-signal inputs, the SFDR is typically limited by front-end sampling distortion, which dithering cannot improve. However, even for such large-signal inputs, dithering may be useful for certain applications because it makes the noise floor whiter. As is common in pipeline ADCs, the AD9650 contains small DNL errors caused by random component mismatches that produce spurs or tones that make the noise floor somewhat randomly colored part-to-part. Although these tones are
For baseband applications in which SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 80. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer.
C2 R2 R1 2V p-p 49.9 C1 R1 R2 VINx VIN+x
AD9650
VCM
08919-036
0.1F
C2
Data Sheet
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9650. For applications in which SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 81). In this configuration, the input is ac-coupled, and the CML is provided to each input through a 33 resistor. These resistors compensate for losses in the input baluns to provide a 50 impedance to the driver. In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 10 displays recommended values to set the RC network. At higher input frequencies, good performance can be
0.1F 2V p-p PA S S P 0.1F 33 0.1F R1 R2 VINx C2 0.1F 33 C1
AD9650
achieved by using a ferrite bead in series with a resistor and removing the capacitors. However, these values are dependent on the input signal and should be used only as a starting guide. Table 10. Example RC Network
Frequency Range (MHz) 0 to 100 100 to 200 100 to 300
1
R2 Series ( Each) 15 10 66
An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 82. See the AD8352 data sheet for more information.
C2 R1 R2 VIN+x
AD9650
VCM
08919-038
VCC 0.1F ANALOG INPUT 0 16 1 2 CD RD RG 3 4 ANALOG INPUT 5 0.1F 0 14 0.1F 0.1F 8, 13 11 0.1F R 200 VIN+x C 0.1F 200 R
0.1F
AD8352
10
AD9650
VINx VCM
08919-039
Rev. A | Page 31 of 44
AD9650
VOLTAGE REFERENCE
REFERENCE VOLTAGE ERROR (%)
0
Data Sheet
0.5
The AD9650 can be configured for a stable 1.35 V internal reference or a user-applied external reference. The input range of the ADC always equals twice the voltage at the reference pin (VREF) for either an internal or an external reference. Table 11 shows a summary of the internal and external reference connections.
1.0
1.5
2.0
2.5
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ADC CORE
AD9650
Figure 83. Internal Reference Configuration
If the internal reference of the AD9650 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 84 shows how the internal reference voltage is affected by loading.
30
10
10
30
50
70
90
TEMPERATURE (C)
Rev. A | Page 32 of 44
08919-189
6 50
08919-188
3.0
Data Sheet
Clock Input Considerations
For optimum performance, the AD9650 sample clock inputs, CLK+ and CLK, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK pins via a transformer or capacitors. These pins are biased internally (see Figure 86) and require no external bias. If the inputs are floated, the CLK pin is pulled low to prevent spurious clocking.
AVDD
AD9650
If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 89. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock drivers offer excellent jitter performance.
0.1F CLOCK INPUT 0.1F CLK+
AD951x
0.1F PECL DRIVER 240 0.1F 240
100
ADC
AD9650
CLK
08919-047
CLOCK INPUT
50k
50k
CLK
A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 90. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ AD9518 clock drivers offer excellent jitter performance.
0.1F CLOCK INPUT 0.1F CLK+
AD951x
0.1F CLOCK INPUT 50k 50k LVDS DRIVER
100 0.1F
ADC
AD9650
CLK
08919-048
In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate, and the CLK pin should be bypassed to ground with a 0.1 F capacitor (see Figure 91).
VCC 0.1F CLOCK INPUT 501 1k 1k OPTIONAL 0.1F 100
AD951x
CMOS DRIVER
CLK+
ADC
AD9650
CLK
08919-049
0.1F
150
ADC
RESISTOR IS OPTIONAL.
AD9650
CLK+
Figure 91. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
ADC
1nF CLOCK INPUT 50 1nF SCHOTTKY DIODES: HSMS2822 0.1F
AD9650
CLK+
0.1F CLK
08919-046
Rev. A | Page 33 of 44
AD9650
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. The AD9650 requires a tight tolerance on the clock duty cycle to maintain dynamic performance characteristics. The AD9650 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9650. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS enabled. Jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.
82 80 2V p-p CLK AMPLITUDE 78
Data Sheet
SNR (dBFS)
72
Figure 92. SNR vs. CLK Divide Ratio for fIN = 141 MHz and a Sample Rate of 105 MSPS
The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9650. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. Refer to the AN-501 Application Note and the AN-756 Application Note (visit www.analog.com) for more information about jitter performance as it relates to ADCs.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. For inputs near full scale, the degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by SNRHF = 10 log[(2 fINPUT tJRMS)2 + 10 ( / SNRLF /10) ] In the equation, the rms aperture jitter represents the clock input jitter specification. Improvements in SNR can be achieved for IF undersampling applications by minimizing the effects of aperture jitter. This can be accomplished by applying a high frequency clock input and using the integrated clock divider to achieve the desired sample rate of the ADC core. Inherently, the jitter performance of the AD9650 improves as the frequency of the clock increases. This is a result of the slew rate of the clock affecting the noise performance of the ADC, where fast transition edges result in the best performance. Figure 92 shows the improvement in SNR for the different clock divide ratios for the 1 V p-p and 2 V p-p sinusoidal clock inputs. Measurements in Figure 92 were taken for the AD9650BCPZ-105 where the input frequency was 141 MHz. The same analysis can be performed for the various speed grades of the AD9650 family of parts.
CHANNEL/CHIP SYNCHRONIZATION
The AD9650 has a SYNC input that offers the user flexible synchronization options for synchronizing the clock divider. The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. The SYNC input should be driven using a single-ended CMOS-type signal.
Rev. A | Page 34 of 44
08919-293
70
Data Sheet
determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers reduces digital power consumption. By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9650 is placed in power-down mode. In this state, the ADC typically dissipates 3.3 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9650 to its normal operating mode. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and must be recharged when returning to normal operation. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required.
AD9650
As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Table 12. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin AGND AVDD SCLK/DFS Offset binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default)
DIGITAL OUTPUTS
The AD9650 output drivers can be configured to interface with 1.8 V CMOS logic families. The AD9650 can also be configured for LVDS outputs (standard ANSI or reduced output swing mode) using a DRVDD supply voltage of 1.8 V. In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The default output mode is CMOS, with each channel output on a separate bus, as shown in Figure 2. The output can also be configured for interleaved CMOS via the SPI port. In interleaved CMOS mode, the data for both channels is output through the Channel A output pins, and the Channel B output is placed into high impedance mode. The timing diagram for interleaved CMOS output mode is shown in Figure 3. The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 12).
TIMING
The AD9650 provides latched data with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9650. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9650 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade.
Rev. A | Page 35 of 44
Data Sheet
The outputs are not disconnected during this test; therefore, the PN sequence can be observed as it runs. The PN sequence can be continued from its last value or reset from the beginning, based on the value programmed in Register 0x0E, Bit 2. The BIST signature result varies based on the channel configuration.
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AD9650
The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 93 and Table 5. Other modes involving the CSB are available. When the CSB is held low indefinitely, which permanently enables the device, this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI secondary pin functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. All data is composed of 8-bit words. Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
CSB
tDS tS
CSB
tCLK
tH
DONT CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DONT CARE
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08919-052
AD9650
HARDWARE INTERFACE
The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9650. The SCLK pin and the CSB pin function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9650 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI is not being used. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD9650.
Data Sheet
When the device is in SPI mode, the PDWN and OEB pins remain active. For SPI control of output enable and power-down, the OEB and PDWN pins should be set to their default states. Table 15. Mode Selection
Pin SDIO/DCS SCLK/DFS OEB PDWN External Voltage AVDD (default) AGND AVDD AGND (default) AVDD AGND (default) AVDD AGND (default) Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled Outputs in high impedance Outputs enabled Chip in power-down or standby Normal operation
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AD9650
Logic Levels
An explanation of logic level terminology follows: Bit is set is synonymous with bit is set to Logic 1 or writing Logic 1 for the bit. Clear a bit is synonymous with bit is set to Logic 0 or writing Logic 0 for the bit.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 17 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 17 affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.
Open Locations
All address and bit locations that are not included in Table 17 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x17).
Default Values
After the AD9650 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 17.
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AD9650
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers
Address Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 SPI port 0 configuration (global) Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0
Data Sheet
Default Notes/ Comments The nibbles are mirrored so that LSBfirst mode or MSB-first mode registers correctly, regardless of shift mode. Read only. Speed grade ID used to differentiate devices; read only.
0x01 0x02
Open
8-bit Chip ID[7:0] (AD9650 = 0x3B, default) Open Open Speed grade ID 001 = 105 MSPS 010 = 80 MSPS 011 = 65 MSPS 100 = 25 MSPS Open Open Open Open Open
0x03
0xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
Bits are set to determine which device on the chip receives the next write command; applies to local registers only. Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation.
Open
Open
Open
0x09
Open
Open
Open
Open
Open
0x0B
Open
Open
Open
Open
Open
Internal powerdown mode (local) 00 = normal operation 01 = full powerdown 10 = standby 11 = normal operation Open Open Duty cycle stabilizer (default) Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8
Open
0x80
0x00
0x00
Clock divide values other than 000 automatically cause the duty cycle stabilizer to become active.
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Data Sheet
Address (Hex) 0x0D Register Name Test mode (local) Bit 7 (MSB) Open Bit 6 Open Bit 5 Reset PN long gen Bit 2 Bit 1 Output test mode 000 = off (default) 001 = midscale short 010 = positive FS 011 = negative FS 100 = alternating checkerboard 101 = PN long sequence 110 = PN short sequence 111 = one/zero word toggle Open Open Open Reset BIST Open BIST sequence enable Open Open Open Open Open Commonmode servo enable Offset adjust in LSBs from +127 to 128 (twos complement format) CMOS Output Open Output Output format output enable (must be invert 00 = offset binary written (local) interleave bar 01 = twos (local) low) complement enable (global) 01 = gray code 11 = offset binary (local) Open Open Input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles DCO clock delay (delay = 2500 ps register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps 11110 = 2419 ps 11111 = 2500 ps BIST signature[7:0] Open Bit 4 Reset PN short gen Bit 3 Open Bit 0 (LSB) Default Value (Hex) 0x00
AD9650
Default Notes/ Comments When this register is set, the test data is placed on the output pins in place of normal data.
0x0E 0x0F
Open Open
Open Open
0x04 0x00
0x10 0x14
0x00 0x00 Configures the outputs and the format of the data.
0x16
Drive strength 0 = ANSI LVDS; 1= reduced swing LVDS (global) Invert DCO clock
Open
0x00
0x17
Open
Open
Open
0x00
0x24
BIST signature LSB (local) 0x25 BIST signature MSB (local) 0x30 Dither enable (local) Digital Feature Control 0x100 SYNC control (global)
0x00 0x00
BIST signature[15:8] Open Open Open Dither enable Open Open Open Open Open
0x00
Open
Open
Open
Open
0x00
Rev. A | Page 41 of 44
AD9650
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
Data Sheet
receives and to ignore the rest. The clock divider SYNC enable bit (Address 0x100, Bit 1) resets after it synchronizes.
SYNC Control (Register 0x100) Bits[7:3]Reserved Bit 2Clock Divider Next SYNC Only
If the master SYNC enable bit (Address 0x100, Bit 0) and the clock divider SYNC enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to synchronize to the first SYNC pulse it
Rev. A | Page 42 of 44
AD9650
The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 F capacitor, as shown in Figure 80.
LVDS Operation
The AD9650 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed, using the SPI configuration registers after power-up. When the AD9650 powers up in CMOS mode with LVDS termination resistors (100 ) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD9650, but it should be taken into account when considering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the AD9650 outputs can be disabled at power-up by taking the OEB pin high. After the part is placed in LVDS mode via the SPI port, the OEB pin can be taken low to enable the outputs.
RBIAS
The AD9650 requires that a 10 k resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with a low ESR, 1.0 F capacitor in parallel with a low ESR, 0.1 F ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9650 to keep these signals from transitioning at the converter inputs during critical sampling periods.
Rev. A | Page 43 of 44
Data Sheet
PIN 1 INDICATOR
8.75 BSC SQ
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
0.50 0.40 0.30 TOP VIEW 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
33 32
16 17
0.22 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
02-23-2010-B
SEATING PLANE
Figure 94. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm 9 mm Body, Very Thin Quad (CP-64-6) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD9650BCPZ-25 AD9650BCPZRL7-25 AD9650BCPZ-65 AD9650BCPZRL7-65 AD9650BCPZ-80 AD9650BCPZRL7-80 AD9650BCPZ-105 AD9650BCPZRL7-105 AD9650-25EBZ AD9650-65EBZ AD9650-80EBZ AD9650-105EBZ
1
Temperature Range 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C
Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Evaluation Board Evaluation Board Evaluation Board
Package Option CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6
2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08919-0-11/11(A)
Rev. A | Page 44 of 44