Ad8421 PDF
Ad8421 PDF
Ad8421 PDF
FEATURES
Low power 2.3 mA maximum supply current Low noise 3.2 nV/Hz maximum input voltage noise at 1 kHz 200 fA/Hz current noise at 1 kHz Excellent ac specifications 10 MHz bandwidth (G = 1) 2 MHz bandwidth (G = 100) 0.6 s settling time to 0.001% (G = 10) 80 dB CMRR at 20 kHz (G = 1) 35 V/s slew rate High precision dc performance (AD8421BRZ) 94 dB CMRR minimum (G = 1) 0.2 V/C maximum input offset voltage drift 1 ppm/C maximum gain drift (G = 1) 500 pA maximum input bias current Inputs protected to 40 V from opposite supply 2.5 V to 18 V dual supply (5 V to 36 V single supply) Gain set with a single resistor (G = 1 to 10,000)
AD8421
8 7 6 5
Figure 1.
10
TOTAL NOISE DENSITY AT 1kHz (V/Hz)
100n
APPLICATIONS
Medical instrumentation Precision data acquisition Microphone preamplification Vibration analysis Multiplexed input applications ADC driver
10n
BEST AVAILABLE 1mA LOW POWER IN-AMP AD8421 RS NOISE ONLY 1k 10k 100k 1M
10123-078
1n 100
SOURCE RESISTANCE, RS ()
GENERAL DESCRIPTION
The AD8421 is a low cost, low power, extremely low noise, ultralow bias current, high speed instrumentation amplifier that is ideally suited for a broad spectrum of signal conditioning and data acquisition applications. This product features extremely high CMRR, allowing it to extract low level signals in the presence of high frequency common-mode noise over a wide temperature range. The 10 MHz bandwidth, 35 V/s slew rate, and 0.6 s settling time to 0.001% (G = 10) allow the AD8421 to amplify high speed signals and excel in applications that require high channel count, multiplexed systems. Even at higher gains, the current feedback architecture maintains high performance; for example, at G = 100, the bandwidth is 2 MHz and the settling time is 0.8 s. The AD8421 has excellent distortion performance, making it suitable for use in demanding applications such as vibration analysis. The AD8421 delivers 3 nV/Hz input voltage noise and 200 fA/Hz current noise with only 2 mA quiescent current, making it an ideal choice for measuring low level signals. For applications with high source impedance, the AD8421 employs innovative process technology and design techniques to provide noise performance that is limited only by the sensor. The AD8421 uses unique protection methods to ensure robust inputs while still maintaining very low noise. This protection allows input voltages up to 40 V from the opposite supply rail without damage to the part. A single resistor sets the gain from 1 to 10,000. The reference pin can be used to apply a precise offset to the output voltage. The AD8421 is specified from 40C to +85C and has typical performance curves to 125C. It is available in 8-lead MSOP and SOIC packages.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2012 Analog Devices, Inc. All rights reserved.
Data Sheet
Gain Selection............................................................................. 20 Reference Terminal .................................................................... 21 Input Voltage Range................................................................... 21 Layout .......................................................................................... 21 Input Bias Current Return Path ............................................... 22 Input Voltages Beyond the Supply Rails.................................. 22 Radio Frequency Interference (RFI)........................................ 23 Calculating the Noise of the Input Stage................................. 23 Applications Information .............................................................. 25 Differential Output Configuration .......................................... 25 Driving an ADC ......................................................................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
5/12Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8421
AR AND BR GRADES
Table 1.
Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 Over Temperature, G = 1 CMRR at 20 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz 1 Input Voltage Noise, eni Output Voltage Noise, eno Peak to Peak, RTI G=1 G = 10 G = 100 to 1000 Current Noise Spectral Density Peak to Peak, RTI VOLTAGE OFFSET 2 Input Offset Voltage, VOSI Over Temperature Average TC Output Offset Voltage, VOSO Over Temperature Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC Test Conditions/ Comments Min AR Grade Typ Max Min BR Grade Typ Max Unit
VCM = 10 V to +10 V 86 106 126 136 80 80 90 100 110 VIN+, VIN = 0 V 3 f = 0.1 Hz to 10 Hz 2 0.5 0.07 f = 1 kHz f = 0.1 Hz to 10 Hz VS = 5 V to 15 V TA = 40C to +85C 200 18 60 86 0.4 350 0.66 6 90 110 124 130 120 120 130 140 1 TA = 40C to +85C 50 0.5 TA = 40C to +85C 1 2 8 2 2.2 100 120 140 140 120 140 150 150 0.1 50 0.1 1 0.5 6 0.5 0.8 2 0.5 0.07 200 18 25 45 0.2 250 0.45 5 2.2 0.09 V p-p V p-p V p-p fA/Hz pA p-p V V V/C V mV V/C dB dB dB dB nA nA pA/C nA nA pA/C 3.2 60 3 3.2 60 nV/Hz nV/Hz 94 114 134 140 93 80 100 110 120 dB dB dB dB dB dB dB dB dB
Rev. 0 | Page 3 of 28
AD8421
Parameter DYNAMIC RESPONSE Small Signal Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time to 0.01% G=1 G = 10 G = 100 G = 1000 Settling Time to 0.001% G=1 G = 10 G = 100 G = 1000 Slew Rate G = 1 to 100 GAIN 3 Gain Range Gain Error G=1 G = 10 to 1000 Gain Nonlinearity G=1 G = 10 to 1000 Gain vs. Temperature3 G=1 G>1 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 4 Over Temperature OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Test Conditions/ Comments 3 dB 10 10 2 0.2 10 V step 0.7 0.4 0.6 5 10 V step 1 0.6 0.8 6 35 G = 1 + (9.9 k/RG) 1 VOUT = 10 V 0.02 0.2 VOUT = 10 V to +10 V RL 2 k RL = 600 RL 600 VOUT = 5 V to +5 V 1 3 50 10 5 50 10,000 1 1 0.6 0.8 6 35 0.7 0.4 0.6 5 10 10 2 0.2 Min AR Grade Typ Max Min BR Grade Typ
Data Sheet
Max Unit
MHz MHz MHz MHz s s s s s s s s V/s 10,000 0.01 0.1 1 3 50 10 1 50 V/V % % ppm ppm ppm ppm ppm/C ppm/C
1 30 5
1 30 5 0.1
30||3 30||3 VS = 2.5 V to 18 V TA = 40C TA = +85C RL = 2 k VS = 2.5 V to 18 V TA = 40C to +85C VS + 2.3 VS + 2.5 VS + 2.1 VS + 1.2 VS + 1.2 65 20 20 VS 1 0.0001 +VS 1.8 +VS 2.0 +VS 1.8 +Vs 1.6 +Vs 1.6 VS + 2.3 VS + 2.5 VS + 2.1 VS + 1.2 VS + 1.2
30||3 30||3 +VS 1.8 +VS 2.0 +VS 1.8 +VS 1.6 +VS 1.6 65 20 20 VS 1 0.0001
VIN+, VIN = 0 V
24 +VS
24 +VS
Rev. 0 | Page 4 of 28
Data Sheet
Parameter POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance Operational 5
1 2
AD8421
Test Conditions/ Comments Dual supply Single supply TA = 40C to +85C 40 40 Min 2.5 5 2 AR Grade Typ Max 18 36 2.3 2.6 +85 +125 Min 2.5 5 2 BR Grade Typ Max 18 36 2.3 2.6 +85 +125 Unit V V mA mA C C
40 40
Total voltage noise = (eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information. Total RTI VOS = (VOSI) + (VOSO/G). 3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table. 4 Input voltage range of the AD8421 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more details. 5 See the Typical Performance Characteristics section for expected operation between 85C and 125C.
VCM = 10 V to +10 V 84 104 124 134 80 80 90 100 100 VIN+, VIN = 0 V 3 f = 0.1 Hz to 10 Hz 2 0.5 0.07 f = 1 kHz f = 0.1 Hz to 10 Hz VS = 5 V to 15 V TA = 40C to +85C 200 18 70 135 0.9 600 1 9 2 0.5 0.07 200 18 50 135 0.9 400 1 9 2.2 0.09 V p-p V p-p V p-p fA/Hz pA p-p V V V/C V mV V/C 3.2 60 3 3.2 60 nV/Hz nV/Hz 92 112 132 140 90 80 90 100 100 dB dB dB dB dB dB dB dB dB
TA = 40C to +85C
Rev. 0 | Page 5 of 28
AD8421
Parameter Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC DYNAMIC RESPONSE Small Signal Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Settling Time 0.001% G=1 G = 10 G = 100 G = 1000 Slew Rate G = 1 to 100 GAIN 3 Gain Range Gain Error G=1 G = 10 to 1000 Gain Nonlinearity G=1 G = 10 to 1000 Gain vs. Temperature3 G=1 G>1 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 4 Over Temperature Test Conditions/ Comments VS = 2.5 V to 18 V Min 90 110 124 130 ARM Grade Typ Max 120 120 130 140 1 TA = 40C to +85C 50 0.5 TA = 40C to +85C 1 3 dB 10 10 2 0.2 10 V step 0.7 0.4 0.6 5 10 V step 1 0.6 0.8 6 35 G = 1 + (9.9 k/RG) 1 VOUT = 10 V 0.05 0.3 VOUT = 10 V to +10 V RL 2 k RL = 600 RL 600 VOUT = 5 V to +5 V 1 3 50 10 5 50 10,000 1 1 0.6 0.8 6 35 0.7 0.4 0.6 5 10 10 2 0.2 2 8 2 3 Min 100 120 140 140
Data Sheet
BRM Grade Typ Max 120 140 150 150 0.1 50 0.1 1 1 6 1 1.5 Unit dB dB dB dB nA nA pA/C nA nA pA/C
MHz MHz MHz MHz s s s s s s s s V/s 10,000 0.02 0.2 1 3 50 10 1 50 V/V % % ppm ppm ppm ppm ppm/C ppm/C
1 30 5
1 30 5 0.1
30||3 30||3 VS = 2.5 V to 18 V TA = 40C TA = +85C VS + 2.3 VS + 2.5 VS + 2.1 +VS 1.8 +VS 2.0 +VS 1.8 VS + 2.3 VS + 2.5 VS + 2.1
G||pF G||pF V V V
Rev. 0 | Page 6 of 28
Data Sheet
Parameter OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance Operational 5
1 2
AD8421
Test Conditions/ Comments RL = 2 k VS = 2.5 V to 18 V TA = 40C to +85C Min VS + 1.2 VS + 1.2 65 20 20 VS 1 0.0001 Dual supply Single supply TA = 40C to +85C 40 40 2.5 5 2 18 36 2.3 2.6 +85 +125 2.5 5 2 ARM Grade Typ Max +VS 1.6 +VS 1.6 Min VS + 1.2 VS + 1.2 65 20 20 VS 1 0.0001 18 36 2.3 2.6 +85 +125 BRM Grade Typ Max +Vs 1.6 +Vs 1.6 Unit V V mA k A V V/V
VIN+, VIN = 0 V
24 +VS
24 +VS
V V mA mA C C
40 40
Total voltage noise = (eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information. Total RTI VOS = (VOSI) + (VOSO/G). 3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table. 4 Input voltage range of the AD8421 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more information. 5 See the Typical Performance Characteristics section for expected operation between 85C and 125C.
Rev. 0 | Page 7 of 28
Data Sheet
THERMAL RESISTANCE
Rating 18 V Indefinite VS + 40 V +VS 40 V +VS + 0.3 V VS 0.3 V 65C to +150C 40C to +125C 150C 2 kV 1.25 kV 0.2 kV
JA is specified for a device in free air using a 4-layer JEDEC printed circuit board (PCB). Table 4.
Package 8-Lead SOIC 8-Lead MSOP JA 107.8 138.6 Unit C/W C/W
ESD CAUTION
For voltages beyond these limits, use input protection resistors. See the Theory of Operation section for more information. 2 There are ESD protection diodes from the reference input to each supply, so REF cannot be driven beyond the supplies in the same way that +IN and IN can. See the Reference Terminal section for more information.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 8 of 28
AD8421
AD8421
8 7 6 5
Rev. 0 | Page 9 of 28
Data Sheet
600
500
500
400
400
UNITS
300
UNITS
10123-003
300
200
200
100
100
40
20
20
40
60
300
200
100
100
200
300
400
1800
1200
1500
1000
1200
800
UNITS
900
UNITS
600
600
400
300
200
10123-004
1.5
1.0
0.5
0.5
1.0
1.5
2.0
1600
1400
1400
1200
1200
1000
1000
UNITS
UNITS
10123-005
PSRR (V/V)
90
60
30
30
60
90
120
CMRR (V/V)
Rev. 0 | Page 10 of 28
10123-008
15
10
10
15
20
0 120
10123-007
0 2.0
1.5
1.0
0.5
0.5
1.0
1.5
2.0
0 2.0
10123-006
0 60
0 400
Data Sheet
15 G=1 10 VS = 15V
3 4 G = 100 VS = 5V
AD8421
VS = 12V
2 1 VS = 2.5V 0 1 2 3 4
10
10123-009
10
10
15
Figure 13. Input Common-Mode Voltage vs. Output Voltage; VS = 2.5 V and 5 V (G = 100)
40 30 20 VS = 5V G=1
2 1 0 1 2 3 4 VS = 2.5V
10 0 10 20 30
10123-010
10 15 20 25 30 35 40
Figure 11. Input Common-Mode Voltage vs. Output Voltage; VS = 2.5 V and 5 V (G = 1)
15 G = 100 10 VS = 15V
30 VS = 15V G=1 20
VS = 12V
10
10
10
20
10123-011
10
10
15
20
15
10
10
15
20
25
Figure 12. Input Common-Mode Voltage vs. Output Voltage; VS = 12 V and 15 V (G = 100)
Rev. 0 | Page 11 of 28
10123-014
15 15
30 25
10123-013
40 35 30 25 20 15 10 5
10123-012
15 15
AD8421
40 30 20 VS = 5V G = 100
Data Sheet
160 GAIN = 1000 140 GAIN = 100
120 GAIN = 10
POSITIVE PSRR (dB)
10 0 10 20 30
10123-015
100 GAIN = 1 80 60 40 20
10123-018
40 35 30 25 20 15 10 5
10 15 20 25 30 35 40
0 0.1
10
10k
100k
1M
30 VS = 15V G = 100 20
10
100 80 60 40
10
20
20
10123-016
20
15
10
10
15
20
25
10
10k
100k
1M
1.0
GAIN (dB)
30 20 10 0 10 20 GAIN = 1 GAIN = 10
10
12
14
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Rev. 0 | Page 12 of 28
10123-020
2.5 12 10 8
30 100
10123-019
30 25
0 0.1
Data Sheet
160 GAIN = 1000 GAIN = 100 6 REPRESENTATIVE SAMPLES 4 2 0 2 4 6 8 40
AD8421
140
120
100
GAIN = 1
80
60
10123-021
10
100
1k
10k
100k
25
10
20
35
50
65
80
95
110
125
FREQUENCY (Hz)
TEMPERATURE (C)
120
CMRR (dB)
GAIN = 10
40 20 0 20 40
100
GAIN = 1
80
60 60
10123-025 10123-074
10123-022
40 0.1
10
100
1k
10k
100k
80 40
25
10
20
35
50
65
80
95
110
125
FREQUENCY (Hz)
TEMPERATURE (C)
2.0
CHANGE IN INPUT OFFSET VOLTAGE (V)
1.5
10
CMRR (V/V)
1.0
0.5
5
0
10
10
15
20
25
30
35
40
45
50
10123-023
0.5
15 40
25
10
20
35
50
65
80
95
110
125
TEMPERATURE (C)
Figure 24. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time
Rev. 0 | Page 13 of 28
10123-024
40 0.1
GAIN = 10
CMRR (dB)
AD8421
3.0
Data Sheet
40 SR 35
VS = 15V
2.5
30
2.0 VS = 5V 1.5
25 20 15 10
+SR
1.0
0.5
5 0 40
25
10
20
35
50
65
80
95
110
125
25
10
20
35
50
65
80
95
110
125
TEMPERATURE (C)
TEMPERATURE (C)
40 20 0 20 40 60 80 100 120 40 25 10 5
ISHORT+
+2.5 +2.0 +1.5 +1.0 +0.5 40C +25C +85C +105C +125C 2 4 6 8 10 12 14 16 18
10123-030 10123-031
ISHORT
20
35
50
65
80
95
110
125
10123-027
VS
TEMPERATURE (C)
40 35 SR 30
+VS 0.5
OUTPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES
25 20 15 10 5 0 40 25
+SR
10123-028
10
20
35
50
65
80
95
110
125
VS
10
12
14
16
18
20
TEMPERATURE (C)
Rev. 0 | Page 14 of 28
10123-029
10123-026
0 40
Data Sheet
+VS 0.5
OUTPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES
5 4 3
NONLINEARITY (ppm)
AD8421
GAIN = 1
2 1 0 1 2 3 4 RL = 2k RL = 10k 8 6 4 2 0 2 4 6 8 10
10123-035 10123-072 10123-036
18
20
10123-032
VS
5 10
GAIN = 1 4 3
NONLINEARITY (ppm)
10
OUTPUT VOLTAGE SWING (V)
2 1 0 1 2 3 4 RL = 600
10
10123-033
15 100
1k LOAD ()
10k
100k
5 10
10
+VS 2
40 20 0 20 40 60 80 RL = 600
+8 +6 +4 +2
10123-034
VS
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
100 10
10
Rev. 0 | Page 15 of 28
AD8421
100 GAIN = 1000 80 60
NONLINEARITY (ppm)
Data Sheet
10k
40 20 0 20 40 60 80
10123-073
1k
RL = 600
100
10
1k
10k
100k
1k
VOLTAGE NOISE SPECTRAL DENSITY (nV/Hz)
100 GAIN = 1
10
5pA/DIV
1 10 100 1k 10k 100k
10123-037
1s/DIV
FREQUENCY (Hz)
30
G = 1000, 40nV/DIV
25
20
15
G = 1, 1V/DIV
10
1s/DIV
10123-038
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Rev. 0 | Page 16 of 28
10123-045
0 10
10123-040
10123-039
100 5
10 0.1
Data Sheet
AD8421
0.002%/DIV
0.002%/DIV
10123-041
1s/DIV
4s/DIV
Figure 46. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step, VS = 15 V, RL = 2 k, CL = 100 pF
Figure 49. Large Signal Pulse Response and Settling Time (G = 1000), 10 V Step, VS = 15 V, RL = 2 k, CL = 100 pF
2500
1500
1000
SETTLED TO 0.001%
0.002%/DIV
500 1s/DIV
10123-042
SETTLED TO 0.01%
GAIN = 1 2 4 6 8 10 12 14 16 18 20
10123-054
Figure 47. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step, VS = 15 V, RL = 2 k, CL = 100 pF
GAIN = 1
0.002%/DIV
10123-043
1s/DIV
50mV/DIV
1s/DIV
Figure 48. Large Signal Pulse Response and Settling Time (G = 100), 10 V Step, VS = 15 V, RL = 2 k, CL = 100 pF
Rev. 0 | Page 17 of 28
10123-046
10123-044
AD8421
GAIN = 10
20pF 50pF NO LOAD 100pF
Data Sheet
G=1
10123-047
50mV/DIV
1s/DIV
50mV/DIV
1s/DIV
Figure 55. Small Signal Response with Various Capacitive Loads (G = 1), RL = Infinity
40 RL 600 VOUT = 10V p-p
GAIN = 100
50 60 70
AMPLITUDE (dBc)
10123-048
20mV/DIV
1s/DIV
150 10
40 GAIN = 1000 50 60 70
NO LOAD RL = 2k RL = 600
AMPLITUDE (dBc)
10123-049
20mV/DIV
2s/DIV
150 10
Rev. 0 | Page 18 of 28
10123-053
Data Sheet
40 50 60 NO LOAD RL = 2k RL = 600 VOUT = 10V p-p 20 30 40 50 G G G G =1 = 10 = 100 = 1000
AD8421
VOUT = 10V p-p RL = 2k
AMPLITUDE (dBc)
70 80 90 100 110
10123-075
AMPLITUDE (dBc)
100
1k FREQUENCY (Hz)
10k
100
1k FREQUENCY (Hz)
10k
40 RL 600 50 60
AMPLITUDE (dBc)
70 80 90 100 110
10123-076
120 10
100
1k FREQUENCY (Hz)
10k
Rev. 0 | Page 19 of 28
10123-077
120 10
140 10
Data Sheet
A1
A2
OUTPUT
IN
+VS RG
+VS
ARCHITECTURE
The AD8421 is based on the classic 3-op-amp topology. This topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier that removes the common-mode voltage. Figure 61 shows a simplified schematic of the AD8421. Topologically, Q1, A1, R1 and Q2, A2, R2 can be viewed as precision current feedback amplifiers. Input Transistors Q1 and Q2 are biased at a fixed current so that any input signal forces the output voltages of A1 and A2 to change accordingly. The differential signal applied to the inputs is replicated across the RG pins. Any current through RG also flows through R1 and R2, creating a gained differential voltage between Node 1 and Node 2. The amplified differential and common-mode signals are applied to a difference amplifier that rejects the common-mode voltage but preserves the amplified differential voltage. The difference amplifier employs innovations that result in very low output errors such as offset voltage and drift, distortion at various loads, as well as output noise. Laser-trimmed resistors allow for a highly accurate in-amp with gain error less than 0.01% and CMRR that exceeds 94 dB (G = 1). The high performance pinout and special attention given to design and layout allow for high CMRR performance across a wide frequency and temperature range. Using superbeta input transistors and bias current compensation, the AD8421 offers extremely high input impedance, low bias current, low offset current, low current noise, and extremely low voltage noise of 3 nV/Hz. The current-limiting and overvoltage protection scheme allow the input to go 40 V from the opposite rail at all gains without compromising the noise performance. The transfer function of the AD8421 is VOUT = G (V+IN VIN) + VREF where G = 1 + 9.9 k
RG
Users can easily and accurately set the gain using a single standard resistor.
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the AD8421. The gain can be calculated by referring to Table 6 or by using the following gain equation: RG = 9.9 k
G 1
The AD8421 defaults to G = 1 when no gain resistor is used. To determine the total gain accuracy of the system, add the tolerance and gain drift of the RG resistor to the specifications of the AD8421. When the gain resistor is not used, gain error and gain drift are minimal. Table 6. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG 10 k 2.49 k 1.1 k 523 200 100 49.9 20 10 4.99 Calculated Gain 1.99 4.98 10.00 19.93 50.50 100.0 199.4 496.0 991.0 1985
RG Power Dissipation
The AD8421 duplicates the differential voltage across its inputs onto the RG resistor. Choose an RG resistor size that is sufficient to handle the expected power dissipation at ambient temperature.
Rev. 0 | Page 20 of 28
10123-057
Data Sheet
REFERENCE TERMINAL
The output voltage of the AD8421 is developed with respect to the potential on the reference terminal. This can be used to sense the ground at the load, thereby taking advantage of the CMRR to reject ground noise or to introduce a precise offset to the signal at the output. For example, a voltage source can be tied to the REF pin to level shift the output, allowing the AD8421 to drive a singlesupply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or VS by more than 0.3 V. For best performance, maintain a source impedance to the REF terminal that is below 1 . As shown in Figure 61, the reference terminal, REF, is at one end of a 10 k resistor. Additional impedance at the REF terminal adds to this 10 k resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be calculated as follows: 2(10 k + RREF)/(20 k + RREF) Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR.
INCORRECT CORRECT
AD8421
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To maintain high CMRR over frequency, closely match the input source impedance and capacitance of each path. Place additional source resistance in the input path (for example, input protection resistors) close to the in-amp inputs, to minimize the interaction of the resistance with parasitic capacitance from the PCB traces. Parasitic capacitance at the gain setting pins (RG) can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), choose a component such that the parasitic capacitance is as small as possible.
AD8421
REF V + V
AD8421
REF
OP1177
10123-058
0.1F
10F
AD8421
IN REF
VOUT LOAD
VS
LAYOUT
To ensure optimum performance of the AD8421 at the PCB level, care must be taken in the design of the board layout. The pins of the AD8421 are arranged in a logical manner to aid in this task.
IN 1 RG 2 RG 3 +IN 4
8 +VS 7 VOUT 6 REF
Figure 64. Supply Decoupling, REF, and Output Referred to Local Ground
A ground plane layer helps to reduce parasitic inductances, which minimizes voltage drops with changes in current. The area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequency. Large changes in currents in an inductive decoupling path or ground return create unwanted effects due to the coupling of such changes into the amplifier inputs. Because load currents flow from the supplies, the load should be connected at the same physical location as the bypass capacitor grounds.
10123-059
AD8421
5 VS
Rev. 0 | Page 21 of 28
10123-060
0.1F
10F
AD8421
Reference Pin
The output voltage of the AD8421 is developed with respect to the potential on the reference terminal. Ensure that REF is tied to the appropriate local ground.
Data Sheet
protection required at all gains. For example, if +VS = +5 V and VS = 8 V, the part can safely withstand voltages from 35 V to +32 V. The remaining AD8421 terminals should be kept within the supplies. All terminals of the AD8421 are protected against ESD.
CORRECT
+VS
AD8421
REF
AD8421
REF
AD8421
AD8421
RPROTECT
VS TRANSFORMER +VS
VS TRANSFORMER +VS
+ VIN
VS
+ VIN
VS
TRANSIENT PROTECTION
RPROTECT
+VS
+VS
AD8421
REF 10M VS THERMOCOUPLE +VS C C
AD8421
REF
+ VIN+
AD8421
RPROTECT
AD8421
VS THERMOCOUPLE +VS
VIN
VS
VIN
VS
VS
10123-063
Figure 67. Input Protection Options for Input Voltages Beyond Absolute Maximum Ratings
R
AD8421
C REF
fHIGH-PASS = 21 RC
C
AD8421
REF
For longer events, use resistors in series with the inputs, combined with diodes. To avoid degrading bias current performance, low leakage diodes such as the BAV199 or FJH1100 are recommended. The diodes prevent the voltage at the input of the amplifier from exceeding the maximum ratings, and the resistors limit the current into the diodes. Because most external diodes can easily handle 100 mA or more, resistor values do not need to be large and, therefore, have a minimal impact on noise performance. At the expense of some noise performance, another solution is to use series resistors. In the case of overvoltage, current into the AD8421 inputs is internally limited. Although the AD8421 inputs must be kept within the limits defined in the Absolute Maximum Ratings section, the I R drop across the protection resistor increases the maximum voltage that the system can withstand, as follows: For positive input signals VMAX_NEW = (40 V + Negative Supply) + IIN RPROTECT For negative input signals VMIN_NEW = (Positive Supply 40 V) IOUT RPROTECT
AD8421
MOST APPLICATIONS
The AD8421 inputs are current limited; therefore, input voltages can be up to 40 V from the opposite supply rail, with no input
Rev. 0 | Page 22 of 28
10123-062
+ VIN+
VS
Data Sheet
Overvoltage performance is shown in Figure 14, Figure 15, Figure 16, and Figure 17. The AD8421 inputs can withstand a current of 40 mA at room temperature for at least a day. This time is cumulative over the life of the device. If long periods of overvoltage are expected, the use of an external protection method is recommended. Under extreme input conditions, the output of the amplifier may invert.
AD8421
To achieve low noise and sufficient RFI filtering, the use of chip ferrite beads is recommended. Ferrite beads increase their impedance with frequency, thus leaving the signal of interest unaffected while preventing RF interference to reach the amplifier. They also help to eliminate the need for large resistor values in the filter, thus minimizing the systems input-referred noise. The selection of the appropriate ferrite bead and capacitor values is a function of the interference frequency, input lead length, and RF power. For best results, place the RFI filter network as close as possible to the amplifier. Layout is critical to ensure that RF signals are not picked up on the traces after the filter. If RF interference is too strong to be filtered sufficiently, shielding is recommended. The resistors used for the RFI filter can be the same as those used for input protection.
10F
L*
+IN
AD8421
REF IN
VOUT
The choice of resistor and capacitor values depends on the desired trade-off between noise, input impedance at high frequencies, CMRR, signal bandwidth, and RFI immunity. An RC network limits both the differential and common-mode bandwidth, as shown in the following equations:
FilterFreq uency DIFF = FilterFreq uency CM = 1 2R(2C D + C C )
where CD 10 CC. CD affects the differential signal, and CC affects the commonmode signal. A mismatch between R CC at the positive input and R CC at the negative input degrades the CMRR of the AD8421. By using a value of CD that is one order of magnitude larger than CC, the effect of the mismatch is reduced and CMRR performance is improved near the cutoff frequencies.
R2
For example, assume that the combined sensor and protection resistance is 4 k on the positive input and 1 k on the negative input. Then the total noise from the input resistance is
(4 4 ) + (4 1 )
2
= 64 + 16 = 8.9 nV/Hz
Rev. 0 | Page 23 of 28
10123-065
1 2RC C
R1
RG
AD8421
AD8421
Voltage Noise of the Instrumentation Amplifier
The voltage noise of the instrumentation amplifier is calculated using three parameters: the device output noise, the input noise, and the RG resistor noise. It is calculated as follows:
Total Voltage Noise =
Data Sheet
For example, if the R1 source resistance in Figure 69 is 4 k, and the R2 source resistance is 1 k, the total effect from the current noise is calculated as follows:
(4 0.2 )2 + (1 0.2 )2
= 0.8 nV/Hz
Resistor )2
For example, for a gain of 100, the gain resistor is 100 . Therefore, the voltage noise of the in-amp is
(60 / 100 )
+ 3.2
(4
0.1
= 3.5 nV/Hz
+ 3.5 2 + 0.8 2
= 9.6 nV/Hz
Rev. 0 | Page 24 of 28
AD8421
Although the dc performance and resistor matching of the op amp affect the dc common-mode output accuracy, such errors are likely to be rejected by the next device in the signal chain and, therefore, typically have little effect on overall system accuracy. Because this circuit is susceptible to instability, a capacitor is included to limit the effective op amp bandwidth. This capacitor can be omitted if the amplifier pairing is stable. The open-loop gain and phase of any amplifier may vary with process variation and temperature. Additional phase lag can be introduced by resistive or capacitive loading. To guarantee stability, the value of the capacitor in Figure 70 should be determined with a sample of circuits by evaluating the small signal pulse response of the circuit with load at the extremes of the output dynamic range. The ambient temperature should also be varied over the expected range to evaluate its effect on stability. The voltage at +OUT may still have some overshoot after the circuit is tuned because the AD8421 output amplifier responds faster than the op amp. A 12 pF capacitor is a good starting point. For best large signal ac performance, use an op amp with a high slew rate to match the AD8421 performance of 35 V/s. High bandwidth is not essential because the system bandwidth is limited by the RC feedback. Some good choices for op amps are the AD8610, ADA4627-1, AD8510, and the ADA4898-1.
AD8421
IN REF 10k VBIAS
+OUT
12pF
10k
+ OP AMP
OUT
The differential output voltage is set by the following equation: VDIFF_OUT = V+OUT VOUT = Gain (V+IN VIN) The common-mode output is set by the following equation: VCM_OUT = (V+OUT + VOUT)/2 = VBIAS The advantage of this circuit is that the dc differential accuracy depends on the AD8421, not on the op amp or the resistors. In addition, this circuit takes advantage of the precise control that the AD8421 has of its output voltage relative to the reference voltage.
10123-066
Rev. 0 | Page 25 of 28
AD8421
DRIVING AN ADC
The Class AB output stage, low noise and distortion, and high bandwidth and slew rate make the AD8421 a good choice for driving an ADC in a data acquisition system that requires frontend gain, high CMRR, and dc precision. Figure 71 shows the AD8421, in a gain-of-10 configuration, driving the AD7685, a 16-bit, 250 kSPS pseudodifferential SAR ADC. The RC low-pass filter that is shown between the AD8421 and the AD7685 has several purposes. It isolates the amplifier output from excessive loading from the dynamic ADC inputs, reduces the noise bandwidth of the amplifier, and provides overload protection for the AD7685 analog inputs. The filter cutoff can be determined empirically. To achieve the best ac performance, keep the impedance magnitude greater than 1 k at the maximum input signal
Data Sheet
frequency, and set the filter cutoff to settle to LSB in one sampling period for a full-scale step. For additional considerations, refer to the data sheet of the ADC in use. In a gain-of-10 configuration, the AD8421 has approximately 8 nV/Hz voltage noise RTI (See the Calculating the Noise of the Input Stage section.) The front-end gain makes the system ten times more sensitive to input signals, with only a 7.5 dB reduction of SNR. The high current output and load regulation of the ADR435 allow the AD7685 to be powered directly from the reference without the need to provide another analog supply rail. The reference pin buffer may be any low power, unity-gain stable, dc precision op amp with less than approximately 25 nV/Hz of wideband noise, such as the OP1177. Not all proper decoupling is shown in Figure 71. Take care to follow decoupling guidelines for both amplifiers and the ADR435.
10 10k 2.5V 10k G = 10 1.1k REF IN+ VDD VIO SDI SCK SDO CNV 3- OR 4-WIRE INTERFACE 1F
ADR435
+5V 0.1F
AD8421
REF IN 12V
100 3nF
AD7685
IN GND
2.5V 10F
10123-070
5k
0 20
160
25
50
75
100
125
FREQUENCY (kHz)
Figure 72. Typical Spectrum of the AD8421 (G = 10) Driving the AD7685
Rev. 0 | Page 26 of 28
AD8421
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 73. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
0.65 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.40 0.25 15 MAX 1.10 MAX 0.23 0.09 0.80 0.55 0.40
10-07-2009-B
6 0
Figure 74. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD8421ARZ AD8421ARZ-R7 AD8421ARZ-RL AD8421BRZ AD8421BRZ-R7 AD8421BRZ-RL AD8421ARMZ AD8421ARMZ-R7 AD8421ARMZ-RL AD8421BRMZ AD8421BRMZ-R7 AD8421BRMZ-RL
1
Temperature Range 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C
Package Description 8-Lead SOIC_N, standard grade 8-Lead SOIC_N, standard grade, 7 Tape and Reel, 8-Lead SOIC_N, standard grade, 13 Tape and Reel 8-Lead SOIC_N, high performance grade 8-Lead SOIC_N, high performance grade, 7 Tape and Reel 8-Lead SOIC_N, high performance grade, 13 Tape and Reel 8-Lead MSOP, standard grade 8-Lead MSOP, standard grade, 7 Tape and Reel 8-Lead MSOP, standard grade, 13 Tape and Reel 8-Lead MSOP, high performance grade 8-Lead MSOP, high performance grade, 7 Tape and Reel 8-Lead MSOP, high performance grade, 13 Tape and Reel
012407-A
Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8
Branding
AD8421 NOTES
Data Sheet
2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10123-0-5/12(0)
Rev. 0 | Page 28 of 28