LNK562-564

LinkSwitch-LP
®

Energy Efficient Off-Line Switcher IC for

Linear Transformer Replacement

Product Highlights
+ DC
Lowest System Cost and Advanced Safety Features AC
Output
IN
• Lowest component count switcher
• Very tight parameter tolerances using proprietary IC
trimming technology and transformer construction
techniques enable Clampless™designs – decreases D
FB
component count/system cost and increases efficiency
LinkSwitch-LP BP
• Meets industry standard requirements for thermal overload
S
protection – eliminates the thermal fuse used with linear
transformers or additional components in RCC designs
(a) PI-3923-092705
• Frequency jittering greatly reduces EMI – enables low cost
input filter configuration VO
• Meets HV creepage requirements between DRAIN and all Rated Output Power = VR • IR
other pins, both on the PCB and at the package
VR
• Proprietary E-Shield™ transformer eliminates Y capacitor

Superior Performance over Linear and RCC

• Hysteretic thermal shutdown protection – automatic
recovery improves field reliability
• Universal input range allows worldwide operation IR IO
• Auto-restart reduces delivered power by >85% during (b) PI-3924-011706
short circuit and open loop fault conditions
• Simple ON/OFF control, no loop compensation needed Figure 1. Typical Application – not a Simplified Circuit (a) and
• High bandwidth provides fast turn on with no overshoot Output Characteristic Envelope (b).
and excellent transient load response

EcoSmart – Energy Efficiency Technology

® OUTPUT POWER TABLE1
• Easily meets all global energy efficiency regulations with 230 VAC ±15% 85-265 VAC
no added components PRODUCT4 Open Open
• No-load consumption <150 mW at 265 VAC input Adapter2 Adapter2
Frame3 Frame3
• ON/OFF control provides constant efficiency to very
light loads – ideal for mandatory CEC regulations LNK562P or G 1.9 W 1.9 W 1.9 W 1.9 W
LNK563P or G 2.5 W 2.5 W 2.5 W 2.5 W
Applications LNK564P or G 3W 3W 3W 3W
• Chargers for cell/cordless phones, PDAs, power tools,
MP3/portable audio devices, shavers etc. Table 1. Notes: 1. Output power may be limited by specific application
• Standby and auxiliary supplies parameters including core size and Clampless operation (see Key
Application Considerations). 2. Minimum continuous power in a typical
non-ventilated enclosed adapter measured at 50 °C ambient. 3. Minimum
Description practical continuous power in an open frame design with adequate
LinkSwitch-LP switcher ICs cost effectively replace all heat sinking, measured at 50 °C ambient. 4. Packages: P: DIP-8B,
unregulated isolated linear transformer based (50/60 Hz) power G: SMD-8B. For lead-free package options, see Part Ordering
Information.
supplies up to 3 W output power. For worldwide operation, a
single universal input design replaces multiple linear transformer
based designs. The self-biased circuit achieves an extremely low frequency is jittered to significantly reduce both quasi-peak and
no-load consumption of under 150 mW. The internal oscillator average EMI, minimizing filter cost.

October 2005
 LNK562-564

BYPASS DRAIN
(BP) (D)
REGULATOR
5.8 V

AUTO-RESTART
COUNTER FAULT BYPASS PIN
0.8 V PRESENT UNDER-VOLTAGE
RESET +
+
5.8 V -
4.85 V CURRENT LIMIT
6.3 V COMPARATOR

- VI
LIMIT

JITTER
CLOCK

DCMAX
ADJ THERMAL
SHUTDOWN
OSCILLATOR
FEEDBACK
1.69 V -VTH
(FB)
S Q

OPEN LOOP R Q
PULLDOWN
LEADING
EDGE
BLANKING

PI-3958-092905
SOURCE
(S)

Figure 2. Functional Block Diagram.

Pin Functional Description

DRAIN (D) Pin: P Package (DIP-8B)
The power MOSFET drain connection provides internal G Package (SMD-8B)
operating current for both start-up and steady-state operation.

BYPASS (BP) Pin: S 1 8 S

A 0.1 µF external bypass capacitor for the internally generated S 2 7 S
5.8 V supply is connected to this pin.
BP 3
FEEDBACK (FB) Pin: FB 4 5 D
During normal operation, switching of the power MOSFET is
controlled by this pin. MOSFET switching is disabled when a
current greater than 70 µA flows into this pin.
PI-3491-111903

SOURCE (S) Pin:

Figure 3. Pin Configuration.
This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS and FEEDBACK pins.

LinkSwitch-LP Functional protection, frequency jittering, current limit circuit, and leading
edge blanking.
Description
LinkSwitch-LP comprises a 700 V power MOSFET switch with Oscillator
a power supply controller on the same die. Unlike conventional The typical oscillator frequency is internally set to an average
PWM (pulse width modulation) controllers, it uses a simple of 66/83/100 kHz for the LNK562, 563 & 564 respectively.
ON/OFF control to regulate the output voltage. The controller Two signals are generated from the oscillator: the maximum
consists of an oscillator, feedback (sense and logic) circuit, 5.8 V duty cycle signal (DCMAX) and the clock signal that indicates
regulator, BYPASS pin under-voltage circuit, over-temperature the beginning of each switching cycle.

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2 10/05
 LNK562-564

The oscillator incorporates circuitry that introduces a small Over-Temperature Protection

amount of frequency jitter, typically 5% of the switching The thermal shutdown circuitry senses the die temperature.
frequency, to minimize EMI. The modulation rate of the The threshold is set at 142 °C typical with a 75 °C hysteresis.
frequency jitter is set to 1 kHz to optimize EMI reduction When the die temperature rises above this threshold (142 °C)
for both average and quasi-peak emissions. The frequency the power MOSFET is disabled and remains disabled until the
jitter, which is proportional to the oscillator frequency, should die temperature falls by 75 °C, at which point the MOSFET
be measured with the oscilloscope triggered at the falling is re-enabled.
edge of the DRAIN voltage waveform. The waveform in
Figure 4 illustrates the frequency jitter. The oscillator frequency Current Limit
is reduced when the FB pin voltage is less than 1.69 V as The current limit circuit senses the current in the power MOSFET.
described below. When this current exceeds the internal threshold (ILIMIT), the
power MOSFET is turned off for the remainder of that cycle. The
Feedback Input Circuit leading edge blanking circuit inhibits the current limit comparator
The feedback input circuit at the FB pin consists of a low for a short time (tLEB) after the power MOSFET is turned on. This
impedance source follower output set at 1.69 V. When the current leading edge blanking time has been set so that current spikes
delivered into this pin exceeds 70 µA, a low logic level (disable) caused by capacitance and rectifier reverse recovery time will
is generated at the output of the feedback circuit. This output not cause premature termination of the MOSFET conduction.
is sampled at the beginning of each cycle on the rising edge of
the clock signal. If high, the power MOSFET is turned on for
600

PI-3660-081303
that cycle (enabled), otherwise the power MOSFET remains
off (disabled). Since the sampling is done only at the beginning 500
of each cycle, subsequent changes in the FB pin voltage or VDRAIN
current during the remainder of the cycle are ignored. When 400
the FB pin voltage falls below 1.69 V, the oscillator frequency
linearly reduces to typically 48% at the auto-restart threshold 300

voltage of 0.8 V. This function limits the power supply output

200
current at output voltages below the rated voltage regulation
threshold VR (see Figure 1). 100

5.8 V Regulator and 6.3 V Shunt Voltage Clamp 0

The 5.8 V regulator charges the bypass capacitor connected to 68 kHz
64 kHz
the BYPASS pin to 5.8 V by drawing a current from the voltage
on the DRAIN, whenever the MOSFET is off. The BYPASS
pin is the internal supply voltage node. When the MOSFET 0 20
is on, the device runs off of the energy stored in the bypass Time (µs)
capacitor. Extremely low power consumption of the internal
Figure 4. Frequency Jitter at fOSC.
circuitry allows LinkSwitch-LP to operate continuously from the
current drawn from the DRAIN pin. A bypass capacitor value of
0.1 µF is sufficient for both high frequency decoupling and Auto Restart
energy storage. In the event of a fault condition such as output short circuit or
an open loop condition, LinkSwitch-LP enters into auto-restart
In addition, there is a 6.3 V shunt regulator clamping the operation. An internal counter clocked by the oscillator gets reset
BYPASS pin at 6.3 V when current is provided to the BYPASS every time the FB pin voltage exceeds the FEEDBACK Pin
pin externally. This facilitates powering the device externally Auto-Restart Threshold Voltage (VFB(AR)). If the FB pin voltage
through a resistor from the bias winding to decrease the no- drops below VFB(AR) for more than 100 ms, the power MOSFET
load consumption. switching is disabled. The auto-restart alternately enables and
disables the switching of the power MOSFET at a duty cycle
BYPASS Pin Under-Voltage of typically 12% until the fault condition is removed.
The BYPASS pin under-voltage circuitry disables the power
MOSFET when the BYPASS pin voltage drops below 4.85 V.
Once the BYPASS pin voltage drops below 4.85 V, it must rise
back to 5.8 V to enable (turn-on) the power MOSFET.

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10/05 3
 LNK562-564

C5 VR1*
D1 RF1* L1 T1 D4 220 µF R3 1N5240B 6 V,
L 1N4937 8.2 Ω 3300 µH EE16 7 UF4002 25 V 2 kΩ 10 V 0.33 A
2
J-1 2.5 W J3-2
C1
90-265 10 µF J3-1
VAC 1 6
400 V
J-2 4 RTN

N
D2
1N4005 5
R1
D3 37.4 kΩ
1N4005 C4*
D C3 100 pF
FB 250 VAC
LinkSwitch-LP 330 nF
U1 BP 50 V
LNK564P C2 R2
S 0.1 µF 3 kΩ
*Optional components
50 V
PI-4106-101105

Figure 5. 6 V, 330 mA CV/CC Linear Replacement Power Supply.

Applications Example output of the power supply), the power supply will turn OFF
for 800 ms and then turn back on for 100 ms. It will continue
The circuit shown in Figure 5 is a typical implementation of in this mode until the auto-restart threshold is exceeded. This
a 6 V, 330 mA, constant voltage, constant current (CV/CC) function reduces the average output current during an output
output power supply. short circuit condition.

AC input differential filtering is accomplished with the very No-load consumption can be further reduced by increasing C3
low cost input filter stage formed by C1 and L1. The proprietary to 0.47 µF or higher.
frequency jitter feature of the LNK564 eliminates the need for
an input pi filter, so only a single bulk capacitor is required. A Clampless primary circuit is achieved due to the very
Adding a sleeve may allow the input inductor L1 to be used as a tight tolerance current limit trimming techniques used in
fuse as well as a filter component. This very simple Filterfuse™ manufacturing the LNK564, plus the transformer construction
input stage further reduces system cost. Alternatively, a fusible techniques used. Peak drain voltage is therefore limited to
resistor RF1 may be used to provide the fusing function. typically less than 550 V at 265 VAC, providing significant
margin to the 700 V minimum drain voltage specification
Input diode D2 may be removed from the neutral phase in (BVDSS).
applications where decreased EMI margins and/or decreased
input surge withstand is allowed. In such applications, D1 will Output rectification and filtering is achieved with output rectifier
need to be an 800 V diode. D4 and filter capacitor C5. Due to the auto-restart feature, the
average short circuit output current is significantly less than
The power supply utilizes simplified bias winding voltage 1 A, allowing low cost rectifier D4 to be used. Output circuitry is
feedback, enabled by LNK564 ON/OFF control. The resistor designed to handle a continuous short circuit on the power supply
divider formed by R1 and R2 determine the output voltage across output. Diode D4 is an ultra-fast type, selected for optimum
the transformer bias winding during the switch OFF time. In the V/I output characteristics. Optional resistor R3 provides a pre-
V/I constant voltage region, the LNK564 device enables/disables load, limiting the output voltage level under no-load output
switching cycles to maintain 1.69 V on the FB pin. Diode D3 and conditions. Despite this pre-load, no-load consumption is within
low cost ceramic capacitor C3 provide rectification and filtering targets at approximately 140 mW at 265 VAC. The additional
of the primary feedback winding waveform. At increased loads, margin of no-load consumption requirement can be achieved
beyond the constant power threshold, the FB pin voltage begins by increasing the value of R4 to 2.2 kΩ or higher while still
to reduce as the power supply output voltage falls. The internal maintaining output voltage well below the 9 V maximum
oscillator frequency is linearly reduced in this region until it specification. Placement is left on the board for an optional
reaches typically 50% of the starting frequency. When the FB Zener clamp (VR1) to limit maximum output voltage under
pin voltage drops below the auto-restart threshold (typically open loop conditions, if required.
0.8 V on the FB pin, which is equivalent to 1 V to 1.5 V at the

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 LNK562-564

Key Application Considerations The following requirements are recommended for a universal
input or 230 VAC only Clampless design:
Output Power Table
The data sheet maximum output power table (Table 1) represents 1. Clampless designs should only be used for PO ≤ 2.5 W using
the maximum practical continuous output power level that can a VOR of ≤ 90 V
be obtained under the following assumed conditions: 2. For designs with PO ≤ 2 W, a two-layer primary must be
used to ensure adequate primary intra-winding capacitance
1. The minimum DC input voltage is 90 V or higher for 85 VAC in the range of 25 pF to 50 pF.
input, or 240 V or higher for 230 VAC input or 115 VAC 3. For designs with 2 < PO ≤ 2.5 W, a bias winding must be added
with a voltage doubler. The value of the input capacitance to the transformer using a standard recovery rectifier diode
should be large enough to meet these criteria for AC input (1N4003– 1N4007) to act as a clamp. This bias winding may
designs. also be used to externally power the device by connecting
2. Secondary output of 6 V with a Schottky rectifier diode. a resistor from the bias winding capacitor to the BYPASS
3. Assumed efficiency of 70%. pin. This inhibits the internal high voltage current source,
4. Voltage only output (no secondary-side constant current reducing device dissipation and no-load consumption.
circuit). 4. For designs with PO > 2.5 W, Clampless designs are not
5. Discontinuous mode operation (KP > 1). practical and an external RCD or Zener clamp should be
6. A suitably sized core to allow a practical transformer design used.
(see Table 2). 5. Ensure that worst-case, high line, peak drain voltage is below
7. The part is board mounted with SOURCE pins soldered the BVDSS specification of the internal MOSFET and ideally
to a sufficient area of copper to keep the SOURCE pin ≤ 650 V to allow margin for design variation.
temperature at or below 100 °C.
8. Ambient temperature of 50 °C for open frame designs VOR (Reflected Output Voltage), is the secondary output plus
and an internal enclosure temperature of 60 °C for adapter output diode forward voltage drop that is reflected to the
designs. primary via the turns ratio of the transformer during the diode
conduction time. The VOR adds to the DC bus voltage and the
LinkSwitch-LP Device leakage spike to determine the peak drain voltage.
Core Size LNK562 LNK563 LNK564
Audible Noise
EE13 1.1 W 1.4 W 1.7 W The cycle skipping mode of operation used in LinkSwitch-LP
EE16 1.3 W 1.7 W 2W can generate audio frequency components in the transformer.
To limit this audible noise generation, the transformer should
EE19 1.9 W 2.5 W 3W
be designed such that the peak core flux density is below
Table 2. Estimate of Transformer Power Capability vs. 1500 Gauss (150 mT). Following this guideline and using the
LinkSwitch-LP Device and Core Size at a Flux Density of standard transformer production technique of dip varnishing,
1500 Gauss (150 mT). practically eliminates audible noise. Vacuum impregnation
of the transformer is not recommended, as it does not provide
Below a value of 1, KP is the ratio of ripple to peak primary any better reduction of audible noise than dip varnishing. And
current. Above a value of 1, KP is the ratio of primary MOSFET although vacuum impregnation has the benefit of increased
OFF time to the secondary diode conduction time. Due to transformer capacitance (which helps in Clampless designs),
the flux density requirements described below, typically a it can also upset the mechanical design of the transformer,
LinkSwitch-LP design will be discontinuous, which also has especially if shield windings are used. Higher flux densities are
the benefit of allowing lower-cost fast (vs. ultra-fast) output possible, increasing the power capability of the transformers
diodes and reducing EMI. above what is shown in Table 2. However careful evaluation of
the audible noise performance should be made using production
Clampless Designs transformer samples before approving the design.
Clampless designs rely solely on the drain node capacitance
to limit the leakage inductance induced peak drain-to-source Ceramic capacitors that use dielectrics such as Z5U, when used
voltage. Therefore the maximum AC input line voltage, the in clamp circuits, may also generate audio noise. If this is the
value of VOR, the leakage inductance energy, (a function of case, try replacing them with a capacitor having a different
leakage inductance and peak primary current), and the primary dielectric or construction, for example a film type.
winding capacitance determine the peak drain voltage. With no
significant dissipative element present, as is the case with an Bias Winding Feedback
external clamp, the longer duration of the leakage inductance To give the best output regulation in bias winding designs, a
ringing can increase EMI. slow diode such as the 1N400x series should be used as the

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10/05 5
 LNK562-564

TOP VIEW

D FB CBP

LinkSwitch-LP
BP

Capacitor
Input Filter

Y1-
Capacitor
S S

S
Tr a n s f o r m e r S

- HV DC +
INPUT

+
DC
OUT
-
Maximize hatched copper
areas ( ) for optimum
Output Filter heatsinking
Capacitor
PI-4157-101305

Figure 6. Recommended Circuit Board Layout for LinkSwitch-LP (Assumes a HVDC Input Stage).

rectifier. This effectively filters the leakage inductance spike Primary Loop Area
and reduces the error that this would give when using fast The area of the primary loop that connects the input filter
recovery time diodes. The use of a slow diode is a requirement capacitor, transformer primary and LinkSwitch-LP together
in Clampless designs. should be kept as small as possible.

LinkSwitch-LP Layout Considerations Primary Clamp Circuit

An external clamp may be used to limit peak voltage on the
Layout DRAIN pin at turn off. This can be achieved by using an RCD
See Figure 6 for a recommended circuit board layout for clamp or a Zener (~200 V) and diode clamp across the primary
LinkSwitch-LP. winding. In all cases, to minimize EMI, care should be taken
to minimize the circuit path from the clamp components to the
Single Point Grounding transformer and LinkSwitch-LP.
Use a single point ground connection from the input filter
capacitor to the area of copper connected to the SOURCE Thermal Considerations
pins. The copper area underneath the LinkSwitch-LP acts not only as
a single point ground, but also as a heatsink. As it is connected
Bypass Capacitor (CBP) to the quiet source node, this area should be maximized for
The BYPASS pin capacitor should be located as near as possible good heat sinking of LinkSwitch-LP. The same applies to the
to the BYPASS and SOURCE pins. cathode of the output diode.

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 LNK562-564

Y Capacitor 2. Maximum drain current – At maximum ambient

The placement of the Y capacitor should be directly from the temperature, maximum input voltage and peak output
primary input filter capacitor positive terminal to the common/ (overload) power, verify drain current waveforms for any
return terminal of the transformer secondary. Such a placement signs of transformer saturation and excessive leading-edge
will route high magnitude common-mode surge currents away current spikes at startup. Repeat under steady state conditions
from the LinkSwitch-LP device. Note: If an input pi (C, L, C) and verify that the leading-edge current spike event is below
EMI filter is used, then the inductor in the filter should be placed ILIMIT(MIN) at the end of the tLEB(MIN). Under all conditions, the
between the negative terminals on the input filter capacitors. maximum DRAIN current should be below the specified
absolute maximum ratings.
Output Diode 3. Thermal Check – At specified maximum output
For best performance, the area of the loop connecting the power, minimum input voltage and maximum ambient
secondary winding, the output diode and the output filter temperature, verify that the temperature specifications
capacitor should be minimized. In addition, sufficient copper are not exceeded for LinkSwitch-LP, transformer, output
area should be provided at the anode and cathode terminals diode and output capacitors. Enough thermal margin
of the diode for heat sinking. A larger area is preferred at the should be allowed for part-to-part variation of the RDS(ON) of
quiet cathode terminal. A large anode area can increase high- LinkSwitch-LP as specified in the data sheet. Under low line and
frequency radiated EMI. maximum power, a maximum LinkSwitch-LP SOURCE pin
temperature of 100 °C is recommended to allow for these
Quick Design Checklist variations.

As with any power supply design, all LinkSwitch-LP designs Design Tools
should be verified on the bench to make sure that component
specifications are not exceeded under worst-case conditions. The Up-to-date information on design tools can be found at the
following minimum set of tests is strongly recommended: Power Integrations web site: www.powerint.com.

1. Maximum drain voltage – Verify that VDS does not exceed

650 V at the highest input voltage and peak (overload) output
power. A 50 V margin to the 700 V BVDSS specification
gives margin for design variation, especially in Clampless
designs.

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10/05 7
 LNK562-564

ABSOLUTE MAXIMUM RATINGS(1,6)

DRAIN Voltage .................................................. 700 V Notes:
Peak DRAIN Current...................................200 mA (375 mA)(2) 1. All voltages referenced to SOURCE, TA = 25 °C.
Peak Negative Pulsed Drain Current (see Fig. 10) ... 100 mA(3) 2. The higher peak DRAIN current is allowed while the
FEEDBACK Voltage .........................................-0.3 V to 9 V DRAIN voltage is simultaneously less than 400 V.
FEEDBACK Current.............................................100 mA 3. Duration not to exceed 2 µs.
BYPASS Voltage ..........................................-0.3 V to 9 V 4. Normally limited by internal circuitry.
Storage Temperature .......................................... -65 °C to 150 °C 5. 1/16 in. from case for 5 seconds.
Operating Junction Temperature(4) ..................... -40 °C to 150 °C 6. Maximum ratings specified may be applied, one at a time,
Lead Temperature(5) ........................................................260 °C without causing permanent damage to the product.
Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect product reliability.

THERMAL IMPEDANCE
Thermal Impedance: P or G Package: Notes:
(θJA) ........................... 70 °C/W(2); 60 °C/W(3) 1. Measured on pin 2 (SOURCE) close to plastic interface.
(θJC)(1) ............................................... 11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
See Figure 7
(Unless Otherwise Specified)
CONTROL FUNCTIONS
LNK562 61 66 71
Output TJ = 25 °C
fOSC Average LNK563 77 83 89 kHz
Frequency VFB =1.69 V
LNK564 93 100 107

Ratio of Output
Frequency At Auto- fOSC(AR) TJ = 25 °C, VFB = VFB(AR) 48 %
Restart to fOSC
Frequency Jitter Peak-Peak Jitter, TJ = 25 °C 5 %
Maximum Duty
DCMAX S2 Open 66 70 %
Cycle
FEEDBACK Pin
TJ = 25 °C
Turnoff Threshold IFB
See Note A
56 70 84 µA
Current
FEEDBACK Pin
TJ = 0 to 125 °C
Voltage at Turnoff VFB
See Note A
1.60 1.69 1.78 V
Threshold
VFB ≥ 2 V
IS1 (MOSFET Not Switching) 160 220 µA
DRAIN Supply See Note B
Current FEEDBACK Open
IS2 (MOSFET Switching) 220 260 µA
See Notes B, C

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8 10/05
 LNK562-564

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
See Figure 7
(Unless Otherwise Specified)
CONTROL FUNCTIONS (cont.)
BYPASS Pin ICH1 VBP = 0 V, TJ = 25 °C, See Note D -5.5 -3.3 -1.8
mA
Charge Current ICH2 VBP = 4 V, TJ = 25 °C, See Note D -3.8 -2.3 -1.0

BYPASS Pin
VBP 5.55 5.8 6.10 V
Voltage
BYPASS Pin
VBPH 0.8 0.95 1.2 V
Voltage Hysteresis
BYPASS Pin
IBPSC See Note E 84 µA
Supply Current
CIRCUIT PROTECTION
di/dt = 40 mA/µs
Current Limit ILIMIT
TJ = 25 °C
124 136 148 mA

LNK562 1099 1221 1380

di/dt = 40 mA/µs
Power Coefficient 2
If
TJ = 25 °C
LNK563 1381 1535 1735 A2Hz
LNK564 1665 1850 2091
Leading Edge TJ = 25 °C
tLEB 220 265 ns
Blanking Time See Note F

Thermal Shutdown
TSD 135 142 150 °C
Temperature
Thermal Shutdown
TSHD See Note G 75 °C
Hysteresis
OUTPUT
ON-State TJ = 25 °C 48 55
RDS(ON) ID = 13 mA Ω
Resistance TJ = 100 °C 76 88

OFF-State Drain VBP = 6.2 V, VFB ≥2 V, VDS = 560 V,

IDSS 50 µA
Leakage Current TJ = 25 °C

VBP = 6.2 V, VFB ≥2 V,

Breakdown Voltage BVDSS
See Note H, TJ = 25 °C
700 V

DRAIN Supply
50 V
Voltage
Output Enable
tEN See Figure 9 17 µs
Delay
Output Disable
tDST 0.5 µs
Setup Time
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10/05 9
 LNK562-564

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
See Figure 7
(Unless Otherwise Specified)
OUTPUT (cont.)
FEEDBACK Pin
Auto-Restart VFB(AR) TJ = 25 °C 0.8 V
Threshold Voltage
Auto-Restart VFB = VFB(AR)
100 ms
ON-Time TJ = 25 °C

Auto-Restart
DCAR 12 %
Duty Cycle

NOTES:
A. In a scheme using a resistor divider network at the FB pin, where RU is the resistor from the FB pin to the rectified
bias voltage and RL is the resistor from the FB pin to the SOURCE pin, the output voltage variation is influenced
by VFB and IFB variations. To determine the contribution from the VFB variation in percent, the following equation
can be used:
J RU + RL N
K VFB(MAX) b RL l + IFB(TYP) RU O
x = 100 # K - 1O
KK VFB(TYP) b RU + RL l + IFB(TYP) RU OO
L RL P

To determine the contribution from IFB variation in percent, the following equation can be used:

J RU + RL N
K VFB(TYP) b RL l + IFB(MAX) RU O
y = 100 # K - 1O
R
KK VFB(TYP) b U + R L OO
L RL l + IFB(TYP) RU P

Since IFB and VFB are independent parameters, the composite variation in percent would be ! x 2 + y 2 .

B. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is ≥2 V (MOSFET not
switching) and the sum of IS2 and IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching).

C Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BYPASS pin current at 6 V.

D. See Typical Performance Characteristics section Figure 15 for BYPASS pin start-up charging waveform.

E. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK
pins and not any other external circuitry.

F. This parameter is guaranteed by design.

G. This parameter is derived from characterization.

H. Breakdown voltage may be checked against minimum BVDSS by ramping the DRAIN pin voltage up to but not
exceeding minimum BVDSS.

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10 10/05
 LNK562-564

470 Ω
5W 470 kΩ
D FB
S1 S2
BP
50 V 50 V
S S 0.1 µF
S S

PI-3490-060204

Figure 7. General Test Circuit.

DCMAX
(internal signal)
tP

FB

tEN
VDRAIN

1
t =
P fOSC
PI-3707-112503

Figure 8. Duty Cycle Measurement. Figure 9. Output Enable Timing.

PI-4021-101305
DRAIN Current (mA)

100

2 µs

-100

Time (µs)

Figure 10. Peak Negative Pulsed DRAIN Current

Waveform.

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 LNK562-564

Typical Performance Characteristics

1.1 1.2

PI-2680-012301
PI-2213-012301
1.0

(Normalized to 25 °C)
(Normalized to 25 °C)
Breakdown Voltage

Output Frequency
0.8

1.0 0.6

0.4

0.2

0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
Junction Temperature (°C) Junction Temperature (°C)
Figure 11. Breakdown vs. Temperature. Figure 12. Frequency vs. Temperature.

1.4 1.1
PI-4164-100505

PI-4057-071905
1.2 FEEDBACK Pin Voltage
(Normalized to 25 °C)

(Normalized to 25 °C)
1.0
Current Limit

0.8
1.0
0.6

0.4

0.2

0 0.9
-50 0 50 100 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)
Figure 13. Current Limit vs. Temperature. Figure 14. FEEDBACK Pin Voltage vs. Temperature.

7 200
PI-3927-083104
PI-2240-012301

6 175
BYPASS Pin Voltage (V)

25 °C
DRAIN Current (mA)

5 150
100 °C

4 125

3 100

2 75

1 50

0 25

0
0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 12 14 16 18 20
Time (ms) DRAIN Voltage (V)
Figure 15. BYPASS Pin Start-up Waveform. Figure 16. Output Characteristics.

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Typical Performance Characteristics (cont.)

1000

PI-3928-083104
Drain Capacitance (pF)
100

10

1
0 100 200 300 400 500 600
Drain Voltage (V)
Figure 17. COSS vs. Drain Voltage.

PART ORDERING INFORMATION

LinkSwitch Product Family
LP Series Number
Package Identifier
G Plastic Surface Mount DIP
P Plastic DIP
Lead Finish
N Pure Matte Tin (Pb-Free)
Tape & Reel and Other Options
Blank Standard Configurations
LNK 562 G N - TL TL Tape & Reel, 1000 pcs minimum, G package only

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DIP-8B
⊕ D S .004 (.10) .137 (3.48) Notes:
-E- MINIMUM 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
3. Dimensions shown do not include mold flash or other
.240 (6.10)
protrusions. Mold flash or protrusions shall not exceed
.260 (6.60)
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 6 is omitted.
Pin 1 5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
.367 (9.32) 6. Lead width measured at package body.
-D- 7. Lead spacing measured with the leads constrained to be
.387 (9.83)
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM
-T-
SEATING .008 (.20)
PLANE .120 (3.05) .015 (.38)
.140 (3.56)
.300 (7.62) BSC
.100 (2.54) BSC .048 (1.22) (NOTE 7)
.014 (.36)
.053 (1.35) .300 (7.62) P08B
.022 (.56) ⊕ T E D S .010 (.25) M .390 (9.91) PI-2551-121504

SMD-8B
⊕ D S .004 (.10) .137 (3.48) Notes:
MINIMUM 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
protrusions shall not exceed
.372 (9.45) .006 (.15) on any side.
.240 (6.10)
.388 (9.86) .420
.260 (6.60) 3. Pin locations start with Pin 1,
⊕ E S .010 (.25) and continue counter-clock-
.046 .060 .060 .046 wise to Pin 8 when viewed
from the top. Pin 6 is omitted.
4. Minimum metal to metal
.080 spacing at the package body
Pin 1 Pin 1
for the omitted lead location
.086 is .137 inch (3.48 mm).
.100 (2.54) (BSC)
.186 5. Lead width measured at
package body.
.286
.367 (9.32) 6. D and E are referenced
-D- Solder Pad Dimensions datums on the package
.387 (9.83)
body.
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)

.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0°- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08B
PI-2546-121504

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Revision Notes Date

E 1) Final Release Data Sheet 10/05
F 2) Revision of PI-3924 10/05

For the latest updates, visit our website: www.powerint.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume
any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY
DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

PATENT INFORMATION
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S.
and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents
may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm.
LIFE SUPPORT POLICY
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform,
when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, EcoSmart, Clampless, E-Shield, Filterfuse,
PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©Copyright 2005, Power Integrations, Inc.

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Rm 2206-2207, Block A, Via Vittorio Veneto 12 51 Newton Road World Wide +1-408-414-9660
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Shenzhen, Guangdong, Phone: +39-028-928-6000 Phone: +65-6358-2160 World Wide +1-408-414-9760
China, 518031 Fax: +39-028-928-6009 Fax: +65-6358-2015
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