Lytswitch-6 Family: Flyback CV/CC Led Driver Ic With Integrated 650 V / 725 V Mosfet and Fluxlink Feedback
Lytswitch-6 Family: Flyback CV/CC Led Driver Ic With Integrated 650 V / 725 V Mosfet and Fluxlink Feedback
Lytswitch-6 Family: Flyback CV/CC Led Driver Ic With Integrated 650 V / 725 V Mosfet and Fluxlink Feedback
Product Highlights
Highly Integrated, Compact Footprint
• Up to 94% efficiency across full load range SR FET
• Incorporates a multi-mode Quasi-Resonant (QR) / CCM / DCM flyback
controller, 650 V or 725 V MOSFET, secondary-side control and
synchronous rectification driver
• Integrated FluxLink™, HIPOT-isolated, feedback link
• Exceptional CV/CC accuracy, independent of transformer design or
FWD
GND
BPS
SR
FB
D V
external components LYTSwitch-6
• Adjustable accurate output current sense using external sense resistor Optional
Primary FET VOUT
Current
and Controller
EcoSmart™ – Energy Efficient Sense
S BPP IS Secondary
• Less than 15 mW no-load including line sense (without PF front end)
Control IC
• Designs using LYTSwitch-6 easily meet Energy Star and all global
lighting energy efficiency regulations
PI-8375-072817
• Low heat dissipation
Figure 1. Typical Application/Performance.
Advanced Protection / Safety Features
• Input line OV with auto-restart
• Output fault OVP/UVP with auto-restart
• Open SR FET gate detection
• Input voltage monitor with accurate brown-in
• Thermal foldback ensures that power continues to be delivered
(lower level) at elevated temperatures
Green Package
• Halogen free and RoHS compliant Output Power Table
Applications 380 VDC /
277 VAC ± 15% 85-305 VAC
450 VDC 2
• Isolated off-line LED driver Product 3
PRIMARY BYPASS
REGULATOR
ENABLE
ENABLE
FAULT
AUTO-RESTART
PRIMARY
GATE LINE COUNTER
BPP/UV BYPASS PIN
INTERFACE RESET
PRIMARY UNDERVOLTAGE
BPP/UV BYPASS PIN
PRIM-CLK +
CAPACITOR
OV SELECT AND -
CURRENT VSHUNT
OSCILLATOR/ LIMIT VILIM VBP+
GATE
TIMERS JITTER
tON(MAX) tOFF(BLOCK)
THERMAL GATE
SHUTDOWN
GATE OV PRIM/SEC
FAULT SecREQ
BPP From
AUTO-RESTART
SenseFET SecPulse Secondary
Power PRIM/SEC Controller
Q S
MOSFET
Q R Sec- RECEIVER
DRIVER
FAULT CONTROLLER
LEB BPP/UV tOFF(BLOCK)
IS
ILIM PRIM-CLK
+
AUTO-RESTART
VILIM - PRIMARY OVP
tON(MAX)
PI-8388-020618
SOURCE
(S)
SR CONTROL
FORWARD REGULATOR
4.4 V
INH
ENABLE BPSUV SECONDARY
VOUT SR BYPASS
(BPS)
+
-
DETECTOR S Q 4.4 V
3.8 V
+ R Q
SR
THRESHOLD
QR
HANDSHAKE/
SECONDARY
FAULT DETECTION
CONTROL INH OVP
DCM
To FEEDBACK
Primary (FB)
Receiver FEEDBACK INH +
DRIVER - VREF
QR
FEEDBACK
COMPENSATION
TsMAX
+
-
tOFF(MIN) THERMAL
tSECINH(MAX) FOLDBACK
OSCILLATOR/
TIMER
tSS(RAMP)
SECONDARY ISENSE
GROUND (IS)
(GND)
PI-8045e-020618
2
Rev. E 02/18 www.power.com
LYTSwitch-6
Input Overvoltage (V) Pin (Pin 13) The primary controller on LYTSwitch-6 is a Quasi-Resonant (QR)
A high-voltage pin connected to the AC or DC side of the input bridge flyback controller that has the ability to operate in continuous
for detecting overvoltage conditions at the power supply input. This conduction mode (CCM). The controller uses both variable frequency
pin should be tied to Source to disable OV protection. and variable current control schemes. The primary controller consists
of a frequency jitter oscillator; a receiver circuit magnetically coupled
PRIMARY BYPASS (BPP) Pin (Pin 14) to the secondary controller, a current limit controller, 5 V regulator on
The connection point for an external bypass capacitor for the the PRIMARY BYPASS pin, audible noise reduction engine for light load
primary-side supply. This is also the ILIM selection pin for choosing operation, bypass overvoltage detection circuit, a lossless input line
standard ILIM or ILIM+1. sensing circuit, current limit selection circuitry, over-temperature
protection, leading edge blanking, and a 650 V / 725 V power MOSFET.
NC Pin (Pin 15)
Leave open. Should not be connected to any other pins. The LYTSwitch-6 secondary controller consists of a transmitter circuit
SOURCE (S) Pin (Pin 16-19) that is magnetically coupled to the primary receiver, a constant
voltage (CV) and a constant current (CC) control circuit, a 4.4 V
These pins are the power MOSFET source connection. It is also
regulator on the secondary SECONDARY BYPASS pin, synchronous
ground reference for primary BYPASS pin.
rectifier MOSFET driver, QR mode circuit, oscillator and timing
DRAIN (D) Pin (Pin 24) functions, thermal foldback control and a host of integrated
Power MOSFET drain connection. protection features.
3
www.power.com Rev. E 02/18
LYTSwitch-6
PI-8205-120516
The LYTSwitch-6 features variable frequency QR controller + CCM
operation for enhanced efficiency and extended output power 1.0
4
Rev. E 02/18 www.power.com
LYTSwitch-6
5
www.power.com Rev. E 02/18
LYTSwitch-6
As an additional safety measure the primary will pause for an The secondary controller temporarily inhibits the FEEDBACK short
auto-restart on-time, t AR (~82 ms), before switching. During this protection threshold (VFB(OFF)) until the end of the soft-start (tSS(RAMP))
“wait” time, the primary will “listen” for secondary requests. If it sees timer. After hand-shake is completed the secondary controller
two consecutive secondary requests, separated by 30 ms, the primary linearly ramps up the switching frequency from fSW to fSREQ over the
will enter secondary control and begins switching in slave mode. If tSS(RAMP) time period.
no such pulses occur during the t AR “wait” period, the primary will
In the event of a short-circuit or overload at start-up, the device will
begin switching under primary control until handshake pulses are
regulate directly into CC (constant-current mode). The device will go
received.
into auto-restart (AR), if the output voltage does not rise above the
Audible Noise Reduction Engine VO(AR) threshold before the expiration of the soft start timer (tSS(RAMP))
The LYTSwitch-6 features and active audible noise reduction mode after handshake has occurred.
wherein the controller (via a “frequency skipping” mode of operation)
avoids the resonant band (where the mechanical structure of the The secondary controller enables the FEEDBACK pin short protection
power supply is most likely to resonate - increasing noise amplitude) mode (VFB(OFF)) at the end of the tSS(RAMP) time period. If the output
between 7 kHz and 12 kHz ‒ 142 ms and 83 ms. If a secondary short maintains the FEEDBACK pin to be below short-circuit threshold
controller request occur within this window from the last conduction the secondary will stop requesting pulses to trigger an auto-restart
cycle, the gate drive of the power MOSFET is inhibited. cycle.
Secondary Controller If output voltage reaches regulation within the tSS(RAMP) time period,
the frequency ramp is immediately aborted and the secondary
As shown in the block diagram in Figure 4, the IC is powered through controller is permitted to go full frequency. This will allow the
regulator 4.4 V (VBPS) by either VOUT or FW. The SECONDARY controller to maintain regulation in the event of a sudden transient
BYPASS pin is connected to an external decoupling capacitor and fed loading soon after regulation is achieved. The frequency ramp will
internally from the regulator block. only be aborted if quasi-resonant detection programming has already
The FORWARD pin also connects to the negative edge detection occurred.
block used for both handshaking and timing to turn on the SF FET Maximum Secondary Inhibit Period
connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The Secondary-cycle requests to initiate primary switching are inhibited to
FORWARD pin voltage is used to determine when to turn off the maintain operation below maximum frequency and ensure minimum
SF FET in discontinuous mode operation. This is when the voltage off-time. Besides these constraints, secondary-cycle requests are
across the RDS(ON) of the SR FET drops below zero volts. also inhibited during the “ON” time cycle of the primary switch (time
between the cycle request and detection of FORWARD pin falling
In continuous conduction mode (CCM) the SR FET is turned off when
edge). The maximum time-out in the event a FORWARD pin falling
the feedback pulse is sent to the primary to demand the next
edge is not detected after a cycle requested is ~30 ms.
switching cycle, providing excellent synchronous operation, free of
the any overlap for the FET turn-off. Thermal Foldback
When the secondary controller die temperature reaches 124 °C, the
The mid-point of an external resistor divider network between the output power is reduced by reducing the constant current reference
OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the threshold (see Figure 8).
FEEDBACK pin to regulate the output voltage. The internal voltage
comparator reference voltage is VREF (1.265 V).
6
Rev. E 02/18 www.power.com
LYTSwitch-6
7
www.power.com Rev. E 02/18
LYTSwitch-6
PI-8569-010318
FORWARD Pin Voltage
Request Window
Output Voltage
Time
Primary VDS
Time
8
Rev. E 02/18 www.power.com
LYTSwitch-6
Application Example
C12
3.3 nF
250 VAC
C16 C18
L3 D16 100 µF 100 µF
560 µH S1J-13-F T2
100 V 100 V 80 V, 580 mA
1 RM10 FL1
TP3
R48 C14
C9 100 Ω 100 pF R29
D1 1000 pF R17 1/2 W 1 kV
ES2_J_LTP 510 kΩ 102 kΩ C37
630 V 1% 1.5 nF
1/8 W 200 V
VR1 D10
9 BZD27C200P STTH3R06S
200 V 600 V
R4 2 FL2
2.0 MΩ
T1 FL4
R46
EE13 VR2 20 Ω
BZD27C200P D8 C15
200 V DFLR1600-7 10 µF
600 V 25 V
FL3
5 7 D11 R30
DFLU1400-7 1.62 kΩ
BR1 1%
D17 5 1/16 W
UD4KB100 ES2J-LTP
1000 V
R22
TP1 47 Ω
L2 4
1
20 mH 3 C2 C3
C1 220 nF 330 nF
90 - 265 RV1 100 nF 450 V 450 V
VAC 275 VAC 630 VDC
F1 2 4 C19
3.15 A 330 pF
50 V
TP2
C13
2.2 µF
C4 25 V
R47 68 µF
4.7 kΩ R45
450 V 2.00 MΩ
1%
R24
D7 6.2 Ω
FWD
GND
DFLR1200-7
BPS
1%
SR
FB
200 V D V
CONTROL R43
VOUT 0.062 Ω
1%
R18 1/2 W
10 kΩ S BPP IS
LYTSwitch-6
C10 C11 U4
22 µF 4.7 µF LYT6068C D13
16 V 50 V US1B RTN
PI-8576-012618 TP4
Figure 10. Schematic DER-657, 46.4 W, 80 V, 0.58 A for Universal External LED Driver Application.
The circuit shown on Figure 10 is a 46 W isolated flyback power caused by the transformer leakage inductance. The RCD primary
supply with a single-stage power factor correction circuit for LED clamp also reduces radiated and conducted EMI.
lighting applications. It provides an accurately regulated 80 V, 580 mA
In order to provide line overvoltage detection, the bulk capacitor
output for multi-LED-string applications where a post regulator is
voltage is sensed and converted into a current by the INPUT
used − such as in RGBW smart-lighting fixtures. The design is also
VOLTAGE pin resistors R4 and R45. The INPUT VOLTAGE pin line
ideal for single string applications as it also provides a constant
overvoltage threshold current (IOV-) determines the input overvoltage
580 mA output current with accurate regulation and no line-induced
shutdown point.
ripple across a load-voltage range of 80 V to 20 V. The circuit is
highly efficient offering accurate load regulation and is stable over The LYTSwitch-6 IC is self-starting, using an internal high-voltage
line (90 VAC to 265 VAC). The circuit also delivers a PF of greater current source to charge the PRIMARY BYPASS pin capacitor (C11)
than 0.9 with less than 20% A-THD (measured at 230 VAC). when AC is first applied. During normal operation the primary-side
circuitry is powered from an auxiliary winding on transformer T2.
Input Stage
A value of 4.7 µF was selected for the BPP capacitor (C11) to select
Fuse F1 provides open-circuit protection which isolates the circuit
increased-current-limit operation. During normal operation the
from the input line in the event of catastrophic component failures.
output of the auxiliary (bias) winding is rectified using diode D7 and
Varistor RV1 clamps any voltage spikes to protect the circuitry located
filtered using capacitor C10. Resistor R18 limits the current being
after the fuse from damage due to overvoltage caused by a line
supplied to the PRIMARY BYPASS pin.
transient or surge. Bridge diode BR1 rectifies the AC line voltage and
provides a full-wave rectified DC voltage across the input film capacitors Power Factor Correction Stage
C2 and C3. The EMI filter is a 2-stage LC circuit comprising C1, L2, The Power Factor Correction circuit comprises an inductor (T1) in
C2, L3, and C3 and suppress differential and common mode noise series with blocking diodes (D1 and D17) and is connected to the
generated from the PFC and flyback switching stages. DRAIN pin of the LYTSwitch-6 IC. High PF is achieved using a
Switched Valley-Fill Single Stage PFC (SVF S2PFC) circuit operating in
Primary Flyback Stage
discontinuous conduction mode (DCM). In DCM the switched current
The bulk capacitor C4 completes the input stage. It filters the line
from inductor T1 shapes the input current waveform to create a
ripple voltage and provides energy storage. This component also
quasi-sinusoid when the rectified voltage on C3 is less than the DC
filters differential current, further reducing conducted EMI. The input
voltage on C4, this results in a high power factor.
stage provides a DC voltage to the flyback converter. One end of the
primary winding of transformer (T2) is connected to the positive During MOSFET on-time, energy is stored in the PFC inductor (T1)
terminal of the bulk capacitor (C4) while the other is connected to the and the leakage inductance of the flyback transformer (T2). During
DRAIN pin of the integrated 650 V power MOSFET in the LYTSwitch-6 MOSFET off-time, the energy from both the PFC and flyback inductors
IC (U1). A low-cost RCD primary clamp made up of D8, R46, R17 and is transferred to the secondary-side through the flyback transformer
C9 limits the voltage spike developed across the MOSFET that is T2. Diode D16 isolates the rectified AC input on C3 from C4 and
9
www.power.com Rev. E 02/18
LYTSwitch-6
provides current path for the charging of the bulk capacitor C4 − 2. Efficiency assumptions depend on power level. Smallest device-
especially at low-line, which improves efficiency. Free-wheel diodes power levels assume efficiency >84% increasing to >89% for the
D1 and D17 provide a current path for the energy stored in the PFC largest device.
inductor that must be transferred to the secondary-side during 3. Transformer primary inductance tolerance is ±10%.
MOSFET off-time. The series connection of D1 and D17 are able to 4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at
withstand the resonant voltage ring from the PFC inductor when the minimum input voltage for universal line, and KP = 1 for high
MOSFET turns off. input line (only) designs.
During a no-load or light load condition (<10% load) the energy
5. Maximum conduction loss for adapters is limited to 0.6 W and to
0.8 W for open frame designs.
stored in the PFC inductor is greater than required by the secondary
load. The excess energy from the PFC inductor is therefore recycled
6. Increased current limit is selected for peak and open-frame power
columns, while standard current limit is used for adapter columns.
to the bulk capacitor C4 boosting the voltage level. A Zener-resistor
clamp comprising of VR1 and VR2 in series with R47 is connected
7. The part is board-mounted with SOURCE pins soldered to a
sufficient area of copper and/or a heat sink to keep the SOURCE-
across the bulk capacitor C4 to clamp this voltage below the
pin temperature ≤110 °C.
voltage-rating of C4. This Zener clamp voltage should be ≤450 V
(the maximum voltage rating of bulk capacitor C4). In the event of
8. Ambient temperature limit is 50 °C for open frame designs and
40 °C for sealed adapters.
an input line surge or transient event, the primary switching MOSFET
is protected from overvoltage by the INPUT VOLTAGE pin sense
9. Below a value of 1, KP is the ratio of ripple to peak primary
current. To prevent reduced power delivery, due to premature
resistors which trigger a line overvoltage shutdown at 460 V.
termination of switching cycles, a transient KP limit of ≥0.6 is
Secondary Stage specified. This prevents the initial current limit (IINT) from being
The secondary-side control of the LYTSwitch-6 IC provides constant exceeded at MOSFET turn-on.
output voltage and constant output current. The voltage produced 10. LYTSwitch-6 parts are unique in that the designer can set the
on the secondary winding of transformer T2 is rectified by D10 and switching frequency between 25 kHz to 95 kHz by adjusting
filtered by the output capacitors C16 and C18. Adding an RC snubber transformer design. One way to lower device temperature is to
(R48 and C14) across the output diode reduces voltage stress. In this design the transformer to reduce switching frequency; a good
design, the SYNCHRONOUS RECTIFIER DRIVE pin is connected to starting point is 50 kHz.
the SECONDARY GROUND pin to allow the use of a low-cost ultrafast
Primary-Side Overvoltage Protection
output diode instead of an SR FET.
Primary-side output overvoltage protection provided by the
The IC secondary is self-powered from either the secondary winding LYTSwitch-6 IC uses an internal latch that is triggered by a threshold
forward voltage via the FORWARD pin, or the output voltage via the current of ISD into the PRIMARY BYPASS pin. For the bypass capacitor
OUTPUT VOLTAGE pin. Decoupling capacitor C13 is connected to the to be effective as a high frequency filter, the capacitor should be
SECONDARY BYPASS pin. In order to meet the maximum voltage located as close as possible to the SOURCE and PRIMARY BYPASS
limits of OUTPUT VOLTAGE pin in this design, the secondary-side of pins of the device.
the IC needs to be powered from a low voltage auxiliary supply
The primary sensed OVP function can be realized by connecting a
(winding FL3 and FL4). The FORWARD pin has to be connected to
series combination of a Zener diode, a resistor and a blocking diode
the same output to insure good regulation and high efficiency. This
from the rectified and filtered bias-winding-voltage supply to the
auxiliary supply is rectified and filtered by D11 and C15 respectively.
PRIMARY BYPASS pin (see Figure 11-a). The rectified and filtered bias
During constant voltage operation, output voltage regulation is winding output voltage may be higher than anticipated (up to
achieved by sensing the output voltage via a resistor network 2 times the desired value) and is dependent on the coupling of the
comprising R29 and R30. The voltage across R30 is monitored at bias winding to the output winding and the resultant ringing of the
the FEEDBACK pin and compared to an internal reference voltage bias winding voltage waveform. It is recommended that the rectified
threshold of 1.265 V. Bypass capacitor C19 is placed across the bias winding voltage be measured. Ideally this measurement should
FEEDBACK and SECONDARY GROUND pins to attenuate high be made at the lowest input voltage and with maximum load applied
frequency noise that would otherwise couple to the feedback signal the output. This measured voltage should be used to select the
and cause unwanted behavior such as pulse bunching. components required to achieve primary sensed OVP. It is
During constant current operation, the maximum output current is set recommended that a Zener diode is selected with a clamping voltage
by the sense resistors R43 and R24. The voltage across the sense approximately 6 V lower than the rectified bias winding voltage at
resistor is applied to the ISENSE pin internal reference threshold which OVP is expected to be triggered. A forward voltage drop of 1 V
of 35 mV to maintain constant current regulation. Diode D13 in can be assumed for the blocking diode. A small-signal standard
parallel with the current sense resistors clamps the voltage across the recovery diode is recommended for this task. The blocking diode
ISENSE and SECONDARY GROUND pin. This shunts the high current prevents any reverse current from charging the bias capacitor during
surge from the output capacitor seen during an output short-circuit start-up. Finally, the value of the series resistor required can be
and prevents damage. calculated such that a current higher than ISD will flow into the
PRIMARY BYPASS pin during an output overvoltage event.
Key Applications Design Considerations
Secondary-Side Overvoltage Protection
Output Power Table Secondary-side output overvoltage protection is provided by the
The output power table (Table 1) represents the maximum LYTSwitch-6 IC which uses an internal auto-restart circuit triggered
continuous output power level that can be obtained under the by an input current into the SECONDARY BYPASS pin exceeding a
following conditions: threshold of IBPS(SD). The direct sensed output OVP function can
1. Minimum DC input voltage is ≥90 V for 85 VAC input and ≥220 V be realized by connecting a Zener diode from the output to the
for 230 VAC input (or 115 VAC with a voltage doubler). The SECONDARY BYPASS pin. The Zener diode voltage needs to be the
voltage rating of the input capacitor should be set to meet these absolute value of (1.25 x VOUT) – (4.4 V − SECONDARY BYPASS pin
criteria.
10
Rev. E 02/18 www.power.com
LYTSwitch-6
CBIAS RZ
FB
VZ
DB
CBPS
CIN RZ
FWD
GND
BPS
D V
SR
FB
VRZ LYTSwitch-6
RBP LYTSwitch-6
Primary FET
DB and Controller Secondary
Control IC
S BPP IS
PI-8579-011218 RTN
PI-8580-012318
a. Primary-side OVP with High Current Pushed into BPP via Zener VZ. b. Secondary-side OVP with High Current Pushed into BPS via Zener V Z and
Resistor R Z.
CY
RFB(UPPER) VOUT
+VBULK
CFB CPH
RSN CSN CSR RSR COUT
RPH
RS DSN
RLS1 RFB(LOWER)
SR FET
DBIAS
CBIAS
CBPS
RFWD
C2
RLS
FWD
GND
BPS
SR
FB
LYTSwitch-6 D V
S BPP IS Secondary
Control IC
RBP
(-) CBPP
PI-8581-012318 RTN
Figure 12. Typical Schematic of LYTSwitch-6 Flyback Power Supply (DC-DC Stage)
voltage). It is necessary to add a low value resistor, in series with the Selecting Critical External Components
OVP Zener diode to limit the maximum current into the SECONDARY The schematic in Figure 12 shows the essential external components
BYPASS pin (see Figure 11-b. required for a working single output LYTSwitch-6 based power supply.
The selection criteria for these components is as follows:
11
www.power.com Rev. E 02/18
LYTSwitch-6
Primary-Side Components To ensure minimum no-load input power and high full load efficiency,
resistor RBP (Figure 12) should be selected such that the current
PRIMARY BYPASS Pin Capacitor (CBPP) through this resistor is higher than the PRIMARY BYPASS pin supply
This capacitor works as the supply decoupling capacitor for the current.
internal primary-side controller and also determines current limit for
the internal MOSFET. 4.7 µF or 0.47 µF capacitance will select The PRIMARY BYPASS pin supply can be calculated as shown below;
INCREASED or STANDARD current limits respectively. Though
I SSW = b 132 K l # ^ I S2 - I S1 h + I S1
fSW
electrolytic capacitors can be used, often surface mount multi-layer
ceramic capacitors are preferred for use on double-sided boards as
they allow the capacitors to be placed close to the IC. A surface Where;
mount multi-layer ceramic X7R capacitor rated for 25 V is therefore ISSW: PRIMARY BYPASS pin supply current at operating switching
recommended. frequency
Line Overvoltage / Brown-In Sense Resistor (RLS) fSW: Operating switching frequency (kHz)
Both line overvoltage and brown-in voltage are sensed by the INPUT IS1: Non-switching PRIMARY BYPASS pin supply current (refer to
VOLTAGE pin. The current from the DC input bus is monitored via data sheet specification tables)
resistor RLS and compared to an internal current threshold. IS2: PRIMARY BYPASS pin supply current at 132 kHz (refer to
data specification sheet)
Typical value range for RLS is in the range of 3.8 MΩ to 4 MΩ. RLS is
approximately equal to VLOV × 1.414 / IOV-. The PRIMARY BYPASS pin voltage will be ~5.3 V if the bias current is
higher than PRIMARY BYPASS pin supply current. A PRIMARY
VLOV is the input line voltage at which the power supply will stop
BYPASS pin voltage of ~5.0 V, indicates that the current through
switching because the overvoltage threshold (IOV-) is exceeded.
RBP is less than the PRIMARY BYPASS pin supply current and the IC is
Switching will be re-enabled when line overvoltage hysteresis (IOV(H))
drawing current from the DRAIN pin. Ensure that the voltage on the
is reached. Line OV (VLOV) is approximately equal to IOV- × RLS / 1.414.
PRIMARY BYPASS pin never falls below 5.3 V − except during start-up.
The power supply will turn on once the brown-in threshold (IUV+) is
To determine maximum value of RBP;
exceeded. Brown-in voltage is approximately equal to IUV+ x RLS /
R BP = 6V BIAS ^ NO - LOAD h - V BPP @ /I SSW;
1.414.
External Bias Supply Components (DBIAS, CBIAS, RBP)
The LYTSwitch-6 IC has an internal bypass regulator from the where VBPP = 5.3 V.
DRAIN pin of the primary-side MOSFET to the PRIMARY BYPASS pin.
This internal regulator is active during the MOSFET off-time and Clamp Network Across Primary Winding
keeps the PRIMARY BYPASS pin voltage from dropping below 5 V. (DSN, RS, RSN, and C SN)
This ensures that the IC will operate normally especially during Figure 13, shows the low cost R2CD clamp which is used in most low
start-up time. During start-up, the IC is powered from the internal power circuits. For higher power designs, a Zener clamp or an R2CD
regulator. When the output voltage has risen sufficiently, the primary plus Zener clamp can be used to achieve better efficiency. It is
controller will draw power from the external bias supply via the advisable to limit the peak Drain voltage to 90% of BVDSS under worst-
auxiliary winding rather than from the internal tap. This will reduce case conditions (maximum input voltage, maximum overload power or
energy consumption as the auxiliary supply is at much lower voltage output short-circuit). The clamp diode, DSN shown in Figure 13 must
than the tap (which is driven by the high-voltage of the DRAIN pin). be either a standard recovery glass passivated diode or a fast
If the coupling between the bias winding and secondary winding is recovery type with a reverse recovery time of less than 500 ns. Use
poor, the bias supply voltage may can drop significantly during of standard recovery glass passivated diodes allows the recovery of
no-load operation and may not be able to supply current to the some of the clamp energy from each cycle and improves average
PRIMARY BYPASS pin and keep the internal regulator off. If this efficiency. The diode momentarily conducts each time the primary
condition causes the internal tap to turn on, no-load power switching MOSFET inside the LYTSwitch-6 IC turns off and energy
consumption will increase. It is therefore recommended that the bias from the leakage reactance is transferred to the clamp capacitor CSN.
voltage be set close to the maximum of 12 V. Higher voltage may Resistor RS, which is in the series path, acts as a damper preventing
also increase no-load power consumption. For the bias supply, there excessive ringing due to resonance between the leakage reactance
is a trade-off between using a standard-recovery diode and a fast and the clamp capacitor CSN. Resistor RS dissipates the energy stored
signal diode for the bias winding rectifier diode, DBIAS. The standard in capacitor CSN. Designs employing different sized LYTSwitch-6
recovery diode will tend to give lower radiated EMI while the fast devices will have different peak primary currents and leakage
diode will reduce no-load power consumption. Since LYTSwitch-6 ICs inductances and will therefore result in different amounts of leakage
inherently use very little power, it is recommended that the standard energy. Capacitor CSN, RSN and RS must therefore be optimized for
recovery diode is used for the bias supply, trading a small increase in each design. As a general rule the value of capacitor CSN should be
power dissipation for improved EMI performance. minimized and the value of resistors RSN and RS maximized, while still
A 22 µF 50 V low ESR aluminum electrolytic capacitor is recommended meeting the 90% derating of the BVDSS limit. RS should be
for the bias supply filter, CBIAS. A low ESR electrolytic capacitor sufficiently large to damp the ring, but small enough to prevent the
reduces no-load power consumption. Use of a ceramic surface mount drain voltage from rising too far. A ceramic capacitor that uses a
capacitor is not recommended as this may cause audible noise due to dielectric such as Z5U if used as the CSN capacitor in the clamp circuit
piezoelectric excitation of the ceramic capacitors mechanical may generate audible noise, so the use of a polyester film type
structure. capacitor is preferred.
12
Rev. E 02/18 www.power.com
LYTSwitch-6
RSN
RSN CSN VRCLAMP VRCLAMP
DCLAMP CSN DCLAMP
Rs DCLAMP RS RS
D D D
Secondary-Side Components Driving LYTSwitch-6 not be used. Care must be taken to ensure that the voltage at the
FORWARD pin never exceeds its absolute maximum voltage rating.
SECONDARY BYPASS Pin Capacitor (CBPS)
If the FORWARD pin voltage exceeds the FORWARD pin absolute
This capacitor works as a voltage supply decoupling capacitor for the
maximum voltage, the IC will be damaged.
integrated secondary-side controller. A surface mount, 2.2 µF, 25 V,
multi-layer ceramic capacitor is recommended for this application. FEEDBACK Pin Divider Network (RFB(UPPER), RFB(LOWER))
The SECONDARY BYPASS pin voltage needs to reach 4.4 V before the A suitable resistive voltage divider should be connected from the
output voltage reaches its target voltage. A significantly higher value output of the power supply to the FEEDBACK pin of the LYTSwitch-6
of SECONDARY BYPASS pin capacitor may prevent this from occurring IC and sized such that at the desired output voltage, the FEEDBACK
and induce an output voltage overshoot during start-up. Values lower pin will be at 1.265 V. A decoupling capacitor (CFB) of 330 pF is
than 1.5 µF may not be provide sufficient energy storage, leading to recommended and should be connected from the FEEDBACK pin to
unpredictable device operation. The capacitor must be located SECONDARY GROUND pin. CFB acts as a decoupling capacitor for the
adjacent to the IC pins. The capacitance of ceramic capacitors drops FEEDBACK pin to prevent switching noise from affecting IC operation.
with applied voltage and the 25 V rating is therefore necessary to SR MOSFET Operation and Selection
guarantee sufficient minimum capacitance during operation. For this Although a simple diode rectifier and snubber is effective, the use
reason capacitors rated for 10 V are not recommended. Capacitors of a SR FET significantly improves efficiency. The secondary-side
with X5R or X7R dielectrics provide the best results. controller turns the SR FET on at the beginning of the flyback cycle.
FORWARD Pin Resistor (RFWD) The gate of the SR FET should be tied directly to the SYNCHRONOUS
The FORWARD pin is connected to the drain terminal of the RECTIFIER DRIVE pin of the LYTSwitch-6 IC (no additional resistors
synchronous rectifier MOSFET (SR FET). This pin is used to monitor should be connected to the gate drive of the SR FET). The SR FET is
the Drain voltage of the SR FET to precisely control turn-on and turned off when its VDS reaches 0 V. The SR FET driver uses the
turn-off of the device. This pin is also used to charge the SECONDARY SECONDARY BYPASS pin as its supply rail; this voltage is typically 4.4 V.
BYPASS pin capacitor whenever the output voltage falls below the A FET with a high gate threshold voltage is not therefore appropriate
SECONDARY BYPASS pin voltage. The use of a 47 Ω, 5% resistor is for this application; FETs with a threshold voltage of 1.5 − 2.5 V are
recommended to ensure sufficient IC supply current and works well ideal. MOSFETs with a threshold voltage as high as 4 V may also be
across a wide range of output voltages. A different resistor value will used provided that the data sheet specifies RDS(ON) across temperature
interfere with the timing of the synchronous rectifier drive and should for a gate voltage of 4.5 V.
13
www.power.com Rev. E 02/18
LYTSwitch-6
There is a short delay between the start of the flyback cycle and the PCB Layout Recommendations
turn-on of the SR FET. During this time, the body diode of the
SR FET will conduct. If an external Schottky diode is connected in Single-Point Grounding
parallel, current flows mostly through the Schottky diode. A parallel Use a single-point ground connection from the input filter capacitor to
Schottky diode will therefore increase efficiency. A 1 A surface- the area of copper connected to the SOURCE pin. See Figure 14.
mount Schottky diode is usually adequate for this task; however the
Bypass Capacitors
gains are modest, for a 5 V, 2 A design the external diode adds
The PRIMARY BYPASS (CBPP) pin, SECONDARY BYPASS (CBPS) pin and
~0.1% to full load efficiency at 85 VAC and ~0.2% at 230 VAC.
feedback decoupling capacitors must be located adjacent to and
The voltage rating of the Schottky diode and the SR FET should be at between those pins and their respective returns with short traces.
least 1.3 times the expected peak inverse voltage (PIV) calculated
PRIMARY BYPASS pin - SOURCE pin.
from the turns ratio of the transformer.
SECONDARY BYPASS pin - SECONDARY GROUND pin.
The interaction between the leakage reactance of the output winding(s) FEEDBACK pin - SECONDARY GROUND pin.
and the output capacitance (COSS) of the SR FET leads to voltage
Signal Components
ringing at the instance of winding voltage reversal when the primary
Resistors RLS, RBP, RFB(UPPER), RFB(LOWER) and R IS which provide feedback
MOSFET turns on. This ringing can be suppressed using a RC
information must be placed as close as possible to the IC pin with
snubber connected across the SR FET. A snubber resistor in the
short traces.
range of 10 Ω to 47 Ω should be used (higher resistance values lead
to a noticeable drop in efficiency). A capacitor value of 1 nF to 2.2 nF Critical Loop Area
is adequate for most designs. Loops for circuits with high dv/dt or di/dt should be kept as small as
possible. The area of the primary loop − input filter capacitor to
Output Filter Capacitance (COUT)
transformer primary winding to IC should be kept small. Ideally, no
Aluminium electrolytic capacitors with low ESR and high RMS ripple
loop should be inside another loop (see Figure 14). This will minimize
current rating are suitable for use with most high frequency flyback
cross-talk between circuits.
switching power supplies intended for ballast applications. Typically,
300 µF to 400 µF capacitance per ampere of output current is Primary Clamp Circuit
appropriate. This value may be adjusted to reflect the amount of A clamp is used to limit the peak voltage on the DRAIN pin at
output current ripple required. Ensure that capacitors with a voltage turn-off. This can be achieved by placing an RCD or Zener diode
rating higher than the highest output voltage (plus sufficient margin) clamp across the primary winding. Positioning the the clamp
are used. components close to the transformer and IC will minimize the size of
this loop and reduce EMI.
Output Current Sense Resistor (R IS)
For output constant current (CC) operation, external current sense Y Capacitor
resistor R IS should be connected between the ISENSE pin and the The Y capacitor should be connected directly between the positive
SECONDARY GROUND pin of the IC as shown in Figure 14. If terminal of the primary input filter capacitor and the output positive
constant current (CC) regulation is not required, this pin should be or return of the transformer main secondary winding. This will route
connected to the SECONDARY GROUND pin of the IC. high magnitude common mode surge currents away from the IC. If
an input π filter (C1, LF and C2) is used, the filter inductor should be
The voltage generated across the resistor is compared to an internal
placed between the negative terminals of the filter capacitors.
reference the Current Limit Voltage Threshold (ISV(TH)) which is
approximately 35 mV. The size of R IS can be calculated ; Output Rectifier Diode
For best performance, the area of the loop connecting the secondary
R IS = I OUT ^ CC h /I SV^ TH h winding, the output rectifier diode, and the output filter capacitor
should be minimized. Sufficient copper area should be provided at
The R IS resistor must be placed close to the ISENSE and SECONDARY the terminals of the rectifier diode for heat sinking.
GROUND pins with short traces. This prevents ground impedance
noise interference that may cause instability which would be most ESD Immunity
apparent during constant current operation. Sufficient clearance should be maintained (>8 mm) between the
primary-side and secondary-side circuits to enable easy compliance
Output Post Filter Components (LPF, CPF) with any ESD or hi-pot test requirements. A spark gap is best placed
If necessary a post filter (LPF and CPF) can be added to attenuate high between the output return (and/or positive terminals) and one of the
frequency switching noise and ripple. Inductor LPF should be in the AC inputs after the fuse. In this configuration a 6.4 mm (5.5 mm may
range of 1 mH – 3.3 mH with a current rating greater than peak be acceptable in some applications) spark gap is suitable to meet
output current. Capacitor CPF should be in the range of 100 µF to creepage and clearance requirements of the applicable safety
330 µF with a voltage rating ≥ 1.25 × VOUT. If a post filter is used standards. This is less than the typical primary to secondary spacing
then the output voltage sense resistor should be connected before because the voltage across a spark gap does not exceed the peak of
the post filter inductor. the AC input.
Drain Node
The drain switching node is the dominant noise generator. As such
components connected the drain node should be placed close to
the IC and away from sensitive feedback circuits. The clamp circuit
components should be located away from the PRIMARY BYPASS pin, and
employ minimum trace width and length.
14
Rev. E 02/18 www.power.com
LYTSwitch-6
PFC loop formed by Bias supply loop Primary signal Secondary signal Secondary loop
filter C3, free-wheel diode formed by auxiliary components C11, R18, components are placed formed by
D1+D17, T1, primary winding winding NB, D7 and R45 and R4 are placed as close as possible to secondary winding
NP and bulk capacitor C4 is C10 is tight and small. as close as possible to IC IC pin to which they are FL1-FL2, COUT
tight and small. pin to which they are connected with short C15//C37 and
connected to with traces. Auxiliary winding rectifier D10 is tight
short traces. FL3-FL4, D11 and C38 and small.
is tight and small.
OUTPUT
PFC
Inductor
Inductor
Filter
CMC
Filter Flyback
Transformer Output
Capacitor
Bulk
Capacitor
MOV
AC INPUT
Copper heat sink for Y capacitor connected
SOURCE pin is maximized. to RTN and C4 (-).
Special Notes
• All loops are separated; no loop is inside a loop. This will avoid ground impedance noise coupling.
• Maintain trace surface area and length of high dv/dt nodes such as DRAIN, as small and short as possible to minimized RFI generation.
• No signal trace (quiet trace) such as Y capacitor and feedback return must be routed near or across noisy nodes (high dv/dt or di/dt) such as DRAIN,
underneath transformer belly, switching side of any winding or output rectifier diode to avoid capactively or magnetically coupled noise.
• No signal trace must share path with traces having an AC switching current such as output capacitor. Connection must be star-connected to
capacitor pad in order to avoid ground impedance coupled noise.
PI-8585-020918
Figure 14. TOP and BOTTOM Sides – Ideal Layout Example Showing Tight Loop Areas for Circuit with High dv/dt and di/dt, Component Placement.
15
www.power.com Rev. E 02/18
LYTSwitch-6
Recommendations in Reducing No-load Consumption 5. Common mode chokes are typically required at the input of a
The LYTSwitch-6 IC can start in self-powered mode, drawing energy power supply to attenuate common mode noise. However, the
from the BYPASS pin capacitor charged through an internal current same effect can be achieved by using shield windings on the
source. Use of a bias winding is used to provide supply current to the transformer. Shield windings can be used in conjunction with
PRIMARY BYPASS pin once the LYTSwitch-6 IC has started switching. common mode filter inductors at the input to reduce conducted
An auxiliary (bias) winding from the switching transformer serves this and radiated EMI.
purpose. The bias-winding-derived supply to the PRIMARY BYPASS 6. Adjusting the values of the SR FET RC snubber components
pin enables designs with no-load consumption of less than 100 mW. reduces high frequency radiated and conducted EMI.
Resistor RBP (shown in Figure 12) can be adjusted to achieve lowest 7. A π filter comprising differential inductors and capacitors can be
no-load input power. used in the input rectifier circuit to reduce low frequency
differential EMI. A ferrite bead (Figure 14) can be added to
Other components that that may further reduce no-load consumption
further improve EMI.
are;
8. A resistor across a differential inductor reduces the Q factor and
1. Low value of primary clamp capacitor, CSN. reduce EMI above 10 MHz; however this may increase the EMI
2. Schottky or ultrafast diode for bias supply rectifier, DBIAS. below 5 MHz.
3. Low ESR capacitor for bias supply filter capacitor, CBIAS. 9. A 1 µF ceramic capacitor connected across the output of the
4. Low value SR FET RC snubber capacitor, CSR. power supply reduces radiated EMI.
5. Transformer construction: Tape between primary winding layers, 10. A slow bias rectifier-diode (250 ns < tRR < 500 ns) reduces
and multi-layers of tape between primary and secondary windings conducted EMI above 20 MHz and radiated EMI above 30 MHz.
reduces inter-winding capacitance. Thermal Management Considerations
Recommendations for EMI Reduction The SOURCE pin is internally connected to the IC lead frame and
1. Appropriate component placement and small loop areas for the provides the main heat removal path for the device. The SOURCE pin
primary and secondary power circuits minimizes radiated and should therefore be connected to a copper area underneath the IC to
conducted EMI. Care should be taken to achieve a compact loop act not only as a single point ground, but also as a heat sink. As this
area. (See Figure 14) area is connected to the quiet source node, this area can be maximized
2. A small capacitor in parallel to the primary-side-clamp diode can for good heat sinking without increasing EMI. Similarly for the output
reduce radiated EMI. SR FET, maximize the PCB area connected to the pins of the SR FET.
3. A resistor (2 Ω – 47 Ω) in series with the bias winding helps Sufficient copper area should be provided on the board to keep the
reduce radiated EMI. IC temperature safely below the absolute maximum limits. It is
4. A series connection of a small resistor and ceramic capacitor recommended that the copper area provided for the copper plane on
(<22 pf) across the primary (Figure 19) or across the secondary which the SOURCE pin of the IC is soldered be sufficiently large to
winding (<100 pf) reduces conducted and radiated EMI. Larger keep the IC temperature below 90 °C when operating the power
capacitor values may increase no-load consumption. supply at full rated load and at the lowest rated input AC supply voltage.
16
Rev. E 02/18 www.power.com
LYTSwitch-6
Heat Spreader Unless a ceramic insulator material is used as a heat sink, care should
For enclosed power supplies such as LED ballast that experience be taken to avoid compromising the isolation barrier. Typically the
high ambient conditions, using the PCB alone as a heat sink may not heat spreader is formed by the combination of heat spreader material
be sufficient to keep IC within temperature limits. The addition of a (copper or aluminum) a 0.4 mm mylar pad for reinforced isolation and
metal heat spreader may be required to limit the maximum IC a thermally conductive pad to better transfer heat from the device to
temperature. the heat-spreader. Figure 15 suggests a simple method to attach a
heat spreader to an InSOP-24D package while maintaining appropriate
creepage and clearance.
Thermal Pad
d > 6.6 mm
InSOP-24D
Heat Sink
d > 6.6 mm
Mylar 0.4 mm
Heat Sink
0.5 mm
6.6 mm
Power
FET
Secondary
Control
Primary
Control
InnoSwitch3 4.2 mm
InSOP-24D
PI-8377-020918
17
www.power.com Rev. E 02/18
LYTSwitch-6
Recommended Position of InSOP-24D Package package. Cutting a slot in the PCB that runs near-to or underneath
with Respect to Transformer the InSOP package is not generally recommended as this weakens
the PCB. For long PCBs, the use of a mechanical support or post in
The PCB underneath the transformer and InSOP-24D should be rigid. the middle of the board or located near to the InSOP package is
If large transformers are used together with a thin PCB (<1.5 mm), it recommended.
is recommended that the transformer be moved away from the InSOP
Force
PI-8523-020618
(23-a) (23-b)
Force Force
Transformer Transformer
PI-8524-020618 PI-8525-021418
(23-c) (23-d)
Figure 16. Recommended Position of InSOP-24D Package Shown with Check Mark.
18
Rev. E 02/18 www.power.com
LYTSwitch-6
Quick Design Checklist excessive leading-edge current spikes at start-up. Repeat tests under
steady-state conditions and verify that the leading-edge current spike
As with any power supply, the performance of all LYTSwitch-6 designs is below ILIMIT(MIN) at the end of tLEB(MIN). Under all conditions, the
should be measured on the bench to make sure that component maximum Drain current for the primary MOSFET should be below the
limits are not exceeded under worst-case conditions. As a minimum, specified absolute maximum ratings.
the following tests are strongly recommended:
Thermal Check – At specified maximum output power, minimum input
Maximum Drain Voltage – Verify that the VDS of the LYTSwitch-6 IC
voltage and maximum ambient temperature, verify that temperature
and the SR FET do not exceed 90% of their respective breakdown
meets specified limits for the LYTSwitch-6 IC, transformer, output
voltages at the highest input voltage and peak (overload) output
SR FET, and output capacitors. There should be sufficient thermal
power both during normal operation and at start-up.
margin to account for part-to-part variation in the RDS(ON) of the
Maximum Drain Current – At maximum ambient temperature, LYTSwitch-6 IC. At low-line and full load it is recommended that the
maximum input voltage and peak output (overload) power. Review LYTSwitch-6 SOURCE pin temperature is limited to 110 °C to allow for
drain current waveforms for any signs of transformer saturation or these variations.
19
www.power.com Rev. E 02/18
LYTSwitch-6
C8
2.2 nF
500 VAC
R8
C16 C10 102 kΩ C14
L2 D2 1000 µF 1000 µF 1% 100 nF
1.5 mH S1J-13-F T1
RM8 16 V 16 V 1/16 W 50 V 12 V, 2.92 A
12 FL1
+V
VR2 C7 R7
D1 BZG03C240TR 3.3 nF R3 C17
ES2-J-LTP 11 15 Ω C9
240 V 200 V 120 kΩ 3.3 nF 1% 470 pF R14
200 V 0.75 W 200 V 20 kΩ
1 VR1 1%
C4 VR3 R4 Z4E140A-E3/54 1/16 W
68 µF BZG03C240TR 1.6 MΩ 140 V 10 FL2
500 V 240 V 1% L3
R2 R15 Q1
T2 Ferrite Bead AON6250
20 Ω 20 Ω (3.5 x 4.45 mm)
EE13 1% 1%
R19 R12 1/2 W 1/2 W
1 kΩ 1.33 MΩ D4
1% GS1M-LTP
6 10
R9 C11
11.8 kΩ 330 pF
R16 BR1 D5 1 1%
36 kΩ UD4KB100 50 V
ES2J-LTP 1/16 W
1000 V
F1 RV1
L 3.15 A 350 VAC
L1 2
8.8 mH C3
220 nF
C1 C2 630 V R6
140 - 320 68 nF 68 nF 47 Ω
VAC 760 VDC 760 VDC
C13
N 10 µF
C12 16 V
2.2 µF
R17 25 V
36 kΩ R5
1.30 MΩ
1%
D3
FWD
GND
DFU1200-7
BPS
SR
FB
D V
CONTROL
VOUT D6
R1 B340A-13-F
10 kΩ
1%
1/8 W S BPP IS R18
0.012 Ω
LYTSwitch-6 1%
C5 C6 U1 1W
22 µF 470 nF LYT6068C
33 V 50 V
RTN
PI-8586-012318
Figure 17. Schematic of DER-637, 35 W, 12 V, 2.92 A, 140 VAC – 320 VAC using LYSwitch-6 LYT6068C with Synchronous Rectification.
A High Efficiency, 35 W, 12 V Universal Input LED Ballast One end of the transformer (T1) primary winding is connected to the
– with Synchronous Rectification positive terminal of the bulk capacitor (C4) while the other side is
The circuit shown on Figure 17 is a 35 W isolated flyback power connected to the Drain of the LYTSwitch-6 (U1) IC’s the integrated
supply with a single-stage power factor correction circuit for LED 650 V power MOSFET. A low cost RCD primary clamp, D4, R2, R15,
lighting applications. It provides a constant voltage output of 12 V R3 and C7 limits the voltage spike seen by the switching MOSFET.
with accurate voltage regulation and an output current of up to The spike is caused by transformer leakage inductance. The RCD
2.92 A. The power supply is intended for for applications where a primary clamp also reduces radiated and conducted EMI. Clamping
post regulators are used to independently regulate multiple LED Zener VR1 limits the drain voltage spike during start-up into full load
strings design such as in RGBW smart lighting. The power supply is at 320 VAC.
also ideal for single-LED string applications as it delivers the same
The LYTSwitch-6 IC is self-starting, using an internal high-voltage
maximum constant output current with accurate regulation and no
current source to charge the PRIMARY BYPASS pin capacitor (C6)
line-induced ripple from 12 V to 3 V output. The circuit is highly
when line voltage is first applied. During normal operation the
efficient and provides excellent line and load regulation across an
primary-side is powered from an auxiliary winding on transformer T1.
input voltage range of 140 VAC to 320 VAC. The power supply also
Output of the auxiliary winding is rectified by diode D3 and filtered by
provides a PF of greater than 0.9 PF and less than 20% A-THD at
capacitor C5. Resistor R1 limits the current supplied to the PRIMARY
230 VAC.
BYPASS pin. The value of the PRIMARY BYPASS pin capacitor C6
Input Stage used is 470 nF which sets normal current limit.
Fuse F1 provides protection, and isolates the circuit from the input
Power Factor Correction Stage
line in the event of catastrophic component failure. Varistor RV1 is
The PFC stage comprises inductor (T2) in series with blocking diode
connected after the fuse and acts as a voltage clamp – limiting the
(D1 and D5) and is connected to the DRAIN pin of the LYTSwitch-6
voltage to a safe level in the event of a line transient or surge. Bridge
IC. High power factor correction is achieved using a Switched
diode BR1 rectifies the AC line voltage to provide a full-wave rectified
Valley-Fill Single Stage PFC (SVF S2PFC) technique, operating in
DC voltage to the input film capacitors C3 and C4. The circuit
employs a 2-stage EMI filter consisting of C1, L1, C2, L2, and C3. discontinuous conduction mode (DCM). The DCM switched current
from inductor T2 shapes the input current into a quasi-sinusoid when
Primary Flyback Stage the rectified voltage on C3 is less than the DC voltage on C4 resulting
The bulk capacitor C4 filters the line ripple voltage and provides in a high power factor.
A DC voltage to the flyback stage. Capacitor C4 also filters
differential current which reduces conducted EMI noise. The voltage During MOSFET on-time, energy is stored in the PFC inductor (T2)
across the bulk capacitor (C4) monitored via the INPUT OVERVOLTAGE pin and flyback transformer (T1). During MOSFET off-time, the energy
resistors (R4 and R12) to provide line overvoltage and brown-in from both the PFC and flyback inductors is transferred to the
protection. The overvoltage threshold (IOV+) determines the secondary-side through the flyback transformer.
overvoltage threshold, while (IUV+) determines the line turn-on Diode D2 isolates capacitor C3 from the rectified AC input. It also
voltage. In the event of a line surge or transient, an input overvoltage provides a current path for charging of the bulk capacitor C4,
shutdown will be triggered by a line voltage exceeding 490 VPK. especially at low-line which improves efficiency. Free-wheel diodes
20
Rev. E 02/18 www.power.com
LYTSwitch-6
D1 and D5 provide a path for the energy stored in the PFC inductor to output voltage via the OUTPUT VOLTAGE pin. Capacitor C13
transfer to the secondary-side during MOSFET off-time. Diode D1 connected to the SECONDARY BYPASS pin of LYTSwitch-6 IC (U1)
and D5 are connected in series to withstand the resonant ring provides decoupling for the internal circuitry.
induced on the PFC inductor when the MOSFET turns off.
During constant voltage operation, output voltage regulation is
During no-load or under light load (<10% load) the energy stored in
achieved by sensing the output voltage via a potential divider formed
the PFC inductor (T2) may be more than the secondary load requires,
by resistors R8 and R9. The voltage across R9 is monitored by the
the excess energy from the PFC inductor is recycled to the bulk
FEEDBACK pin and compared to an internal reference voltage
capacitor C4 and boosts the bulk voltage. A Zener-resistor clamp,
Of 1.265 V to maintain accurate regulation. Bypass capacitor C11 is
(VR2 and VR3 in series with R19) is connected across the bulk capacitor
placed across FEEDBACK and SECONDARY GROUND pins to filter high
C4 to limit the voltage rise to safe levels. The Zener clamp voltage is
frequency noise preventing interference with the feedback signal.
restricted to less than the 500 V rating of the bulk capacitor C4.
During constant current operation, the output current is set by the
Secondary Stage
sense resistor R18. The voltage across the sense resistor is
The secondary-side control provided by the LYTSwitch-6 IC provides
compared to the ISENSE pin’s internal reference threshold of 35 mV
constant output voltage and constant output current. The output
in order to maintain constant current regulation. Diode D6 in parallel
from the secondary winding of the transformer is rectified by SR FET
with the current sense resistor R18 clamps the voltage across the
Q1 and filtered by output capacitors C10 and C16. Adding an RC
ISENSE pin and SECONDARY GROUND pin to protect the IC from the
snubber (R7 and C9) across the SR FET reduces voltage stress.
high current surge from the output capacitor induced by an output
The secondary-side of the IC is self-powered using either the short-circuit.
secondary winding forward voltage via the FORWARD pin or the
21
www.power.com Rev. E 02/18
LYTSwitch-6
Thermal Resistance
Thermal Resistance: Notes:
(qJA)..................................... 76 °C/W1, 65 °C/W2 1. Soldered to 0.36 sq. inch (232 mm2) 2 oz. (610 g/m2) copper clad.
(qJC)......................................................8 °C/W3 2. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad.
3. The case temperature is measured on the top of the package.
Primary-Side TAMB = 25 °C
1.35 W
Power Rating (device mounted in socket resulting in TCASE = 120 °C)
Secondary-Side TAMB = 25 °C
0.125 W
Power Rating (device mounted in socket)
Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Control Functions
Start-Up Switching
fSW TJ = 25 °C 22 25 27 kHz
Frequency
Jitter Frequency fM TJ = 25 °C, fSW = 100 kHz 0.8 1.25 1.70 kHz
Minimum Primary
Feedback Block-Out tBLOCK tOFF(MIN) µs
Timer
22
Rev. E 02/18 www.power.com
LYTSwitch-6
Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Control Functions (cont.)
OV Pin Line
IOV- TJ = 25 °C 106 115 118 µA
Overvoltage Threshold
OV Pin Line
IOV(H) TJ = 25 °C 6 7 8 µA
Overvoltage Hysteresis
OV Pin Line
Overvoltage Deglitch tOV+ TJ = 25 °C 3 µs
Filter
UV Pin Brown-In
IUV+ TJ = 25 °C 23.95 26.06 28.18 µA
Threshold
Line Fault Protection
VOLTAGE Pin
VV TJ = 25 °C 1000 V
Voltage Rating
23
www.power.com Rev. E 02/18
LYTSwitch-6
Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Circuit Protection
di/dt = 162.5 mA/ms
LYT60x3C 511 550 589
TJ = 25 °C
Overload Detection TJ = 25 °C
fOVL 102 110 118 kHz
Frequency See Note A
Auto-Restart Trigger TJ = 25 °C
t AR(SK) 1.3 sec
Skip Time See Note A
Short Auto-Restart
t AR(OFF)SH TJ = 25 °C 0.17 0.20 0.23 sec
Off-Time
24
Rev. E 02/18 www.power.com
LYTSwitch-6
Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Output
TJ = 25 °C 4.90 5.64
LYT6063C
ID = ILIMIT+1 TJ = 100 °C 7.60 8.74
TJ = 25 °C 1.95 2.24
LYT6065C
ID = ILIMIT+1 TJ = 100 °C 3.02 3.47
TJ = 25 °C 1.02 1.17
LYT6067C
ID = ILIMIT+1 TJ = 100 °C 1.58 1.82
TJ = 25 °C 0.86 0.99
LYT6068C
ON-State Resistance RDS(ON) W
ID = ILIMIT+1 TJ = 100 °C 1.33 1.53
TJ = 25 °C 1.95 2.24
LYT6075C
ID = ILIMIT+1 TJ = 100 °C 3.02 3.47
TJ = 25 °C 1.20 1.38
LYT6077C
ID = ILIMIT+1 TJ = 100 °C 1.86 2.14
Thermal Shutdown
TSD(H) 70 °C
Hysteresis
25
www.power.com Rev. E 02/18
LYTSwitch-6
Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Secondary
FEEDBACK Pin Voltage VFB TJ = 25 °C 1.250 1.265 1.280 V
Maximum Switching
fSREQ TJ = 25 °C 118 132 145 kHz
Frequency
Current Limit
ISV(TH) External Resistor 33.94 35.90 37.74 mV
Voltage Threshold
Soft-Start Frequency
tSS(RAMP) TJ = 25 °C 7.5 11.8 16 ms
Ramp Time
FEEDBACK Pin
VFB(OFF) 112 135 mV
Short-Circuit
Thermal Foldback
TƒB(H) 15 °C
Hysteresis
26
Rev. E 02/18 www.power.com
LYTSwitch-6
Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Synchronous Rectifier @ TJ = 25 °C
SR Pin Drive Voltage VSR 4.4 V
SR Pin Voltage
VSR(TH) 0 mV
Threshold
TJ = 25 °C
SR Pin Pull-Up Current ISR(PU) 135 165 195 mA
CLOAD = 2 nF, fSW = 100 kHz
SR Pin Pull-Down TJ = 25 °C
ISR(PD) 87 97 107 mA
Current CLOAD = 2 nF, fSW = 100 kHz
0-100% 71
TJ = 25 °C
Rise Time tR ns
CLOAD = 2 nF 10-90% 40
0-100% 32
TJ = 25 °C
Fall Time tF ns
CLOAD = 2 nF 10-90% 15
TJ = 25 °C
Output Pull-Up
RPU VBPS = 4.4 V 7.2 8.3 9.4 W
Resistance
ISR = 10 mA
TJ = 25 °C
Output Pull-Down
RPD VBPS = 4.4 V 10.8 12.1 13.4 W
Resistance
ISR = 10 mA
Notes:
A. This parameter is derived from characterization.
27
www.power.com Rev. E 02/18
LYTSwitch-6
3.0 1.4
PI-8438-092017
PI-8439-092017
Scaling Factors:
1.2 LYT6063C 1.40
2.5 LYT6065C 3.20
Scaling Factors:
0.0 0
0 100 200 300 400 500 600 700 0 2 4 6 8 10
Drain Voltage (V) DRAIN Voltage (V)
Figure 18. Maximum Allowable Drain Current vs. Drain Voltage. Figure 19. Output Characteristics.
10000 75
PI-8440-092017
PI-8441-092017
Scaling Factors: Scaling Factors:
LYT6063C 1.40 LYT6063C 1.40
LYT6065C 3.20
Drain Capacitance (pF)
LYT6065C 3.20
1000 LYT6067C 6.10 LYT6067C 6.10
LYT6068C 7.65 LYT6068C 7.65
50
Power (mW)
100
25
10
1.1 VSR(t)
SYNCHRONOUS RECTIFIER DRIVE
PI-2213-021518
PI-7474-011215
-0.0
(Normalized to 25 °C)
-0.3
1.0
0.9 -1.8
-50 -25 0 25 50 75 100 125 150
500 ns
Junction Temperature (°C) Time (ns)
Figure 22. Breakdown vs. Temperature. Figure 23. SYNCHRONOUS RECTIFIER DRIVE Pin Negative
Voltage.
28
Rev. E 02/18 www.power.com
LYTSwitch-6
4.5 1.4
PI-8485-101117
PI-8487-021518
Scaling Factors: Scaling Factors:
4.0 LYT6073 1.40 LYT6073 1.40
1.2
LYT6075 3.20 LYT6075 3.20
3.5
1.0
3.0
2.5 0.8
2.0 0.6
1.5
0.4
1.0 TCASE = 25 °C
0.2 TCASE = 100 °C
0.5
0.0 0
0 100 200 300 400 500 600 700 800 0 2 4 6 8 10
Drain Voltage (V) Drain Voltage (V)
Figure 24. Maximum Allowable Drain Current vs. Drain Voltage. Figure 25. Output Characteristics.
10000 100
PI-8486-101117
PI-8488-101117
Scaling Factors: Scaling Factors:
LYT6073 1.40
LYT6073 1.40
LYT6075 3.20
Drain Capacitance (pF)
LYT6075 3.20
LYT6077 5.20
1000 75 LYT6077 5.20
Power (mW)
100 50
10 25
29
www.power.com Rev. E 02/18
InSOP-24D
30
Rev. E 02/18
3 4
0.50 [0.020] Ref. 0.20 [0.008] Ref.
2.71 0.107
3.35 [0.132] Ref. 2.59 0.102
5 Lead Tips
2X 24 13 0.15 [0.006] C
0.10 [0.004] C B
LYTSwitch-6
PI-8106-083017
POD-inSOP-24D Rev A
www.power.com
LYTSwitch-6
MSL Table
Part Number MSL Rating
LYT60xxC 3
Latch-up at 125 °C JESD78D > ±100 mA or > 1.5 × VMAX on all pins
Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins
ANSI/ESDA/JEDEC
Charge Device Model ESD > ±500 V on all pins
JS-002-2014
31
www.power.com Rev. E 02/18
Revision Notes Date
E Code L. Added Applications section. 02/18
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE, SCALE-iDriver, SCALE-iFlex, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch,
InnoSwitch, HiperTFS, HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI
FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2018, Power Integrations, Inc.