LNK603-606/613-616

LinkSwitch-II Family
Energy-Efficient, Accurate CV/CC Switcher
for Adapters and Chargers

Product Highlights
Dramatically Simplifies CV/CC Converters
• Eliminates optocoupler and all secondary CV/CC control circuitry
• Eliminates all control loop compensation circuitry

Advanced Performance Features Wide Range

• Compensates for transformer inductance tolerances High-Voltage
• Compensates for input line voltage variations DC Input
D
• Compensates for cable voltage drop (LNK61X series) FB

• Compensates for external component temperature variations LinkSwitch-II BP/M

• Very tight IC parameter tolerances using proprietary trimming S
technology
• Frequency jittering greatly reduces EMI filter cost
• Even tighter output tolerances achievable with external resistor PI-4960-012315
selection/trimming
(a) Typical Application Schematic
• Programmable switching frequency up to 85 kHz to reduce trans-
former size VO ±5%

Advanced Protection/Safety Features

• Auto-restart protection reduces power delivered by >95% for output
short-circuit and control loop faults (open and shorted components)
• Hysteretic thermal shutdown – automatic recovery reduces power ±10%
supply returns from the field
• Meets high-voltage creepage requirements between DRAIN and all
other pins both on the PCB and at the package

EcoSmart™– Energy Efficient PI-4906-012315 IO

• Easily meets all global energy efficiency regulations (b) Output Characteristic
• No-load consumption below 30 mW at 230 VAC with optional
Figure 1. Typical Application/Performance – Not a Simplified Circuit (a) and
external bias winding Output Characteristic Envelope (b). (see Application Section for
• ON/OFF control provides constant efficiency down to very light loads more information).
– ideal for CEC and ENERGY STAR 2.0 regulations
• No current sense resistors – maximizes efficiency
Output Power Table
Green Package 85-265 VAC
• Halogen free and RoHS compliant package Product3
Adapter 1
Open Frame2
Applications
LNK603/613PG/DG 2.5 W 3.3 W
• Chargers for cell/cordless phones, PDAs, MP3/portable audio
devices, adapters, LED drivers, etc. LNK604/614PG/DG 3.5 W 4.1 W

Description LNK605/615PG/DG 4.5 W 5.1 W

LNK606/616PG/GG/DG 5.5 W 6.1 W
The LinkSwitch™-II dramatically simplifies low power CV/CC charger
designs by eliminating an optocoupler and secondary control circuitry. Table 1. Output Power Table.
The device introduces a revolutionary control technique to provide very Notes:
tight output voltage and current regulation, compensating for transformer 1. Minimum continuous power in a typical non-ventilated enclosed adapter
and internal parameter tolerances along with input voltage variations. measured at +50 °C ambient, device, TJ <100 °C.
2. Maximum practical continuous power in an open frame design with adequate
The device incorporates a 700 V power MOSFET, a novel ON/OFF control heat sinking, measured at 50 °C ambient (see Key Applications Consider-
state machine, a high-voltage switched current source for self biasing, ations section for more information).
frequency jittering, cycle-by-cycle current limit and hysteretic thermal 3. Packages: P: DIP-8C, G: SMD-8C, D: SO-8C.
shutdown circuitry onto a monolithic IC.

DIP-8C (P Package) SMD-8C (G Package) SO-8C (D Package).

Figure 2. Package Options.

www.power.com August 2016

This Product is Covered by Patents and/or Pending Patent Applications.

 LNK603-606/613-616

DRAIN
(D)
REGULATOR
BYPASS 6V
(BP/M)
+
FB 6V -
+ OUT Reset 5V
FEEDBACK D Q STATE
VTH - MACHINE
(FB) VILIMIT
tSAMPLE-OUT
ILIM Drive
CABLE DROP VILIMIT DCMAX
COMPENSATION

FAULT
6.5 V FB Auto-Restart
Open-Loop

INDUCTANCE THERMAL
CORRECTION SHUTDOWN
tSAMPLE-INPUT DCMAX
tSAMPLE-OUT SAMPLE
tSAMPLE-INPUT DELAY

OSCILLATOR
SOURCE
+ (S)
SOURCE ILIM - VILIMIT
CONSTANT
(S) CURRENT Current Limit
Comparator LEADING
EDGE
BLANKING

PI-4908-012915

Figure 3. Functional Block Diagram.

Pin Functional Description

DRAIN (D) Pin:
P Package (DIP-8C)
This pin is the power MOSFET drain connection. It provides internal
operating current for both start-up and steady-state operation. G Package (SMD-8C) D Package (SO-8C)
BYPASS/MULTI-FUNCTIONAL PROGRAMMABLE (BP/M) Pin:
This pin has multiple functions: FB 1 8 S 1 8
FB S
1. It is the connection point for an external bypass capacitor for the
BP/M 2 7 2 7
internally generated 6 V supply. S BP/M S
2. It is a mode selection for the cable drop compensation for 6
6 S S
LNK61X series.
4 5
D 4 5 S D S
FEEDBACK (FB) Pin:
During normal operation, switching of the power MOSFET is controlled
by this pin. This pin senses the AC voltage on the bias winding. This
control input regulates both the output voltage in CV mode and output
current in CC mode based on the flyback voltage of the bias winding. PI-3491-020615
The internal inductance correction circuit uses the forward voltage on
the bias winding to sense the bulk capacitor voltage. Figure 4. Pin Configuration.

SOURCE (S) Pin:

This pin is internally connected to the output MOSFET source for
high-voltage power and control circuit common returns.

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LinkSwitch-II Functional Description Auto-Restart and Open-Loop Protection

In the event of a fault condition such as an output short or an open
The LinkSwitch-II combines a high-voltage power MOSFET loop condition the LinkSwitch-II enters into an appropriate protection
switch with a power supply controller in one device. Similar to the mode as described below.
LinkSwitch-LP and TinySwitch-III it uses ON/OFF control to regulate
the output voltage. In addition, the switching frequency is modulated In the event the FEEDBACK pin voltage during the flyback period falls
to regulate the output current to provide a constant current below 0.7 V before the FEEDBACK pin sampling delay (~2.5 ms) for a
characteristic. The LinkSwitch-II controller consists of an oscillator, duration in excess of ~450 ms (auto-restart on-time (t AR-ON) the
feedback (sense and logic) circuit, 6 V regulator, over-temperature converter enters into auto-restart, wherein the power MOSFET is
protection, frequency jittering, current limit circuit, leading-edge disabled for 2 seconds (~18% auto-restart duty cycle). The auto-
blanking, inductance correction circuitry, frequency control for restart alternately enables and disables the switching of the power
constant current regulation and ON/OFF state machine for CV control. MOSFET until the fault condition is removed.

Inductance Correction Circuitry In addition to the conditions for auto-restart described above, if the
If the primary magnetizing inductance is either too high or low the sensed FEEDBACK pin current during the forward period of the
converter will automatically compensate for this by adjusting the conduction cycle (switch “on” time) falls below 120 mA, the converter
oscillator frequency. Since this controller is designed to operate in annunciates this as an open-loop condition (top resistor in potential
discontinuous-conduction mode the output power is directly divider is open or missing) and reduces the auto-restart time from
proportional to the set primary inductance and its tolerance can be 450 ms to approximately 6 clock cycles (90 ms), whilst keeping the
completely compensated with adjustments to the switching disable period of 2 seconds.
frequency.
Over-Temperature Protection
Constant Current (CC) Operation The thermal shutdown circuitry senses the die temperature. The
As the output voltage and therefore the flyback voltage across the threshold is set at 142 °C typical with a 60 °C hysteresis. When the
bias winding increases, the FEEDBACK pin voltage increases. The die temperature rises above this threshold (142 °C) the power
switching frequency is adjusted as the FEEDBACK pin voltage MOSFET is disabled and remains disabled until the die temperature
increases to provide a constant output current regulation. The falls by 60 °C, at which point the MOSFET is re-enabled.
constant current circuit and the inductance correction circuit are
Current Limit
designed to operate concurrently in the CC region.
The current limit circuit senses the current in the power MOSFET.
Constant Voltage (CV) Operation When this current exceeds the internal threshold (ILIMIT), the power
As the FEEDBACK pin approaches VFBth from the constant current MOSFET is turned off for the remainder of that cycle. The leading
regulation mode, the power supply transitions into CV operation. edge blanking circuit inhibits the current limit comparator for a short
The switching frequency at this point is at its maximum value, time (tLEB) after the power MOSFET is turned on. This leading edge
corresponding to the peak power point of the CC/CV characteristic. blanking time has been set so that current spikes caused by
The controller regulates the FEEDBACK pin voltage to remain at VFBth capacitance and rectifier reverse recovery time will not cause
using an ON/OFF state-machine. The FEEDBACK pin voltage is premature termination of the MOSFET conduction. The LinkSwitch-II
sampled 2.5 ms after the turn-off of the high-voltage switch. At light also contains a “di/dt” correction feature to minimize CC variation across
loads the current limit is also reduced to decrease the transformer the input line range.
flux density.
6.0 V Regulator
Output Cable Compensation The 6 V regulator charges the bypass capacitor connected to the
This compensation provides a constant output voltage at the end of BYPASS pin to 6 V by drawing a current from the voltage on the
the cable over the entire load range in CV mode. As the converter DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal
load increases from no-load to the peak power point (transition point supply voltage node. When the MOSFET is on, the device runs off of
between CV and CC) the voltage drop introduced across the output the energy stored in the bypass capacitor. Extremely low power
cable is compensated by increasing the FEEDBACK pin reference consumption of the internal circuitry allows the LinkSwitch-II to
voltage. The controller determines the output load and therefore the operate continuously from the current drawn from the DRAIN pin.
correct degree of compensation based on the output of the state A bypass capacitor value of either 1 mF or 10 mF is sufficient for both
machine. Cable drop compensation for a 24 AWG (0.3 W) cable is high frequency decoupling and energy storage.
selected with CBP = 1 mF and for a 26 AWG (0.49 W) cable with
CPB = 10 mF.

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Applications Example

C6
1 nF R7
100 V 200 Ω
L1 T1
1.5 mH EE16 5 V, 555 mA
5 10

C3 D7
R2 820 pF SS14
D1 D2 470 kΩ 1 kV 3 8 R8
1N4007 1N4007 200 Ω
1 C7 DC
680 µF Output
10 V
RF1 R3 VR1
8.2 Ω 300 Ω 2 2MM5230B-7
2W 4.7 V

D5
1N4007 4
AC C1 C2
Input 4.7 µF 4.7 µF
400 V 400 V
R5
NC 13 kΩ
1%
D6
D
LL4148
D3 D4 LinkSwitch-II FB
1N4007 1N4007 U1 BP
LNK613DG R4
S R6
C4 6.2 kΩ C5 8.87 kΩ
1 µF 10 µF 1%
25 V 16 V
PI-5111-012315

Figure 5. Energy Efficient USB Charger Power Supply (74% Average Efficiency, <30 mW No-load Input Power).

Circuit Description Table 2 shows the amount of compensation for each device and
bypass capacitor value. The LNK60x devices do not provide cable
This circuit shown in Figure 5 is configured as a primary-side drop compensation.
regulated flyback power supply utilizing the LNK613DG. With an
average efficiency of 74% and <30 mW no-load input power this The optional bias supply formed by D6 and C5 provides the operating
design easily exceeds the most stringent current energy efficiency current for U1 via resistor R4. This reduces the no-load consumption
requirements. from ~200 mW to <30 mW and also increases light load efficiency.

Input Filter The rectified and filtered input voltage is applied to one side of the
AC input power is rectified by diodes D1 through D4. The rectified primary winding of T1. The other side of the transformer’s primary
DC is filtered by the bulk storage capacitors C1 and C2. Inductor L1, winding is driven by the integrated MOSFET in U1. The leakage
C1 and C2 form a pi (π) filter, which attenuates conducted differential- inductance drain voltage spike is limited by an RCD-R clamp
mode EMI noise. This configuration along with Power Integrations consisting of D5, R2, R3, and C3.
transformer E-shield™ technology allow this design to meet EMI
Output Rectification
standard EN55022 class B with good margin without requiring a Y
The secondary of the transformer is rectified by D7, a 1 A, 40 V
capacitor, even with the output connected to safety earth ground.
Schottky barrier type for higher efficiency, and filtered by C7. If
Fusible resistor RF1 provides protection against catastrophic failure.
lower efficiency is acceptable then this can be replaced with a
This should be suitably rated (typically a wire wound type) to
1 A PN junction diode for lower cost. In this application C7 was sized
withstand the instantaneous dissipation while the input capacitors
to meet the required output voltage ripple specification without
charge when first connected to the AC line.
requiring a post LC filter. To meet battery self discharge requirement
LNK 613 Primary the pre-load resistor has been replaced with a series resistor and
The LNK613DG device (U1) incorporates the power switching device, Zener network (R8 and VR1). However in designs where this is not a
oscillator, CC/CV control engine, startup, and protection functions. requirement a standard 1 kW resistor can be used.
The integrated 700 V MOSFET provides a large drain voltage margin
Output Regulation
in universal input AC applications, increasing reliability and also
The LNK613 regulates the output using ON/OFF control in the
reducing the output diode voltage stress by allowing a greater
constant voltage (CV) regulation region of the output character-istic and
transformer turns ratio. The device is completely self-powered from
frequency control for constant current (CC) regulation. The feedback
the BYPASS pin and decoupling capacitor C4. For the LNK61X
resistors (R5 and R6) were selected using standard 1% resistor
devices, the bypass capacitor value also selects the amount of output
values to center both the nominal output voltage and constant
cable voltage drop compensation. A 1 mF value selects the standard
current regulation thresholds.
compensation. A 10 mF value selects the enhanced compensation.

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Key Application Considerations LinkSwitch-II Output Cable Voltage Drop

Output Power Table Compensation
The data sheet maximum output power table (Table 1) repre-sents BYPASS Pin Output Voltage
Device
the maximum practical continuous output power level that can be Capacitor Value Change Factor
obtained under the following assumed conditions: 1 μF 1.035
LNK613
10 μF 1.055
1. The minimum DC input voltage is 90 V or higher at 85 VAC input.
The value of the input capacitance should be large enough to 1 μF 1.045
LNK614
meet these criteria for AC input designs. 10 μF 1.065
2. Secondary output of 5 V with a Schottky rectifier diode.
1 μF 1.050
3. Assumed efficiency of 70%. LNK615
4. Discontinuous mode operation (KP >1.3). 10 μF 1.070
5. The part is board mounted with SOURCE pins soldered to a 1 μF 1.060
sufficient area of copper to keep the SOURCE pin temperature at LNK616
10 μF 1.090
or below 90 °C.
6. Ambient temperature of 50 °C for open frame designs and an Table 2. Cable Compensation Change Factor vs. Device and BYPASS Pin
Capacitor Value.
internal enclosure temperature of 60 °C for adapter designs.

Note: Higher output power are achievable if an output CC tolerance of the power supply. See Figure 6 for a recommended circuit board
>±10% is acceptable, allowing the device to be operated at a higher layout for LinkSwitch-II.
SOURCE pin temperature.
When designing a printed circuit board for the LinkSwitch-II based
Output Tolerance power supply, it is important to follow the following guidelines:
LinkSwitch-II provides an overall output tolerance (including line, Single Point Grounding
component variation and temperature) of ±5% for the output voltage Use a single point (Kelvin) connection at the negative terminal of the
in CV operation and ±10% for the output current during CC operation input filter capacitor for the LinkSwitch-II SOURCE pin and bias
over a junction temperature range of 0 °C to 100 °C for the P/G winding return. This improves surge capabilities by returning surge
package. For the D package (SO8) additional CC variance may occur currents from the bias winding directly to the input filter capacitor.
due to stress caused by the manufacturing flow (i.e. solder-wave
immersion or IR reflow). A sample power supply build is Bypass Capacitor
recommended to verify production tolerances for each design. The BYPASS pin capacitor should be located as close as possible to
the SOURCE and BYPASS pins.
BYPASS Pin Capacitor Selection
Feedback Resistors
For LinkSwitch-II 60x Family of Devices (without output Place the feedback resistors directly at the FEEDBACK pin of the
cable voltage drop compensation) LinkSwitch-II device. This minimizes noise coupling.
A 1 mF BYPASS pin capacitor is recommended. The capacitor voltage
rating should be greater than 7 V. The capacitor’s dielectric material Thermal Considerations
is not important but tolerance of capacitor should be ≤ ±50%. The The copper area connected to the SOURCE pins provides the
capacitor must be physically located close to the LinkSwitch-II LinkSwitch-II heat sink. A good estimate is that the LinkSwitch-II will
BYPASS pin. dissipate 10% of the output power. Provide enough copper area to
keep the SOURCE pin temperature below 90 °C. Higher temperatures
For LinkSwitch-II 61x Family of Devices (with output cable are allowable only if an output current (CC) tolerance above ±10% is
voltage drop compensation) acceptable. In this case a maximum SOURCE pin temperature below
The amount of output cable compensation can be selected with the 110 °C is recommended to provide margin for part to part RDS(ON)
value of the BYPASS pin capacitor. A value of 1 mF selects the variation.
standard cable compensation. A 10 mF capacitor selects the enhanced
Secondary Loop Area
cable compensation. Table 2 shows the amount of compensation for
To minimize leakage inductance and EMI the area of the loop connecting
each LinkSwitch-II device and capacitor value. The capacitor can be
the secondary winding, the output diode and the output filter capacitor
either ceramic or electrolytic but tolerance and temperature variation
should be minimized. In addition, sufficient copper area should be
should be ≤ ±50%.
provided at the anode and cathode terminal of the diode for heat
The output voltage that is entered into PIXls design spreadsheet is sinking. A larger area is preferred at the quiet cathode terminal.
the voltage at the end of the output cable when the power supply is A large anode area can increase high frequency radiated EMI.
delivering maximum power. The output voltage at the terminals of
Electrostatic Discharge Spark Gap
the supply is the value measured at the end of the cable multiplied by
An trace is placed along the isolation barrier to form one electrode of
the output voltage change factor.
a spark gap. The other electrode on the secondary is formed by the
LinkSwitch-II Layout Considerations output return node. The spark gap directs ESD energy from the
secondary back to the AC input. The trace from the AC input to the
Circuit Board Layout spark gap electrode should be spaced away from other traces to
LinkSwitch-II is a highly integrated power supply solution that prevent unwanted arcing occurring and possible circuit damage.
integrates on a single die, both, the controller and the high-voltage
MOSFET. The presence of high switching currents and voltages Drain Clamp Optimization
together with analog signals makes it especially important to follow LinkSwitch-II senses the feedback winding on the primary side to
good PCB design practice to ensure stable and trouble free operation regulate the output. The voltage that appears on the feed-back

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Output Filter
Input Stage Primary Clamp Output Capacitors
Diode Snubber
C1 R1 R8 C6
C2 T1

R4
R3
C3 D5 D7
S S S S

R1
LinkSwitch-II
L2 U1 R5
R2 Feedback
D1 Resistors R6 FB BP D
C7
D2 C4
D4
C5
Bypass D3 C8
Capacitor R9
D3
Bypass Supply
RF1 Components
Preload
Resistor

AC Spark
Input Gap DC
Output
PI-5110-012315

Figure 6. PCB Layout Example Showing 5.1 W Design using P Package.

winding is a reflection of the secondary winding voltage while the exceed 3 mA at the maximum bias winding voltage. The value of R4 is
internal MOSFET is off. Therefore any leakage inductance induced calculated according to (VBIAS – VBP)/IS2, where VBIAS (10 V typ.) is the
ringing can affect output regulation. Optimizing the drain clamp to voltage across C5, IS2 (0.5 mA typ.) is the IC supply current and VBP
minimize the high frequency ringing will give the best regulation. (6.0 V typ.) is the BYPASS pin voltage. The parameters IS2 and VBP are
Figure 7 shows the desired drain voltage waveform compared to provided in the parameter table of the LinkSwitch-II data sheet. Diode
Figure 8 with a large undershoot due to the leakage inductance D6 can be any low cost diode such as FR102, 1N4148 or BAV19/20/21.
induced ring. This will reduce the output voltage regulation perfor-
mance. To reduce this adjust the value of the resistor in series with
Quick Design Checklist
the clamp diode. As with any power supply design, all LinkSwitch-II designs should be
verified on the bench to make sure that component specifications are
Addition of a Bias Circuit for Higher Light Load Efficiency and
not exceeded under worst-case conditions. The following minimum
Lower No-load Input Power Consumption.
set of tests is strongly recommended:
The addition of a bias circuit can decrease the no-load input power
from ~200 mW down to less than 30 mW at 230 VAC input. Light
1. Maximum drain voltage – Verify that peak VDS does not exceed 680 V
at the highest input voltage and maximum output power.
load efficiency also increases which may avoid the need to use a
Schottky barrier vs PN junction output diode while still meeting
2. Maximum drain current – At maximum ambient temperature,
maximum input voltage and maximum output load, verify drain
average efficiency requirements.
current waveforms at start-up for any signs of transformer
The power supply schematic shown in Figure 5 has the bias circuit saturation and excessive leading edge current spikes. LinkSwitch-II
incorporated. Diode D6, C5 and R4 form the bias circuit. As the has a leading edge blanking time of 170 ns to prevent premature
output voltage is less than 8 V, an additional transformer winding is termination of the ON-cycle.
needed, AC stacked on top of the feedback winding. This provides a 3. Thermal check – At maximum output power, both minimum and
high enough voltage to supply the BYPASS pin even during low maximum input voltage and maximum ambient temperature;
switching frequency operation at no-load. verify that temperature specifications are not exceeded for
LinkSwitch-II, transformer, output diodes and output capacitors.
In Figure 5 the additional bias winding (from pin 2 to pin 1) is stacked Enough thermal margin should be allowed for part-to-part
on top of the feedback winding (pin 4 to pin 2). Diode D6 rectifies variation of the RDS(ON) of LinkSwitch-II, as specified in the data
the output and C5 is the filter capacitor. A 10 uF capacitor is sheet. To assure 10% CC tolerance a maximum SOURCE pin
recommended to hold up the bias voltage at low switching frequencies. temperature of 90 ºC is recommended.
The capacitor type is not critical but the voltage rating should be
above the maximum value of VBIAS. The recommended current into Design Tools
the BYPASS pin is equal to IC supply current (~0.5 mA) at the
Up-to-date information on design tools can be found at the Power
minimum bias winding voltage. The BYPASS pin current should not
Integrations web site: www.power.com

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 LNK603-606/613-616

PI-5094-012315
PI-5093-012315
An overshoot
is acceptable

Negative ring may

increase output
ripple and/or
degrade output
regulation

Figure 7. Desired Drain Voltage Waveform with Minimal Leakage Figure 8. Undesirable Drain Voltage Waveform with Large Leakage
Ringing Undershoot. Ring Undershoot.

L1 TI
1 mH EE13
5 10

C3 D7
R2 820 pF SL13
D1 D2 470 kΩ 1 kV 3 8
1N4007 1N4007
C7 DC
470 µF 1 kΩ Output
RF1 10 V
R3
8.2 Ω 300 Ω 2
2W

D5
1N4007 4
AC C1 C2
Input 4.7 µF 4.7 µF
400 V 400 V
NC R5
13 kΩ
1%
D
D3 D4 LinkSwitch-II FB
1N4007 1N4007 U1 BP
LNK613DG
S C4 R6
1 µF 9.31 kΩ
50 V 1%
PI-5116-012315

Figure 9. LinkSwitch-II Flyback Power Supply without Bias Supply.

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Absolute Maximum Ratings1,5

DRAIN Voltage .........................................................-0.3 V to 700 V Lead Temperature(3) .................................................................260 °C
DRAIN Peak Current: LNK603/613............................... 320 (480) mA4 Notes:
LNK604/614...............................400 (600) mA4 1. All voltages referenced to SOURCE, TA = 25 °C.
LNK605/615...............................504 (750) mA4 2. Duration not to exceed 2 ms.
LNK606/616...............................654 (980) mA4 3. 1/16 in. from case for 5 seconds.
Peak Negative Pulsed Drain Current ....................................-100 mA2 4. The higher peak DRAIN current is allowed while the DRAIN
FEEDBACK Pin Voltage.................................................. -0.3 V to 9 V voltage is simultaneously less than 400 V.
FEEDBACK Pin Current .........................................................100 mA 5. Maximum ratings specified may be applied, one at a time
BYPASS Pin Voltage....................................................... -0.3 V to 9 V without causing permanent damage to the product.
BYPASS Pin Current................................................................10 mA Exposure to Absolute Maximum ratings for extended
Storage Temperature .................................................-65 °C to 150 °C periods of time may affect product reliability.
Operating Junction Temperature...............................-40 °C to 150 °C

Thermal Resistance
Thermal Resistance: P or G Package: Notes:
(qJA) ......................................... 70 °C/W2; 60 °C/W3 1. Measured on pin 8 (SOURCE) close to plastic interface.

(qJC)1 ....................................................... 11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
D Package: 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(qJA).......................................100 °C/W2; 80 °C/W3
(qJC)1........................................................ 30 °C/W

Conditions
Parameter Symbol SOURCE = 0 V; TJ = 0 to 100 °C Min Typ Max Units
(Unless Otherwise Specified)
Control Functions
TJ = 25 °C, VFB = VFBth LNK603/6 59 66 73
Output Frequency fOSC tON × IFB = 2 mA-ms kHz
See Notes A, G LNK613/6 58 65 72

Frequency Ratio TJ = 25 °C
fRATIO(CC) 1.59 1.635 1.68
(Constant Current) Between VFB = 1.0 V and VFB = 1.6 V
Frequency Ratio Between tON × IFB = 1.6 mA × ms
fRATIO(IC) 1.160 1.215 1.265
(Inductance Correction) and tON × IFB = 2 mA × ms

Peak-Peak Jitter Compared to

Frequency Jitter ±7 %
Average Frequency, TJ = 25 °C

Ratio of Output Fre- TJ = 25 °C

fOSC(AR) 12 16.5 21 %
quency at Auto-Restart Relative to fOSC

Maximum Duty Cycle DCMAX See Notes D, E 55 %

LNK603/604P 1.815 1.840 1.865
LNK603/604D 1.855 1.880 1.905
LNK605P, LNK605D 1.835 1.860 1.885
TJ = 25 °C
LNK606P/G/D 1.775 1.800 1.825
FEEDBACK Pin Voltage VFBth CBP = 10 mF V
LNK613/614P 1.935 1.960 1.985
See Note F
LNK613/614/615D 1.975 2.000 2.025
LNK615P 1.975 2.000 2.025
LNK616P/G/D 1.935 1.960 1.985

FEEDBACK Pin Voltage

TC VFB -0.01 %/°C
Temperature Coefficient

FEEDBACK Pin Voltage

VFB(AR) 0.65 0.72 0.79 V
at Turn-OFF Threshold

Cable Compensation CBP = 1 mF 1.035

υFB LNK613
Factor CBP = 10 mF 1.055

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Conditions
Parameter Symbol SOURCE = 0 V; TJ = 0 to 100 °C Min Typ Max Units
(Unless Otherwise Specified)

Control Functions
CBP = 1 mF 1.045
LNK614
CBP = 10 mF 1.065

Cable Compensation CBP = 1 mF 1.05

υFB LNK615
Factor CBP = 10 mF 1.07
CBP = 1 mF 1.06
LNK616
CBP = 10 mF 1.09
IFB = -500 mA 4
fOSC = 66 kHz IFB = -1 mA 2
Switch ON-Time tON VFB = VFBth ms
See Note E IFB = -1.5 mA 1.33
IFB = -2 mA 1
Minimum Switch
tON(min) See Note E 700 ns
ON-Time
FEEDBACK Pin
tFB 2.35 2.55 2.75 ms
Sampling Delay
IS1 FB Voltage > VFBth 280 330

DRAIN Supply LNK6X3/4 440 520

FB Voltage = VFBth -0.1, mA
Current
IS2 Switch ON-Time = tON LNK6X5 480 560
(MOSFET Switching at fOSC)
LNK6X6 520 600
LNK6X3/4 -5.0 -3.4 -1.8
ICH1 VBP = 0 V
BYPASS Pin LNK6X5/6 -7.0 -4.8 -2.5
mA
Charge Current LNK6X3/4 -4.0 -2.3 -1.0
ICH2 VBP = 4 V
LNK6X5/6 -5.6 -3.2 -1.4

BYPASS Pin Voltage VBP 5.65 6.00 6.25 V

BYPASS Pin
VBPH 0.70 1.00 1.20 V
Voltage Hysteresis
BYPASS Pin
VSHUNT 6.2 6.5 6.8 V
Shunt Voltage
Circuit Protection
LNK6X3
186 200 214
di/dt = 50 mA/ms , TJ = 25 °C

LNK6X4
233 250 267
di/dt = 60 mA/ms , TJ = 25 °C
Current Limit ILIMIT mA
LNK6X5
293 315 337
di/dt = 70 mA/ms , TJ = 25 °C

LNK6X6
382 410 438
di/dt = 100 mA/ms , TJ = 25 °C
Normalized Output TJ = 25 °C
IO 0.975 1.000 1.025
Current See Figure 20, See Note F
Leading Edge TJ = 25 °C
tLEB 170 215 ns
Blanking Time See Note E
Thermal Shutdown
TSD 135 142 150 °C
Temperature

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Conditions
Parameter Symbol SOURCE = 0 V; TJ = 0 to 100 °C Min Typ Max Units
(Unless Otherwise Specified)

Circuit Protection
Thermal Shutdown
TSDH 60 °C
Hysteresis
Output
TJ = 25 °C 24 28
LNK6X3
ID = 50 mA TJ = 100 °C 36 42

TJ = 25 °C 24 28
LNK6X4
ID = 50 mA TJ = 100 °C 36 42
ON-State
RDS(ON) W
Resistance TJ = 25 °C 16 19
LNK6X5
ID = 62 mA TJ = 100 °C 24 28

LNK6X6 TJ = 25 °C 9.6 11
ID = 82 mA
TJ = 100 °C 14 17

VDS = 560 V, See Figure 20

IDSS1 50
OFF-State TJ = 125 °C, See Note C
mA
Leakage VDS = 375 V, See Figure 20
IDSS2 15
TJ = 50 °C
Breakdown TJ = 25 °C
BVDSS 700 V
Voltage See Figure 20

DRAIN Supply
50 V
Voltage

tON × IFB = 2 mA-ms, fOSC = 12 kHz

Auto-Restart
t AR-ON VFB = 0 450 ms
ON-Time
See Notes A, E

Auto-Restart OFF-Time t AR-OFF 1.2 2 s

Open-Loop FEEDBACK
IOL See Note E -120 mA
Pin Current Threshold

Open-Loop ON-Time See Note E 90 ms

NOTES:
A. Auto-restart ON-time is a function of switching frequency programmed by ton× IFB and minimum frequency in CC mode.
B. The current limit threshold is compensated to cancel the effect of current limit delay. As a result the output current stays constant across
the input line range.
C. IDSS1 is the worst-case OFF-state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical
specification under worst-case application conditions (rectified 265 VAC) for no-load consumption calculations.
D. When the duty-cycle exceeds DCMAX the LinkSwitch-II operates in on-time extension mode.
E. This parameter is derived from characterization.
F. Mechanical stress induced during the assembly may cause shift in this parameter. This shift has no impact on the ability of LinkSwitch-II
to meet CC = ±10% and CV = ±5% in mass production given the design follows recommendation in AN-44 and good manufacturing practice.
G. The switching frequency is programmable between 60 kHz and 85 kHz.

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Typical Performance Characteristics

1.200 1.200

PI-5085-012315

PI-5086-012315
1.000 1.000
(Normalized to 25 °C)

(Normalized to 25 °C)
0.800 0.800
Current Limit

Frequency
0.600 0.600

0.400 0.400

0.200 0.200

0.000 0.000
-40 -15 10 35 60 85 110 135 -40 -15 10 35 60 85 110 135
Temperature (°C) Temperature (°C)

Figure 10. Current Limit vs. Temperature. Figure 11. Output Frequency vs. Temperature.

1.200 1.200
PI-5087-012315

PI-5088-012315
1.000 1.000
(Normalized to 25 °C)

(Normalized to 25 °C)
Frequency Ratio

Frequency Ratio
0.800 0.800

0.600 0.600

0.400 0.400

0.200 0.200

0.000 0.000
-40 -15 10 35 60 85 110 135 -40 -15 10 35 60 85 110 135
Temperature (°C) Temperature (°C)

Figure 12. Frequency Ratio vs. Temperature (Constant Current). Figure 13. Frequency Ratio vs. Temperature (Inductor Current).

1.200 1.200 PI-5090-012315

PI-5089-012315

Normalized Output Current

1.000 1.000
(Normalized to 25 °C)
(Normalized to 25 °C)
Feedback Voltage

0.800 0.800

0.600 0.600

0.400 0.400

0.200 0.200

0.000 0.000
-40 -15 10 35 60 85 110 135 -40 -15 10 35 60 85 110 135
Temperature (°C) Temperature (°C)

Figure 14. Feedback Voltage vs. Temperature. Figure 15. Normalized Output Current vs. Temperature.

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Typical Performance Characteristics (cont.)

1.1 300

PI-5082-012315
PI-2213-012315
TCASE = 25 °C
250 TCASE = 100 °C
(Normalized to 25 °C)

Drain Current (mA)

Breakdown Voltage

200

1.0 150

100
Scaling Factors:
LNK6x3 1.0
50 LNK6x4 1.0
LNK6x5 1.5
LNK6x6 2.5
0.9 0
-50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10
Junction Temperature (°C) DRAIN Voltage (V)

Figure 16. Breakdown vs. Temperature. Figure 17. Output Characteristic.

1000 50
PI-5083-012315

PI-5084-012315
Drain Capacitance (pF)

40
Scaling Factors:
LNK6x3 1.0
100
Power (mW)

LNK6x4 1.0
Scaling Factors: 30 LNK6x5 1.5
LNK6x3 1.0 LNK6x6 2.5
LNK6x4 1.0
LNK6x5 1.5
LNK6x6 2.5 20
10

10

1 0
0 100 200 300 400 500 600 0 200 400 600
Drain Voltage (V) DRAIN Voltage (V)
Figure 18. COSS vs. Drain Voltage. Figure 19. Drain Capacitance Power.

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LinkSwitch-II
FB S
1 µF BP/M S
5 µF 50 kΩ 10 kΩ
.1 µF S

D S
4 kΩ
S1 S2
VIN
+
16 V
Curve
Tracer

To measure BVDSS, IDSS1, and IDSS2 follow these steps:

1) Close S1, open S2.
2) Power-up VIN source (16 V).
3) Open S1, close S2.
4) Measure I/V characteristics of DRAIN pin using the curve tracer. PI-4962-012915

Figure 20. Test Set-up for Leakage and Breakdown Tests.

680 µF 3.3 V
470 pF 200 V
+
RO VO
200 Ω

11.5 kΩ

+ 50 V

LinkSwitch-II
FB S
BP S
7.15 kΩ
S

10 µF D S

1) The transformer inductance is chosen to set the value of tON × IFB to 2 mA × µS.
2) RO is chosen to operate test circuit in the CC region.
3) VO is measured.
4) Output current is VO / RO.
PI-4963-012315

Figure 21. Test Set-up for Output Current Measurements.

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PDIP-8C (P Package)
⊕ D S .004 (.10) Notes:
-E- 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
.240 (6.10) 3. Dimensions shown do not include mold flash or other
.260 (6.60) protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
Pin 1 5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
.356 (9.05) 6. Lead width measured at package body.
-D-
.387 (9.83)
7. Lead spacing measured with the leads constrained to be
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM

-T-
SEATING .008 (.20)
PLANE .118 (3.00) .015 (.38)
.140 (3.56)

.300 (7.62) BSC

.100 (2.54) BSC .048 (1.22) .137 (3.48) (NOTE 7)
.014 (.36)
.053 (1.35) MINIMUM .300 (7.62) P08C
.022 (.56) ⊕T E D S .010 (.25) M .390 (9.91) PI-3933-081716

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 LNK603-606/613-616

SMD-8C (G Package)
Notes:
⊕ D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
.080 2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
.086 protrusions shall not exceed
.186 .006 (.15) on any side.
.372 (9.45) 3. Pin locations start with Pin 1,
.240 (6.10)
.388 (9.86) .286 .420 and continue counter-clock-
.260 (6.60)
⊕ E S .010 (.25) wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
for the omitted lead location
is .137 inch (3.48 mm).
Pin 1 Pin 1 5. Lead width measured at
.137 (3.48) package body.
MINIMUM Solder Pad Dimensions 6. D and E are referenced
.100 (2.54) (BSC) datums on the package
body.
.356 (9.05)
-D-
.387 (9.83)
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)

.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0 °- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08C
PI-4015-081716

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SO-8C (D Package)
0.10 (0.004) C A-B 2X
2 DETAIL A
4 B
4.90 (0.193) BSC

A 4
D
8 5

GAUGE
PLANE
SEATING
PLANE
2 3.90 (0.154) BSC 6.00 (0.236) BSC o
C 0-8
0.25 (0.010)
1.04 (0.041) REF
BSC
0.10 (0.004) C D
0.40 (0.016)
2X 1
Pin 1 ID 4 0.20 (0.008) C 1.27 (0.050)
1.27 (0.050) BSC 2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D

1.35 (0.053) 1.25 - 1.65

1.75 (0.069) DETAIL A
(0.049 - 0.065)

0.10 (0.004) 0.10 (0.004) C H

0.25 (0.010) 7X
SEATING PLANE

C 0.17 (0.007)
0.25 (0.010)

Reference
Solder Pad +
Dimensions
Notes:
1. JEDEC reference: MS-012.
2.00 (0.079) 4.90 (0.193) 2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
+ + + 5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
1.27 (0.050) 0.60 (0.024)
D07C PI-4526-012315

Part Ordering Information

• LinkSwitch Product Family
• II Series Number
• Package Identifier
G Plastic Surface Mount DIP
P Plastic DIP
D Plastic SO-8
• Package Material
G GREEN: Halogen Free and RoHS Compliant
• Tape & Reel and Other Options
Blank Standard Configurations
Tape & Reel, 1 k pcs minimum for G Package. 2.5 k pcs for D Package. Not
LNK 615 D G - TL TL
available for P Package.

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 LNK603-606/613-616

Revision Notes Date

C Final data sheet. 06/08
D Auto-restart time modified PCN-09131. 03/09
E Introduced Max Current Limit when V DRAIN is below 400 V. 07/09
F Added LNK616DG and LNK606DG. 01/10
G Updated Note 6 in Parameter Table. 02/10
H Updated due to DM process change. 05/13
H Specified Max BYPASS Pin Current. 03/14
I Figure removed “Test Set-up for FEEDBACK Pin Measurements” from previous version. Updated to latest Brand Style. 02/15
J Updated PDIP-8C (P Package) and SMD-8C (G Package) per PCN-16232. 08/16

17
www.power.com Rev. J 08/16
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, HiperTFS,
HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of
Power Integrations, Inc. Other trademarks are property of their respective companies. ©2016, Power Integrations, Inc.

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Power Integrations:
LNK603DG LNK613DG LNK604DG LNK614DG LNK605DG LNK615DG LNK606GG LNK616GG LNK606DG
LNK606DG-TL LNK616DG LNK616DG-TL LNK604PG LNK606PG LNK613PG LNK614DG-TL LNK605DG-TL
LNK604DG-TL LNK603DG-TL LNK606GG-TL LNK615DG-TL LNK603PG LNK613DG-TL LNK616GG-TL
LNK615PG LNK616PG LNK614PG LNK605PG