LNK362-364

LinkSwitch-XT Family
Energy Efficient, Low Power Off-Line Switcher IC

Product Highlights + +
DC
Optimized for Lowest System Cost Output
• Proprietary IC trimming and transformer construction
techniques enable Clampless™ designs with LNK362 LinkSwitch-XT
Wide Range
for lower system cost, component count and higher HV DC Input D
LNK362
efficiency FB

• Fully integrated auto-restart for short-circuit and BP

open loop protection S

• Self-biased supply – saves transformer auxiliary

winding and associated bias supply components a) Clampless flyback converter with LNK362 PI-4086-081005
• Frequency jittering greatly reduces EMI
• Meets HV creepage requirements between DRAIN and
+ +
all other pins both on the PCB and at the package DC
Output
• Lowest component count switcher solution
Features Superior to Linear/RCC
LinkSwitch-XT
• Accurate hysteretic thermal shutdown protection – Wide Range LNK363-364
HV DC Input D
automatic recovery improves field reliability FB
• Universal input range allows worldwide operation BP
• Simple ON/OFF control, no loop compensation S
needed
• Eliminates bias winding – simpler, lower cost
b) Flyback converter with LNK363/4 PI-4061-081005
transformer
• Very low component count – higher reliability and Figure 1. Typical Application with LinkSwitch-XT.

single side printed circuit board

• Auto-restart reduces delivered power by 95% during
short-circuit and open loop fault conditions Output Power Table(4)
• High bandwidth provides fast turn-on with no 230 VAC ±15% 85-265 VAC
overshoot and excellent transient load response Product3) Open Open
Adapter(1) Adapter(1)
Frame(2) Frame(2)
EcoSmart™– Extremely Energy-Efficient
• Easily meets all global energy efficiency regulations LNK362P/G/D 2.8 W 2.8 W 2.6 W 2.6 W
with no added components LNK363P/G/D 5W 7.5 W 3.7 W 4.7 W
• No-load consumption <300 mW without bias winding LNK364P/G/D 5.5 W 9W 4W 6W
at 265 VAC input (<50 mW with bias winding)
Table 1. Output Power Table.
• ON/OFF control provides constant efficiency to very
Notes:
light loads – ideal for mandatory CEC regulations 1. Minimum continuous power in a typical non-ventilated enclosed
Applications adapter measured at 50 °C ambient.
2. Minimum practical continuous power in an open frame design with
• Chargers/adapters for cell/cordless phones, PDAs, adequate heat sinking, measured at 50 °C ambient.
digital cameras, MP3/portable audio players, and 3. Packages: P: DIP-8B, G: SMD-8B, D: SO-8C. Please see Part
shavers Ordering Information.
4. See Key Application Considerations section for complete description
• Supplies for appliances, industrial systems, and of assumptions.
metering
Description cycle current limit and thermal shutdown circuitry onto
LinkSwitch™-XT incorporates a 700 V power MOSFET, a monolithic IC. The start-up and operating power are
oscillator, simple ON/OFF control scheme, a high-voltage derived directly from the DRAIN pin, eliminating the need
switched current source, frequency jittering, cycle-by- for a bias winding and associated circuitry.

www.power.com May 2015

 LNK362-364

BYPASS DRAIN
(BP) (D)
REGULATOR
5.8 V

FAULT
PRESENT

AUTO-
RESTART BYPASS PIN
COUNTER UNDER-VOLTAGE
+
CLOCK
5.8 V -
RESET 4.8 V

CURRENT LIMIT
6.3 V COMPARATOR

- VI
LIMIT

JITTER
CLOCK

DCMAX
THERMAL
SHUTDOWN
OSCILLATOR
FEEDBACK
VFB -VTH
(FB)
S Q

R Q
LEADING
EDGE
BLANKING

SOURCE
(S)

PI-4232-110205

Figure 2. Functional Block Diagram.

Pin Functional Description

DRAIN (D) Pin:
Power MOSFET drain connection. Provides internal P Package (DIP-8B)
operating current for both start-up and steady-state G Package (SMD-8B) D Package (SO-8C)
operation.
S 1 8 S 1 8
BYPASS (BP) Pin: BP S
Connection point for a 0.1 µF external bypass capacitor S 2 7 S FB
2 7
S
for the internally generated 5.8 V supply. If an external 6
BP 3 S
bias winding is used, the current into the BP pin must not 4 5
exceed 1 mA. FB 4 5 D
D S

FEEDBACK (FB) Pin:

During normal operation, switching of the power MOSFET
PI-7192-110413
is controlled by this pin. MOSFET switching is disabled
when a current greater than 49 µA is delivered into this Figure 3. Pin Configuration.
pin.

SOURCE (S) Pin:

This pin is the power MOSFET source connection.
It is also the ground reference for the BYPASS and
FEEDBACK pins.

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 LNK362-364

LinkSwitch-XT Functional Description BYPASS pin through an external resistor. This facilitates
powering of the device externally through a bias winding
LinkSwitch-XT combines a high-voltage power MOSFET to decrease the no-load consumption to less than 50 mW.
switch with a power supply controller in one device. Unlike
conventional PWM (pulse width modulator) controllers, BYPASS Pin Undervoltage
a simple ON/OFF control regulates the output voltage. The The BYPASS pin undervoltage circuitry disables the power
controller consists of an oscillator, feedback (sense and MOSFET when the BYPASS pin voltage drops below 4.8 V.
logic) circuit, 5.8 V regulator, BYPASS pin undervoltage Once the BYPASS pin voltage drops below 4.8 V, it must
circuit, over-temperature protection, frequency jittering, rise back to 5.8 V to enable (turn-on) the power MOSFET.
current limit circuit, and leading edge blanking integrated
with a 700 V power MOSFET. The LinkSwitch-XT Over-Temperature Protection
incorporates additional circuitry for auto-restart. The thermal shutdown circuitry senses the die temperature.
The threshold is set at 142 °C typical with a 75 °C
Oscillator hysteresis. When the die temperature rises above this
The typical oscillator frequency is internally set to an threshold (142 °C) the power MOSFET is disabled and
average of 132 kHz. Two signals are generated from the remains disabled until the die temperature falls by 75 °C,
oscillator: the maximum duty cycle signal (DCMAX) and the at which point it is re-enabled.
clock signal that indicates the beginning of each cycle.
Current Limit
The oscillator incorporates circuitry that introduces a The current limit circuit senses the current in the power
small amount of frequency jitter, typically 9 kHz peak- MOSFET. When this current exceeds the internal threshold
to-peak, to minimize EMI emission. The modulation rate (ILIMIT), the power MOSFET is turned off for the remainder
of the frequency jitter is set to 1.5 kHz to optimize EMI of that cycle. The leading edge blanking circuit inhibits
reduction for both average and quasi-peak emissions. The the current limit comparator for a short time (tLEB) after the
frequency jitter should be measured with the oscilloscope power MOSFET is turned on. This leading edge blanking
triggered at the falling edge of the DRAIN waveform. The time has been set so that current spikes caused by
waveform in Figure 4 illustrates the frequency jitter. capacitance and rectifier reverse recovery time will not
cause premature termination of the switching pulse.
Feedback Input Circuit
The feedback input circuit at the FB pin consists of a Auto-Restart
low impedance source follower output set at 1.65 V for In the event of a fault condition such as output overload,
LNK362 and 1.63 V for LNK363/364. When the current output short-circuit, or an open loop condition,
delivered into this pin exceeds 49 µA, a low logic level LinkSwitch-XT enters into auto-restart operation. An
(disable) is generated at the output of the feedback circuit. internal counter clocked by the oscillator gets reset
This output is sampled at the beginning of each cycle every time the FB pin is pulled high. If the FB pin is not
on the rising edge of the clock signal. If high, the power pulled high for approximately 40 ms, the power MOSFET
MOSFET is turned on for that cycle (enabled), otherwise switching is disabled for 800 ms. The auto-restart
the power MOSFET remains off (disabled). Since the alternately enables and disables the switching of the
sampling is done only at the beginning of each cycle, power MOSFET until the fault condition is removed.
subsequent changes in the FB pin voltage or current
600
during the remainder of the cycle are ignored.
PI-4047-110205
500 V
5.8 V Regulator and 6.3 V Shunt Voltage Clamp DRAIN
The 5.8 V regulator charges the bypass capacitor 400
connected to the BYPASS pin to 5.8 V by drawing a
current from the voltage on the DRAIN, whenever the 300
MOSFET is off. The BYPASS pin is the internal supply
voltage node. When the MOSFET is on, the LinkSwitch-XT 200
runs off of the energy stored in the bypass capacitor.
100
Extremely low power consumption of the internal circuitry
allows the device to operate continuously from the current 0
drawn from the DRAIN pin. A bypass capacitor value of 136.5 kHz
0.1 µF is sufficient for both high frequency decoupling and 127.5 kHz
energy storage.

In addition, there is a 6.3 V shunt regulator clamping the 0 5 10

BYPASS pin at 6.3 V when current is provided to the Time (µs)
Figure 4. Frequency Jitter.

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 LNK362-364

CY1
100 pF
250 VAC

C4
L1 T1 330 µF 6.2 V,
1 mH EE16 9 16 V 322 mA
4
5 J3
D5
1N4934
3 8
NC NC J4
RF1 VR1
D1 D2 R1 BZX79-
8.2 Ω 1N4005 1N4005 3.9 k
J1 2.5 W B5V1
1/8 W 5.1 V, 2%
R2
390 Ω
85-265 C1 C2 1/8 W
VRMS 3.3 µF 3.3 µF
400 V 400 V
R3
1k
J2 U2 1/8 W
D PC817A
LinkSwitch-XT FB
U1 BP
LNK362P
D3 D4 S
C3
1N4005 1N4005 L2 100 nF
1 mH 50 V
PI-4162-110205

Figure 5. 2 W Universal Input CV Adapter using LNK362.

Applications Example The rectified and filtered input voltage is applied to the
primary winding of T1. The other side of the primary
A 2 W CV Adapter is driven by the integrated MOSFET in U1. No primary
The schematic shown in Figure 5 is a typical implementation clamp is required as the low value and tight tolerance of
of a universal input, 6.2 V ±7%, 322 mA adapter using the LNK362 internal current limit allows the transformer
LNK362. This circuit makes use of the clampless primary winding capacitance to provide adequate
technique to eliminate the primary clamp components and clamping of the leakage inductance drain voltage spike.
reduce the cost and complexity of the circuit.
The secondary of the flyback transformer T1 is rectified
The EcoSmart features built into the LinkSwitch-XT family by D5, a low cost, fast recovery diode, and filtered by
allow this design to easily meet all current and proposed C4, a low ESR capacitor. The combined voltage drop
energy efficiency standards, including the mandatory across VR1, R2 and the LED of U2 determines the
California Energy Commission (CEC) requirement for output voltage. When the output voltage exceeds this
average operating efficiency. level, current will flow through the LED of U2. As the LED
The AC input is rectified by D1 to D4 and filtered by the current increases, the current fed into the FEEDBACK pin
bulk storage capacitors C1 and C2. Resistor RF1 is a of U1 increases until the turnoff threshold current (~49 µA)
flameproof, fusible, wire wound type and functions as a is reached, disabling further switching cycles of U1. At
fuse, inrush current limiter and, together with the π filter full load, almost all switching cycles will be enabled, and
formed by C1, C2, L1 and L2, differential mode noise at very light loads, almost all the switching cycles will be
attenuator. Resistor R1 damps ringing caused by L1 disabled, giving a low effective frequency and providing
and L2. high light load efficiency and low no-load consumption.

This simple input stage, together with the frequency Resistor R3 provides 1 mA through VR1 to bias the Zener
jittering of LinkSwitch-XT, a low value Y1 capacitor and closer to its test current. Resistor R2 allows the output
PI’s E-Shield™ windings within T1, allow the design to voltage to be adjusted to compensate for designs where
meet both conducted and radiated EMI limits with the value of the Zener may not be ideal, as they are only
>10 dBmV margin. The low value of CY1 is important to available in discrete voltage ratings. For higher output
meet the requirement for a very low touch current (the line accuracy, the Zener may be replaced with a reference IC
frequency current that flows through CY1) often specified such as the TL431.
for adapters, in this case <10 µA.

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 LNK362-364

The LinkSwitch-XT is completely self-powered from the 2. For designs where PO ≤ 2 W, a two-layer primary
DRAIN pin, requiring only a small ceramic capacitor C3 should be used to ensure adequate primary intra-
connected to the BYPASS pin. No auxiliary winding on the winding capacitance in the range of 25 pF to 50 pF.
transformer is required. 3. For designs where 2 < PO ≤ 2.5 W, a bias winding
should be added to the transformer using a standard
Key Application Considerations recovery rectifier diode to act as a clamp. This bias
LinkSwitch-XT Design Considerations winding may also be used to externally power the
device by connecting a resistor from the bias-winding
Output Power Table capacitor to the BYPASS pin. This inhibits the
The data sheet maximum output power table (Table 1) internal high-voltage current source, reducing device
represents the maximum practical continuous output dissipation and no-load consumption.
power level that can be obtained under the following 4. For designs where PO > 2.5 W clampless designs are
assumed conditions: not practical and an external RCD or Zener clamp
should be used.
1. The minimum DC input voltage is 90 V or higher for 5. Ensure that worst-case high line, peak drain voltage is
85 VAC input, or 240 V or higher for 230 VAC input or below the BVDSS specification of the internal MOSFET
115 VAC with a voltage doubler. The value of the input and ideally ≤ 650 V to allow margin for design variation.
capacitance should be large enough to meet these
criteria for AC input designs. †For 110 VAC only input designs it may be possible to
2. Secondary output of 6 V with a fast PN rectifier diode. extend the power range of clampless designs to include
3. Assumed efficiency of 70%. the LNK363. However, the increased leakage ringing may
4. Voltage only output (no secondary-side constant degrade EMI performance.
current circuit).
5. Discontinuous mode operation (KP >1). **VOR is the secondary output plus output diode forward
6. A primary clamp (RCD or Zener) is used. voltage drop that is reflected to the primary via the turns
7. The part is board mounted with SOURCE pins ratio of the transformer during the diode conduction time.
soldered to a sufficient area of copper to keep the The VOR adds to the DC bus voltage and the leakage spike
SOURCE pin temperature at or below 100 °C. to determine the peak drain voltage.
8. Ambient temperature of 50 °C for open frame designs
Audible Noise
and an internal enclosure temperature of 60 °C for
The cycle skipping mode of operation used in LinkSwitch-XT
adapter designs.
can generate audio frequency components in the transformer.
Below a value of 1, KP is the ratio of ripple to peak To limit this audible noise generation, the transformer
primary current. Above a value of 1, KP is the ratio of should be designed such that the peak core flux density is
primary MOSFET OFF time to the secondary diode below 1500 Gauss (150 mT). Following this guideline and
conduction time. Due to the flux density requirements using the standard transformer production technique of
described below, typically a LinkSwitch-XT design will be dip varnishing practically eliminates audible noise. Vacuum
discontinuous, which also has the benefits of allowing impregnation of the transformer should not be used due
lower cost fast (instead of ultra-fast) output diodes and to the high primary capacitance and increased losses
reducing EMI. that result. Higher flux densities are possible, however
careful evaluation of the audible noise performance should
Clampless Designs be made using production transformer samples before
Clampless designs rely solely on the drain node capacitance approving the design.
to limit the leakage inductance induced peak drain-to-
source voltage. Therefore, the maximum AC input line Ceramic capacitors that use dielectrics, such as Z5U, when
voltage, the value of VOR, the leakage inductance energy, a used in clamp circuits may also generate audio noise. If
function of leakage inductance and peak primary current, this is the case, try replacing them with a capacitor having
and the primary winding capacitance determine the peak a different dielectric or construction, for example a film type.
drain voltage. With no significant dissipative element present, LinkSwitch-XT Layout Considerations
as is the case with an external clamp, the longer duration
of the leakage inductance ringing can increase EMI. See Figure 6 for a recommended circuit board layout for
LinkSwitch-XT (P & G package).
The following requirements are recommended for a
universal input or 230 VAC only clampless design: Single Point Grounding
Use a single point ground connection from the input filter
1. A clampless design should only be used for PO ≤ 2.5 W, capacitor to the area of copper connected to the SOURCE
using the LNK362† and a VOR** ≤ 90 V. pins.

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 LNK362-364

Input Filter
TOP VIEW Capacitor

Y1-
Capacitor

FB
D

LinkSwitch-XT
T
r
S
a
BP
n S S
s - HV DC +
S
f INPUT
o S
r S
m
CBP
e
r

Opto-
coupler

+
DC Maximize hatched copper
OUT
- areas ( ) for optimum
heatsinking
Output Filter
Capacitor
PI-4155-102705

Figure 6. Recommended Printed Circuit Layout for LinkSwitch-XT using P Package in a Flyback Converter Configuration.

Bypass Capacitor CBP Y-Capacitor

The BYPASS pin capacitor should be located as near as The placement of the Y-type cap should be directly from
possible to the BYPASS and SOURCE pins. the primary input filter capacitor positive terminal to the
common/return terminal of the transformer secondary.
Primary Loop Area
Such a placement will route high magnitude common-
The area of the primary loop that connects the input
mode surge currents away from the LinkSwitch-XT
filter capacitor, transformer primary and LinkSwitch-XT
device. Note that if an input pi (C, L, C) EMI filter is used,
together should be kept as small as possible.
then the inductor in the filter should be placed between
Primary Clamp Circuit the negative terminals of the input filter capacitors.
A clamp is used to limit peak voltage on the DRAIN pin
Optocoupler
at turn-off. This can be achieved by using an RCD clamp
Place the optocoupler physically close to the LinkSwitch-XT
or a Zener (~200 V) and diode clamp across the primary
to minimize the primary-side trace lengths. Keep the high
winding. In all cases, to minimize EMI, care should
current, high-voltage drain and clamp traces away from
be taken to minimize the circuit path from the clamp
the optocoupler to prevent noise pick up.
components to the transformer and LinkSwitch-XT.
Output Diode
Thermal Considerations
For best performance, the area of the loop connecting
The copper area underneath the LinkSwitch-XT acts not
the secondary winding, the output diode and the output
only as a single point ground, but also as a heatsink. As
filter capacitor should be minimized. In addition, sufficient
this area is connected to the quiet source node, it should
copper area should be provided at the anode and
be maximized for good heat sinking of LinkSwitch-XT.
cathode terminals of the diode for heat sinking. A larger
The same applies to the cathode of the output diode.

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 LNK362-364

TOP VIEW

Y1-
Capacitor
Input Filter
Capacitor

D
S

LinkSwitch-XT
T
r S
a FB
n S
s S
f BP
o
r
m
e - +
r HV DC
INPUT
CBP

Opto-
coupler

Maximize hatched copper

areas ( ) for optimum
heatsinking
Output Filter
Capacitor + DC -
OUT

PI-4585-021607

Figure 7. Recommended Printed Circuit Layout for LinkSwitch-XT using D Package in a Flyback Converter Configuration.

area is preferred at the quiet cathode terminal. A large edge current spikes at start-up. Repeat under steady
anode area can increase high frequency radiated EMI. state conditions and verify that the leading-edge current
spike event is below ILIMIT(MIN) at the end of the tLEB(MIN).
Quick Design Checklist Under all conditions, the maximum drain current should
be below the specified absolute maximum ratings.
As with any power supply design, all LinkSwitch-XT
3. Thermal Check – At specified maximum output
designs should be verified on the bench to make sure
power, minimum input voltage and maximum ambient
that component specifications are not exceeded under
temperature, verify that the temperature specifications
worst-case conditions. The following minimum set of
are not exceeded for LinkSwitch-XT, transformer,
tests is strongly recommended:
output diode and output capacitors. Enough thermal
1. Maximum drain voltage – Verify that VDS does not margin should be allowed for part-to-part variation of
exceed 650 V at the highest input voltage and peak the RDS(ON) of LinkSwitch-XT as specified in the data
(overload) output power. The 50 V margin to the sheet. Under low line, maximum power, a maximum
700 V BVDSS specification gives margin for design LinkSwitch-XT SOURCE pin temperature of 105 °C is
variation, especially in clampless designs. recommended to allow for these variations.
2. Maximum drain current – At maximum ambient
Design Tools
temperature, maximum input voltage and peak output
(overload) power, verify drain current waveforms for any Up-to-date information on design tools can be found at the
signs of transformer saturation and excessive leading- Power Integrations website: www.power.com

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 LNK362-364

Absolute Maximum Ratings(1,5)

DRAIN Pin Voltage .............................................. -0.3 V to 700 V Notes:
Peak DRAIN Pin Current: LNK362.................200 mA (375 mA)(2) 1. All voltages referenced to SOURCE, TA = 25 °C.
....................................................................
LNK363/364..........400 mA (750 mA)(2) 2. The higher peak DRAIN current is allowed while the DRAIN
FEEDBACK Pin Voltage ..........................................-0.3 V to 9 V voltage is simultaneously less than 400 V.
FEEDBACK Pin Current ................................................. 100 mA 3. Normally limited by internal circuitry.
BYPASS Pin Voltage................................................-0.3 V to 9 V 4. 1/16 in. from case for 5 seconds.
Storage Temperature ...................................... -65 °C to 150 °C 5. Maximum ratings specified may be applied, one at a time,
Operating Junction Temperature(3) ................... -40 °C to 150 °C without causing permanent damage to the product.
Lead Temperature(4) ..........................................................260 °C Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect product reliability.

Thermal Resistance
Thermal Resistance: P or G Package: Notes:
(qJA) ........................... 70 °C/W(3); 60 °C/W(4) 1. Measured on pin 2 (SOURCE) close to plastic interface.
(qJC)(1) ............................................... 11 °C/W 2. Measured on pin 8 (SOURCE) close to plastic interface.
D Package: 3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
(qJA) ...............................100 °C/W(3); 80 °C/W(4) 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(qJC)(2) ............................................... 30 °C/W

Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 8
(Unless Otherwise Specified)
Control Functions
Average 124 132 140
Output Frequency fOSC TJ = 25 °C kHz
Peak-Peak Jitter 9

Maximum Duty Cycle DCMAX S2 Open 60 %

FEEDBACK Pin Turn-Off
IFB TJ = 25 °C 30 49 68 mA
Threshold Current

FEEDBACK Pin Voltage TJ = 0 °C to LNK362 1.55 1.65 1.75

VFB V
at Turn-Off Threshold 125 °C LNK363-364 1.53 1.63 1.73
VFB ≥2 V
IS1 (MOSFET Not Switching) 200 250 mA
See Note A
DRAIN Supply Current
FEEDBACK Open
IS2 (MOSFET Switching) 250 300 mA
See Notes A, B
VBP = 0 V, TJ = 25 °C
ICH1 -5.5 -3.5 -1.8
BYPASS Pin See Note C
mA
Charge Current VBP = 4 V, TJ = 25 °C
ICH2 -3.8 -2.3 -1.0
See Note C
BYPASS Pin
VBP 5.55 5.8 6.10 V
Voltage
BYPASS Pin
VBPH 0.8 1.0 1.2 V
Voltage Hysteresis

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 LNK362-364

Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 8 Min Typ Max Units
(Unless Otherwise Specified)
Control Functions (cont)
BYPASS Pin
IBPSC See Note D 68 mA
Supply Current

Circuit Protection
di/dt = 30 mA/ms
LNK362 130 140 150
TJ = 25 °C
ILIMIT
di/dt = 42 mA/ms
Current Limit (See Note LNK363 195 210 225 mA
TJ = 25 °C
E)
di/dt = 50 mA/ms
LNK364 233 250 268
TJ = 25 °C

di/dt = 30 mA/ms
LNK362 2199 2587
TJ = 25 °C

di/dt = 42 mA/ms
Power Coefficient I2f LNK363 4948 5821 A2Hz
TJ = 25 °C

di/dt = 50 mA/ms
LNK364 7425 8250
TJ = 25 °C

Leading Edge TJ = 25 °C LNK362 300 375

tLEB ns
Blanking Time See Note F LNK363/364 170 250

TJ = 25 °C
Current Limit Delay tILD 125 ns
See Note F

Thermal Shutdown
TSD 135 142 150 °C
Temperature

Thermal Shutdown
TSHD See Note G 75 °C
Hysteresis

Output

LNK362 TJ = 25 °C 48 55
ID = 14 mA TJ = 100 °C 76 88

ON-State LNK363 TJ = 25 °C 29 33
RDS(ON) W
Resistance ID = 21 mA TJ = 100 °C 46 54

LNK364 TJ = 25 °C 24 28
ID = 25 mA TJ = 100 °C 38 45

VBP = 6.2 V, VFB ≥2 V,

OFF-State Drain
IDSS VDS = 560 V, 50 mA
Leakage Current
TJ = 125 °C

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 LNK362-364

Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 8
(Unless Otherwise Specified)

Output (cont)
Breakdown VBP = 6.2 V, VFB ≥ 2 V,
BVDSS 700 V
Voltage See Note H, TJ = 25 °C

DRAIN Supply Voltage 50 V

Output Enable Delay tEN See Figure 10 10 ms

Output Disable
tDST 0.5 ms
Setup Time

Auto-Restart TJ = 25 °C LNK362 40
tAR ms
ON-Time See Note I LNK363-364 45

Auto-Restart
DCAR 5 %
Duty Cycle

NOTES:
A. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is ≥2 V (MOSFET not switching)
and the sum of IS2 and IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching).
B Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BYPASS pin current at 6 V.
C. See Typical Performance Characteristics section Figure 15 for BYPASS pin start-up charging waveform.
D. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK
pins and not any other external circuitry.
E. For current limit at other di/dt values, refer to Figure 14.
F. This parameter is guaranteed by design.
G. This parameter is derived from characterization.
H. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to
but not exceeding minimum BVDSS.
I. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).

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 LNK362-364

470 Ω
5W 470 kΩ
D FB
S1 S2
BP
50 V 50 V
S S 0.1 µF
S S

PI-3490-060204

Figure 8. LinkSwitch-XT General Test Circuit.

DCMAX
t2 (internal signal)
t1 tP
HV
90% 90%
FB
DRAIN t1
VOLTAGE D=
t2 tEN
VDRAIN
10%
0V 1
tP =
fOSC
PI-2048-021015 PI-3707-112503

Figure 9. LinkSwitch-XT Duty Cycle Measurement. Figure 10. LinkSwitch-XT Output Enable Timing.

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 LNK362-364

Typical Performance Characteristics

1.1 1.2

PI-2213-012315

PI-2680-021809
1.0
(Normalized to 25 °C)

(Normalized to 25 °C)
Breakdown Voltage

Output Frequency
0.8

1.0 0.6

0.4

0.2

0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
Junction Temperature (°C) Junction Temperature (°C)
Figure 11. Breakdown vs. Temperature. Figure 12. Frequency vs. Temperature.

1.4 1.4
PI-4091-081505

PI-4092-081505
1.2 Normalized Current Limit 1.2
(Normalized to 25 °C)

1.0 1.0
Current Limit

0.8 0.8 Normalized

Normalized Current
TBD
di/dt = 1 Limit = 1
0.6 0.6 LNK362 30 mA/µs 140 mA
LNK363 42 mA/µs 210 mA
LNK364 50 mA/µs 250 mA
0.4 0.4

0.2 0.2

0 0
-50 0 50 100 150 1 2 3 4 5
Temperature (°C) Normalized di/dt
Figure 13. Current Limit vs. Temperature. Figure 14. Current Limit vs. di/dt.

7 400
PI-4093-081605
PI-2240-012301

350
6
BYPASS Pin Voltage (V)

25 °C
DRAIN Current (mA)

300
5 100 °C
250
4
200
3
Scaling Factors:
150 LNK362 0.5
2
LNK363 0.8
100 LNK364 1.0
1
50
0
0
0 2 4 6 8 10 12 14 16 18 20
0 0.2 0.4 0.6 0.8 1.0
DRAIN Voltage (V)
Time (ms)
Figure 15. BYPASS Pin Start-up Waveform. Figure 16. Output Characteristics.

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 LNK362-364

Typical Performance Characteristics (cont.)

1000

PI-4094-081605
Drain Capacitance (pF)
100
Scaling Factors:
LNK362 0.5
LNK363 0.8
LNK364 1.0
10

1
0 100 200 300 400 500 600
Drain Voltage (V)
Figure 17. COSS vs. Drain Voltage.

Part Ordering Information

• LinkSwitch Product Family
• XT Series Number
• Package Identifier
G Plastic Surface Mount DIP
P Plastic DIP
D Plastic SO-8
• Lead Finish
N Pure Matte Tin (RoHS Compliant)
G RoHS Compliant and Halogen Free (P and D package only)
• Tape & Reel and Other Options
Blank Standard Configurations
Tape & Reel, 1 k pcs minimum for G Package. 2.5 k pcs for D
LNK 364 G N - TL TL
Package. Not available for P Package.

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 LNK362-364

PDIP-8B (P Package)
⊕D S .004 (.10)
.137 (3.48) Notes:
MINIMUM 1. Package dimensions conform to JEDEC specification
-E-
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
3. Dimensions shown do not include mold flash or other
.240 (6.10) protrusions. Mold flash or protrusions shall not exceed
.260 (6.60) .006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 6 is omitted.
5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
Pin 1 6. Lead width measured at package body.
7. Lead spacing measured with the leads constrained to be
.367 (9.32) perpendicular to plane T.
-D- .387 (9.83)
.057 (1.45)
.068 (1.73)
(NOTE 6)

.125 (3.18) .015 (.38)

.145 (3.68) MINIMUM

-T-
SEATING .008 (.20)
PLANE .120 (3.05) .015 (.38)
.140 (3.56)

.300 (7.62) BSC

.100 (2.54) BSC .048 (1.22) (NOTE 7)

.014 (.36)
.053 (1.35)
.300 (7.62) P08B
.022 (.56) ⊕T E D S .010 (.25) M .390 (9.91)
PI-2551-040110

SMD-8B (G Package)
⊕D S .004 (.10) .137 (3.48) Notes:
MINIMUM 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
protrusions shall not exceed
.420 .006 (.15) on any side.
.240 (6.10) .372 (9.45) 3. Pin locations start with Pin 1,
.260 (6.60) .388 (9.86) and continue counter-clock-
⊕ E S .010 (.25) .046 .060 .060 .046 wise to Pin 8 when viewed
from the top. Pin 6 is omitted.
4. Minimum metal to metal
.080 spacing at the package body
Pin 1 for the omitted lead location
Pin 1 is .137 inch (3.48 mm).
.086 5. Lead width measured at
.186 package body.
.100 (2.54) (BSC) 6. D and E are referenced
.286
datums on the package body.
Solder Pad Dimensions
.367 (9.32)
-D-
.387 (9.83)
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)

.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0 °- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08B
PI-2546-031715

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 LNK362-364

SO-8C (D Package)
0.10 (0.004) C A-B 2X
2 DETAIL A
4 B
4.90 (0.193) BSC

A 4
D
8 5

GAUGE
PLANE
SEATING
PLANE
2 3.90 (0.154) BSC 6.00 (0.236) BSC o
C 0-8
0.25 (0.010)
1.04 (0.041) REF
BSC
0.10 (0.004) C D
0.40 (0.016)
2X 1
Pin 1 ID 4 0.20 (0.008) C 1.27 (0.050)
1.27 (0.050) BSC 2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D

1.35 (0.053) 1.25 - 1.65

1.75 (0.069) DETAIL A
(0.049 - 0.065)

0.10 (0.004) 0.10 (0.004) C H

0.25 (0.010) 7X
SEATING PLANE

C 0.17 (0.007)
0.25 (0.010)

Reference
Solder Pad +
Dimensions
Notes:
1. JEDEC reference: MS-012.
2.00 (0.079) 4.90 (0.193) 2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
+ + + 5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
1.27 (0.050) 0.60 (0.024)
D07C PI-4526-040110

Revision Notes Date

B Released Final Data Sheet. 11/05
C Corrected Application Example section. 12/05
D Added SO-8C package. 2/07
E Updated Part Ordering Information section with Halogen Free 11/08
F Updated with new Brand Style. 05/15

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 LNK362-364

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations.
A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, InnoSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero,
HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are
trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2015, Power Integrations, Inc.

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