VIPER35

Datasheet

Quasi-resonant high performance off line high voltage converter

Features
• 800 V avalanche-rugged power MOSFET allowing ultra wide range input VAC
to be achieved
• Embedded HV start-up and senseFET
• Built-in soft-start
• Quasi-resonant current mode PWM controller with drain current limit (IDlim)
• Multifunction ZCD pin:
– Zero-current detection
– OCP threshold (IDlim) setup
– Output OVP (auto-restart)
SO 16 N
– Feed-forward compensation
• Support isolated flyback topology with optocoupler
• Frequency limit:
– 136 kHz (L type), 225 kHz (H type)
• Less than 30 mW @ 230 VAC in no-load condition
Product status link • Brown-out set through resistor divider
VIPER35 • Short-circuit protection (auto-restart)
• Hysteretic thermal shutdown

Product label
Application
• Auxiliary power supply
• Adapter/charger for PDA, camcorders, shavers, tablet, video games, STB
• Supplies for industrial systems, metering, appliances

Description
VIPER35 is a high voltage converter, which smartly integrates an 800 V rugged
power MOSFET with a quasi-resonant current mode PWM control. This IC meets
severe energy saving standards as it has very low consumption and operates in burst
mode under light load conditions.
The VIPER35 features the brown-out enabling the IC to set the switch-off and switch-
on threshold independently one of each other. The quasiresonant operation reduces
the level of EMI and the quantity of components in the application.
The quasi-resonant operation reduces the switching losses and improves power
conversion efficiency. The device features high level protections such as: output
overvoltage, shortcircuit and thermal shutdown with hysteresis.
After the removal of a fault condition, the IC is automatically restarted.

DS10628 - Rev 5 - December 2022 www.st.com

For further information contact your local STMicroelectronics sales office.
 VIPER35
Block diagram

1 Block diagram

Figure 1. Block diagram

Figure 2. Basic application schematic

DS10628 - Rev 5 page 2/38

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Typical output power

2 Typical output power

Table 1. Typical output power

230 VAC 85-265 VAC

Part number
Adapter (1) Open frame (2) Adapter (1) Open frame (2)

VIPER35 20 W 22 W 15 W 16 W

1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.

2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heatsinking.

DS10628 - Rev 5 page 3/38

 VIPER35
Pin description

3 Pin description

Figure 3. Pin description

Table 2. Pin settings

No. Name Function

1,2 GND Device ground and source ofthe power MOSFET.

3 N.C. Not internally connected. Itcan be connected to GND.
Not available for user. This pin is mechanically connected to the
4 N.A. controller die pad of the frame. In order to improve the noise
immunity it should be connected to GND (pin 1, 2).
Supply voltage ofthe control section. This pin provides the charging
5 VDD
current of the external capacitor during the power-up.
Multifunction pin:
1. Zero-current detection for quasi-resonant operations.
2. Drain current limit (IDlim) setup for overcurrent protection
6 ZCD (RLIM).
3. Feed-forward compensation (RFF) setup.
4. Output overvoltage protection (resistor divider ROVP / RLIM)
setup.
Control input for duty cycle control. Internal current generator
provides bias current for loop regulation. A voltage below the
7 FB threshold VFBbm activates the burst-mode operation. A level close
to the threshold VFBlin means that the cycle-by-cycle overcurrent set-
point is close.
Brown-out protection input with hysteresis. A voltage below the
threshold VBRth shuts down (not latch) the device and lowers the
8 BR power consumption. The device operation restarts as the voltage
exceeds the threshold VBRth + VBRhyst. It must be connected to
ground when it is not used.
Not internally connected. These pins must be left floating in order to
9 to 12 N.C.
get a safe clearance distance.
High voltage drain pin. The built-in high voltage switched start-up
13 to 16 DRAIN bias current is drawn from this pin. Pins connected to the metal frame
facilitate heat dissipation.

DS10628 - Rev 5 page 4/38

 VIPER35
Absolute maximum ratings and thermal data

4 Absolute maximum ratings and thermal data

Table 3. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

VDRAIN Drain-to-source (ground) voltage 800 V

EAV Repetitive avalanche energy (limited by TJ = 150 °C) 5 mJ

IAR Repetitive avalanche current (limited by TJ = 150 °C) 1.5 A

IDRAIN Single pulse drain current 3 A

VZCD Input pin voltage (with IZCD = 1 mA) -0.3 Self limited V

VFB Input pin voltage -0.3 5.5 V

VBR Input pin voltage (with IBR = 0.25 mA) -0.3 Self limited V

VDD Supply voltage -0.3 Self limited V

IDD Input current 25 mA

PTOT Power dissipation at TA<60 °C 1.5 W

TJ Operating junction temperature range -40 150 °C

TSTG Storage temperature -55 150 °C

Table 4. Thermal data

Symbol Parameter Max. Unit

RthJP Thermal resistance junction pin (dissipated power = 1 W) 35 °C/W

RthJA Thermal resistance junction ambient (dissipated power = 1 W) 110 °C/W

RthJA Thermal resistance junction ambient (1) (dissipated power = 1 W) 80 °C/W

1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq inch) of Cu (35 μm thick).

DS10628 - Rev 5 page 5/38

 VIPER35
Electrical characteristics

5 Electrical characteristics

Table 5. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

TJ= -40 to 125 °C, VDD= 14 V (1) (unless otherwise specified)

IDRAIN = 1 mA, VFB = GND TJ

VBVDSS Breakdown voltage 800 V
= 25 °C
VDRAIN = 800 V
IOFF Off-state drain current 60 uA
VFB = GND, TJ = 25 °C

IDRAIN = 0.4 A, VFB = 3 V

4.5 Ω
VBR = GND, TJ = 25 °C
Drain-source on- state
RDS(on)
resistance IDRAIN = 0.4 A, VFB = 3 V
9 Ω
VBR = GND, TJ=125 °C

Effective (energy related)

COSS VDRAIN = 0 to 640 V 17 pF
output capacitance
Voltage
TJ = -40 to 125 °C (unless otherwise specified)

VDRAIN_START Drain-source start voltage 60 80 100 V

VDRAIN = 120 V

Start-up charging current VBR = GND

IDDch1 -2 -3 -4 mA
(power-up) VFB = GND
VDD = 4 V

VDRAIN = 120 V

Start-up charging current VBR = GND

IDDch2 -0.4 -0.6 -0.8 mA
(auto-restart) VFB = GND
VDD = 5 V, after fault

VDD Operating voltage range After turn-on 8.5 23.5 V

VDDclamp Clamp voltage IDD = 20 mA 23.5 V

VDDon VDD start-up threshold 13 14 15 V

VDRAIN = 120 V
VDD undervoltage shutdown
VDDoff VBR = GND 7.5 8 8.5 V
threshold
VFB = GND
VDD(RESTART) VDD restart voltage threshold 4 4.5 5 V

Current
VFB = GND
Operating supply current, VBR = GND
IDD0 0.6 0.7 mA
notswitching
VDD = 10 V (2)

VDRAIN = 120 V

VDD = 16 V
Operating supply current
IDD1 ZCD switching @100kHz 2 3 m
switching
Resistive load: 100 Ω
VFB = 2.5 V

DS10628 - Rev 5 page 6/38

 VIPER35
Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Operating supply current

IDD_FAULT VDD = 10 V 400 uA
withprotection tripping
IDDoff Operating supply current VDD <VDDoff 270 uA

Feedback pin
TJ = -40 to 125 °C (unless otherwise specified)

VFBolp Overload shutdown threshold 4.5 4.8 5.2 V

VFBlin Linear dynamics upper limit 3.1 3.3 3.5 V

VFBbm Burst mode threshold Voltage falling 0.56 0.6 0.64 V

VFBbmhys Burst mode hysteresis Voltage rising 100 mV

VFB = 0.3 V -150 -215 -280 µA

IFB Feedback sourced current
3.3 V< VFB<4 V -2.5 -3 -3.5 µA

RFB(DYN) Dynamic resistance VFB> 2.5 V 12 25 kΩ

HFB VFB/ID 0.5 2 V/A

ZCD pin
VZCDCLh Upper clamp voltage IZCD = 1 mA 5 5.5 6 V

VZCDAth Arming voltage threshold Positive-going edge 0.75 0.8 0.85 V

VZCDTth Triggering voltage threshold Negative-going edge 0.55 0.6 0.65 V

IZCD Internal pull-up VFB <VFBlin -7.5 -10 -12.5 µA

Turn-on delay after ZCD

tDELAY 300 ns
trigger
VZCD<1 V 6.3 µs
Turn-on inhibit time after
tBLANK
MOSFET turn- off VZCD>1 V 2.5 µs

Current limitation
VFB = 4V
IZCD = -10 µA 0.95 1 1.05 A
TJ = 25 °C

VFB = 4 V
IDlim Drain current limitation IZCD = - 55 µA 0.68 0.8 0.92 A
TJ = 25 °C

VFB = 4 V
IZCD = - 105 µA 0.55 0.65 0.75 A
TJ = 25 °C

VIPER35L 3.5 ms
tSS Soft-start time
VIPER35H 4.2 ms
VIPER35L 7.5 15 ms
tSU Start-up time
VIPER35H 9.5 18 ms
tON_MIN Minimum turn-on time 220 400 480 ns

td Propagation delay (3) 100 ns

tLEB Leading edge blanking (3) 300 ns

Peak drain current during

ID_BM VFB = 0.6 V 120 170 220 mA
burst mode

DS10628 - Rev 5 page 7/38

 VIPER35
Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Overvoltage protection
VOVP Overvoltage threshold 3.8 4.2 4.6 V

tSTROBE Strobe time 2.2 µs

Oscillator section
VIPER35L 122 136 150 kHz
FOSClim Internal frequency limit
VIPER35H 200 225 250 kHz
VFB = 1 V
1/4
VZCD <VZCDTth kHz
FOSClim
t< tSU
FSTARTER Starter frequency
VFB = 1V
VZCD <VZCDTth 1/8 FOSClim kHz
t> tSU

Brown-out protection
VBRth Brown-out threshold Voltage falling 0.41 0.45 0.49 A

Voltage hysteresis above

VBRHyst 40 50 60 mV
VBRth

IBRHyst Current hysteresis 7 12 µA

VBRclamp Clamp voltage IBR = 250 µA 3 V

VDIS Brown-out disable voltage 50 150 mV

Thermal shutdown
Thermal shutdown
TSD (3) 150 160 °C
temperature
THYST Thermal shutdown hysteresis (3) 30 °C

1. Adjust VDD above VDDon start-up threshold before setting 14 V

2. Adjust VDD above VDDon start-up threshold before setting 10 V.
3. Specification assured by design, characterization and statistical correlation.

DS10628 - Rev 5 page 8/38

 VIPER35
Typical electrical characteristics

6 Typical electrical characteristics

Figure 4. VDDon vs TJ Figure 5. VDD(RESTART) vs TJ

Figure 6. IDlim vs TJ Figure 7. VDRAIN_START vs TJ

Figure 8. HFB vs TJ Figure 9. VDD(RESTART) vs TJ

DS10628 - Rev 5 page 9/38

 VIPER35
Typical electrical characteristics

Figure 10. VBRhyst vs TJ Figure 11. IBRhys vs TJ

Figure 12. IDD0 vs TJ Figure 13. IDD1 vs TJ

Figure 14. VZCD vs IZCD Figure 15. IDlim vs IZCD

DS10628 - Rev 5 page 10/38

 VIPER35
Typical electrical characteristics

Figure 16. RDS(on) vs TJ Figure 17. VBVDSS vs TJ

Figure 18. IDDch1 vs TJ Figure 19. IDDch2 vs TJ

Figure 20. FOSClim_L vs TJ Figure 21. FOSClim_H vs TJ

DS10628 - Rev 5 page 11/38

 VIPER35
Typical electrical characteristics

Figure 22. Thermal shutdown timing diagram

DS10628 - Rev 5 page 12/38

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Typical circuits

7 Typical circuits

Figure 23. Min-feature quasi-resonant flyback (isolated)

DS10628 - Rev 5 page 13/38

 VIPER35
Typical circuits

Figure 24. Full-feature quasi-resonant flyback (isolated)

DS10628 - Rev 5 page 14/38

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Efficiency performance for a typical flyback converter

8 Efficiency performance for a typical flyback converter

The efficiency of the converter has been measured in different load and line voltage conditions. In accordance
with the Energy Star average active mode testing efficiency method, the efficiency measurements have been
performed at 25%, 50% and 75% and 100% of the rated output power, both at 115 VAC and 230 VAC.

Table 6. Power supply efficiency, VOUT = 12 V, VIN = 115 VAC

% load IOUT[A] VOUT[V] POUT[W] PIN[W] Efficiency[%]

25% 0.31 12.1 3.78 4.53 83.47

50% 0.63 12.1 7.56 8.98 84.21
75% 0.94 12.1 11.34 13.4 84.65
100% 1.25 12.1 15.12 17.93 84.36
Average efficiency 84.17

Table 7. Power supply efficiency, VOUT = 12 V, VIN = 230 VAC

% load IOUT[A] VOUT[V] POUT[W] PIN[W] Efficiency[%]

25% 0.31 12.1 3.78 4.71 80.28

50% 0.63 12.1 7.56 9.22 82.02
75% 0.94 12.1 11.34 13.53 83.84
100% 1.25 12.1 15.12 17.77 85.12
Average efficiency 82.82

Figure 25. Power supply consumption at light output Figure 26. Power supply consumption at no output load,
loads,VOUT = 12 V VOUT = 12 V

DS10628 - Rev 5 page 15/38

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Operation description

9 Operation description

The device is a high-performance low voltage PWM controller chip with an 800 V, avalanche-rugged power
section.
The controller includes the PWM logic, ZCD logic for quasi-resonant operation, oscillator, start-up circuit with
soft-start, current limiting circuit with adjustable set-point, burst mode management, brown-out circuit, UVLO
circuit, auto-restart circuit and thermal protection circuit.
The current limit set-point can be reduced by ZCD pin. Burst mode operation guarantees high performance in
standby mode and meets energy-saving standards.
Allfault protections are built-in auto-restart mode with very low repetition rate to prevent the IC overheating.

9.1 Power section and gate driver

The power section is given by an avalanche-rugged N-channel MOSFET, which guarantees safe operation within
the specified energy rating as well as high dv/dt capability. The power MOSFET has a BVDSS of 800 V min. and a
typical RDS (on) of 4.5 Ω at 25 °C. The integrated senseFET structure allows a virtual loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn- off to minimize
common-mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low to ensure that the
power section cannot be turned on accidentally.

9.2 High voltage start-up generator

The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor
voltage is higher than VDRAIN_START threshold, 80 V DC typically.
When HV current generator is on, IDDch1 current (3 mA typical value) is delivered to the capacitor on VDD pin.
During auto-restart mode after a fault event, the current is reduced to IDDch2 (0.6 mA, typ.) in order to have a slow
duty cycle during the restart phase.

9.3 Power-up and soft-start

When the input voltage reaches the device start threshold, VDRAIN_START, the VDD voltage begins growing due to
IDDch1 current (see Section 5 : Feedback pin) coming from the internal high voltage start-up circuit. If the VDD
voltage reaches VDDon threshold, the power MOSFET starts switching and the HV current generator turns off.
The IC is powered by the energy stored in the capacitor on VDD pin, CVDD, until the selfsupply circuit (typically an
auxiliary winding of the transformer and a steering diode) develops a voltage so high to sustain the operation.
CVDD capacitor must be correctly sized to avoid fast discharge and keep the required voltage higher than VDDoff
threshold. In fact, an insufficient capacitance value could terminate the switching operation before the controller
receives any energy from the auxiliary winding.
The following formula can be used to calculate CVDD capacitor:
I × t
CVDD = VDDcℎ − V SSaux (1)
DDon DDoff
tSSaux is the time needed for the steady-state of the auxiliary voltage. It represents an estimate of the user's
application according to the output stage configurations (transformer, output capacitances, etc.).
During the normal operation, the power MOSFET switches on after the transformer demagnetization, detected
through the voltage VZCD sensed on ZCD pin.
At power-up, the initial output voltage is zero and the voltage VZCD is not so high to correctly arm the internal
ZCD circuit. In this case, the power MOSFET turns on with the fixed frequency FSTARTER, reported in Section 5 :
Feedback pin. After the start-up, as soon as the voltage on ZCD logic is enabled to work, the turn-on of the power
MOSFET is driven by this circuit and it is not related to the internal oscillator (except for the frequency foldback
function) any longer.
The start-up phase is managed by a dedicated internal logic and is activated by every attempt of the start-up
converter or after a fault.

DS10628 - Rev 5 page 16/38

 VIPER35
Power-up and soft-start

An internal clock counter defines the start-up time, tSU, since during quasi-resonant operation, the switching
frequency and the duration of the start-up time depend on the load, tSU range is indicated in Section 5 :
Feedback pin. At the beginning of the start-up time, the drain current limitation progressively rises to the
maximum value. In this way a soft-start occurs and the stress on the secondary diode is considerably reduced. It
also prevents transformer saturation.
The soft-start time lasts 3.5 ms (VIPER35L) or 4.2 ms (VIPER35H), (see tSS in Section 5 : Feedback pin).
At the start-up, until the output voltage reaches its regulated value, the feedback loop is open and an improper
activation of the overload protection could occur. In order to avoid this, OLP logic is disabled and it is active at the
end of the start-up phase, t > tSU. Figure 29 and Figure 30 show two possible start-up cases.
As soon as the output voltage reaches the regulated value, the regulation loop takes over and the drain current is
regulated below its limit, IDlim, by the feedback voltage, which is at a value lower than the VFBlin threshold.

Figure 27. IDD current during start-up and burst mode

DS10628 - Rev 5 page 17/38

 VIPER35
Power-up and soft-start

Figure 28. Timing diagram: normal power-up and power-down sequence

Figure 29. Timing diagram: start-up phase and soft-start (case 1)

DS10628 - Rev 5 page 18/38

 VIPER35
Power-down description

Figure 30. Timing diagram: start-up phase and soft-start (case 2)

9.4 Power-down description

At converter power-down, the system loses its ability to regulate as soon as the decreasing input voltage is so low
to reach the peak current limitation. VDD voltage drops and when it falls below VDDoff threshold (see Section 5 :
Feedback pin) the power MOSFET switches off, the energy is interrupted, VDD voltage decreases, the start-up
sequence is inhibited and the power-down is completed. This feature prevents any restart attempt and ensures a
monotonic output voltage decay during the system power-down.

9.5 Auto-restart description

Every time a protection is tripped, the IC automatically restarts after a duration depending on the discharge
and recharge of CVDD capacitor. As shown in Figure 31, after a fault, the IC stops and VDD voltage decreases
because of IC consumption. As soon as VDD voltage falls below VDD(RESTART) threshold and if the DC input
voltage is higher than VDRAIN_START threshold, the internal HV current source turns on and it starts to charge
CVDD capacitor with the current IDDch2 (0.6 mA, typ.). As soon as VDD voltage reaches VDD(ON) threshold, the IC
restarts.

Figure 31. Timing diagram: behavior after short-circuit

DS10628 - Rev 5 page 19/38

 VIPER35
Quasi-resonant operation (QR)

9.6 Quasi-resonant operation (QR)

The control core of the VIPER35 is a current mode PWM controller with a zero-current detect circuit designed
for quasi-resonant (QR) operation, a technique whose benefits are: minimum turn-on losses, low EMI emission
and safe behavior in case of short-circuit. At heavy load the converter operates in quasi-resonant mode; operation
synchronizes MOSFET turn-on to the transformer demagnetization by detecting the resulting negative going
edge of the voltage across any winding of the transformer. The system works close to the boundary between
discontinuous (DCM) and continuous conduction (CCM) of the transformer and as a result, the switching
frequency is different according to different line/load conditions. See the hyperbolic-like portion reported in
Figure 32.
At medium/ light load, depending on the converter input voltage as well, the device enters valley-skipping
mode. An internal oscillator, synchronized to MOSFET turn-on, defines the maximum operating frequency of
the converter, FOSClim.
The VIPER35 is available as type 'L' or type 'H', depending on FOSClim value, see Section 5 : Feedback pin.
During the normal operation the converter works with a frequency below FOSClim, so the 'L' type is suitable for
applications where the priority is on the EMI filter minimization. The 'H' type is suitable when an extended QR
operation range or the transformer size reduction are priorities.
As the load is reduced, and the switching frequency tends to exceed the oscillator’s one, MOSFET turn-on
doesn’t occur on the first valley but on the second one, the third one and so on. In this way a “frequency clamp”
effect is achieved, piecewise linear portion is showed in Figure 32.
When the load is extremely light or disconnected, the converter enters burst mode operation. By decreasing
the load, the frequency is reduced even few hundred hertz, so to comply with energy saving regulations or
recommendations. As the peak current is low, no audible noise occurs.
The above mentioned operation is based on ZCD pin. This pin is the input of the integrated ZCD circuit which
allows the power section turn-on at the end of the transformer demagnetization. The input signal for the ZCD is
obtained as a partition of the auxiliary voltage used to supply the device, see Figure 33.
When the triggering circuit senses a negative-going edge below VZCDTth threshold (see Section 5 : Feedback
pin), after an internal delay that helps to achieve minimum drain-source voltage switch-on (“valley switching”), the
power MOSFET turns on. However, to enable power MOSFET turn-on, the triggering circuit has to be previously
armed by a positive-going edge exceeding VZCDAth threshold (see Section 5 : Feedback pin) on the same ZCD
pin.
After the MOSFET turn-off, the blanking time, tBLANK, is generated to avoid an erroneous arming and triggering
due to the noise, generated by the leakage inductance resonance of the transformer which rings and couples with
ZCD pin.

Figure 32. Switching frequency vs power

DS10628 - Rev 5 page 20/38

 VIPER35
Frequency foldback function and valley-skipping mode

Figure 33. Zero-current detection circuit

9.7 Frequency foldback function and valley-skipping mode

The switching frequency, in quasi-resonant mode, is not fixed and it depends on both the load and the converter
input voltage. The switching frequency increases when the load decreases, or when the mains voltage increases,
and vice versa. To avoid that, the VIPER35 taps the maximum switching frequency of the application thanks to its
control logic.
The frequency limit is given by an internal oscillator switching at 136 kHz for the VIPER35L or at 225 kHz for
the VIPER35H, (see parameter FOSCliminSection 5 : Feedback pin). This oscillator is synchronized with the
power MOSFET turn-on. When the power MOSFET is off, if the first negative-going edge voltage of the ZCD pin,
resulting from transformer demagnetization, appears after at least one oscillator cycle has been completed, the
MOSFET turns on and the oscillator is synchronized again.
Otherwise,if the first negative-going edge voltage appears before completing one oscillator cycle, the signal is
ignored. Due to the ringing of the drain voltage, the ZCD pin experiences another positive-going edge voltage that
arms the circuit and a negative-going edge voltage. Again, if this appears before the oscillator cycle is completed,
it is ignored, otherwise the MOSFET turns on and the oscillator is synchronized. In this manner, one or more drain
ringing cycles are skipped (Figure 34 shows the so called “valley-skipping mode”) and the switching frequency
doesn’t exceed FOSClim limit.

Figure 34. Drain ringing cycle skipping as the load progressively reduces

When the system operates in valley-skipping mode, uneven switching cycles may be observed under some
line/load conditions, due to the fact that the off-time of the power MOSFET changes its discrete steps one ringing
cycle, while the off-time needed for cycle by-cycle energy balance could fall in between. Therefore one or even
longer switching cycles are compensated by one or more shorter cycles and vice versa. This mechanism is
natural and any effect on the converter performance and on its output voltage appears.
This operation does not consider the blanking time tBLANK after power MOSFET turn-off. Actually tBLANK is not
taken into account as long as the following condition is met:

DS10628 - Rev 5 page 21/38

 VIPER35
Blanking time

T
D ≤ 1 − TBLANK = 1 − TBLANK ∙ FOSClim (2)
OSClim
where D is the MOSFET duty cycle. If this condition is not met, the time during which MOSFET turn-on is inhibited
is extended beyond tOSClim by a fraction of tBLANK. As a consequence, the maximum switching frequency is a
little bit lower than the internal limit set by the oscillator and valley-skipping mode takes place slightly earlier than
expected.

9.8 Blanking time

The blanking time, tBLANK, can have two different values: the lower one is 2.5 seconds (typical value) and the
higher one is 6.3 seconds (typical value). The value is linked to the voltage VZCD, sampled during the time
tSTROBE. The time tBLANK has the lower value if VZCD>1 V or it has the higher value if VZCD<1 V, refer to
Section 5 : Feedback pin and Figure 35.
The higher value of the blanking time is active during the start-up phase or in case of output short-circuit,
when the output voltage of the converter is quite lower than the regulated value. In this condition, during the
demagnetization of the transformer, VZCD can be very close to the arming and triggering thresholds (VZCDAth and
VZCDTth) and ZCD circuit can be erroneously trigged, leading the system to work with higher frequency and in
continuous mode. This false trigger is inhibited by the selection of tBLANK higher value when VZCD is lower than 1
V.
During the normal operation, in steady-state condition, the voltage VZCD during the demagnetization is higher than
1 V and the selected tBLANK value is the lower one.
Figure 35 shows the typical waveforms during the power-up and the linked tBLANK selection.

Figure 35. Timing diagram: doubleblanking time

9.9 Starter
If the amplitude of the voltage on ZCD pin at the end of one oscillator cycle is smaller than VZCDAth arming
threshold, (in this case MOSFET turn-on could not be triggered), the system stops.
This is what normally happens during the converter power-up or under overload/short-circuit conditions.
During the converter start-up phase, the voltage on ZCD pin is not so high to arm the triggering circuit. Thus, the
converter operates at a fixed frequency, FSTARTER, (see Section 5 : Feedback pin). As the voltage developed
across the auxiliary winding arms the ZCD circuit,
MOSFET turn-on is locked to transformer demagnetization, hence quasi-resonant operation is set.

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 VIPER35
Current limit set-point and feed-forward option

9.10 Current limit set-point and feed-forward option

The VIPER35 is a current mode converter and the drain current is limited cycle-by-cycle according to FB pin
voltage value, which is related to the feedback loop response and the load. When the drain current, sensed by the
integrated senseFET, reaches the current limitation, after the internal propagation delay, the MOSFET switches
off. The current limitation cannot exceed a certain value, IDlim, which can vary according to the current sunk by
ZCD pin during MOSFET on-time.
Usually a resistor, RLIM, connected from ZCD pin to ground fixes this sunk current and then the peak drain current
set-point: the lower the resistor, the lower IDlim.
For a quasi-resonant flyback converter, the power capability strongly depends on the input voltage. In wide
range applications, at maximum line, the power capability can be more than twice the value at minimum line,
as shown by the upper curve in the diagram, see Figure 36. To reduce this dependence, the IDlim has to be
reduced according to the increment of the input voltage, this is the line feed-forward. It's given by a resistor, RFF,
connected between the ZCD pin and the auxiliary winding, see Figure 37. Since the voltage across the auxiliary
winding during MOSFET on-time is proportional to the input voltage through the auxiliary-to-primary turn ratio
NAUX/NP, a current proportional to the input voltage is sunk by the ZCD pin, thus the overcurrent set-point lowers.

Figure 36. Typical power capability vs input voltage in quasi-resonant converter

In order to select the RFF resistance value (see Figure 37), when the proper overcurrent set- points are known at
minimum and at the maximum converter input voltage, in Figure 15 the needed current to sink during MOSFET
on-time is visible. With the following approximated formula, the value of RFF resistor can be calculated:
Vin_max − Vin_min
RFF = (3)
naux ∙ IZCD1 − IZCD2
where:
• Vin_Max and Vin_min are the maximum and minimum converter rectified input voltage.
• NAUX is the primary-to-auxiliary winding turn ratio.
• IZCD1, and IZCD2 are the currents needed to sink from the ZCD pin, in order to obtain the selected
overcurrent set-points, at maximum and minimum flyback input voltage, see Figure 15.
Given RFF value, RLIM value can be calculated by the following formula:

DS10628 - Rev 5 page 23/38

 VIPER35
Overvoltage protection (OVP)

VZCD1 VZCD2
RLIM = Max , (4)
Vin_min Vin_max
naux + VZCD1 naux + VZCD2
IZCD1 − RFF I ZCD2 − RFF
where:
VZCD1 and VZCD2 are ZCD pin voltages when the sunk current is IZCD1 and IZCD2 respectively, see Figure 14.

Figure 37. ZCD pin typical external configuration

9.11 Overvoltage protection (OVP)

The device has integrated the logic to monitor the output voltage using as input signal, the voltage VZCD during
the off-time of the power MOSFET. This is the time when the voltage from the auxiliary winding tracks the output
voltage, through the turn ratio NAUX/NSEC.
ZCD pin has to be connected to the auxiliary winding through the diode DOVP and the resistors ROVP and RLIM as
shown in Figure 37. When, during the off-time, the voltage VZCD exceeds, four consecutive times, the reference
voltage VOVP (reported in Table 6), the overvoltage protection stops the power MOSFET and the converter enters
auto-restart mode.
In order to bypass the noise after the turn-off of the power MOSFET, VZCD voltage is sampled inside a short
window after the time tSTROBE, see Section 5 ,Feedback pin, and Figure 38. The sampled signal, if higher than
VOVP, triggers the internal OVP digital signal and increments the internal counter. The same counter is reset every
time the signal OVP is not triggered in one oscillator cycle.
Referring to Figure 37, the resistor divider ratio kOVPis given by below equations:
VOVP
kOVP = N (5)
aux ∙ V
Nsec OUTOVP + VDSEC − VDAUX

RLIM
kOVP = R (6)
LIM + ROVP

where:
• VOVP is theOVP threshold (see Section 5 ,Feedback pin, )
• VOUTOVP is the converter output voltage value to activate the OVP (set by design)
• NAUX is the auxiliary winding turn
• NSEC is the secondary winding turn
• VDSEC is the secondary diode forward voltage
• VDAUX is the auxiliary diode forward voltage

DS10628 - Rev 5 page 24/38

 VIPER35
ZCD pin summary

• ROVP and RLIM make the output voltage divider

Byfixing RLIM, according to the desired IDlim, ROVP can be calculated as follows:
1 − kOVP
ROVP = RLIM ∙ (7)
kOVP

The resistor values let the current sourced and sunk by the ZCD pin be within the rated capability of the internal
clamp.

Figure 38. Timing diagram:OVP

9.12 ZCD pin summary

With reference to Figure 37, the circuitry connected to the ZCD pin enables the following functions:
1. Current limit set-point (IDLIM)
2. Line feed-forward compensation (FF)
3. Output overvoltage protection (OVP)
4. Zero-current detection for QR operation
Chosen RLIM, RFF and ROVP as described in the previous sections, these functions are automatically defined.
Section 5 ,Feedback pin, refers to Figure 37 and lists the external resistance combinations needed to activate
one or more functions associated to ZCD pin.

Table 8. ZCD pin configurations

IDlim OVP FF RLim ROVP RFF DOVP

■ □ □ Eq. (7) with VOUTOVP ˃2 VOUT ˗ Yes

□ ■ □ 22 kΩ Eq. (7) ˗ Yes

□ □ ■ 22 kΩ Eq. (7) with VOUTOVP˃2VOUT Eq. (3) Yes

■ ■ □ with RFF= ∞ Eq. (7) ˗ Yes

□ ■ ■ 22 kΩ Eq. (7) Eq. (3) Yes

■ □ ■ Eq. (4) Eq. (7) with VOUTOVP ˃2VOUT Eq. (3) Yes

■ ■ ■ Eq. (4) Eq. (7) Eq. (3) Yes

9.13 Feedback and overload protection (OLP)

The feedback pin (FB) controls the PWM operation, enters the burst mode and manages the delayed overload
protection.

DS10628 - Rev 5 page 25/38

 VIPER35
Feedback and overload protection (OLP)

VFBbm and VFBlin thresholds (Section 5 ,Feedback pin, ) are respectively low and high limit of PWM operations,
where the drain current is sensed by the integrated resistor, RSENSE, and applied to the comparator PWM. The
PWM logic turns off the power MOSFET as soon as the sensed voltage is equal to the voltage applied to FB pin
and through the integrated resistor network (see Figure 1 and Figure 23).
IC block diagram (Figure 1) shows in parallel with the PWM comparator how OCP comparator limits the drain
current to IDlim value, as per Section 5 ,Feedback pin, .
In case of higher load, the voltage VFB increases, when it reaches VFBlin threshold, the drain current is limited to
IDlim by OCP comparator and the internal current starts the charge of CFB capacitor. As soon as the voltage VFB
reaches the threshold VFBolp, see Figure 41, the protection turns off the IC. The auto-restart mode is active using
the low value of the current IDDch, see Section 5 ,Feedback pin, .
The time, from the high load detection, VFB = VFBlin, to the overload turn-off, VFB = VFBolp, depends on the value
of CFB capacitor and on the internal charge current, IFB. OLP delay time can be calculated as follows:
VFBolp − VFBlin
TOLP_delay = CFB ∙ (8)
IFB

The current, IFB, is 3 A as minimum value. Components, connected to FB pin, belong to the compensation loop,
so they have to be selected taking into account the proper delay and loop stability. Figure 39 and Figure 40 show
two different feedback networks.
In Figure 39 CFB capacitor, connected to FB pin, is used as part of the circuit to compensate the feedback loop
but it is also an element to delay OLP shutdown owing to the time needed to charge the capacitor (see Equation
8). After the start-up time, tSU, during which the feedback voltage is fixed at VFBlin, the output capacitor could not
be at its nominal value and the controller detects this situation as an overload condition. In this case, OLP delay
avoids the wrong device shutdown during the start-up.
Owing to the above considerations, OLP delay time must last to bypass the initial output voltage transient and
check the overload condition only when the output voltage is in steady-state. The output transient time depends
on the value of the output capacitor and on the load.
When CFB capacitor value is too low and cannot ensure the OLP delay, an alternative compensation network can
be used as showed in Figure 40. Two poles (fPFB, fPFB1) and one zero (fZFB) are introduced by CFB and CFB1
capacitors and RFB1 resistor.
The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole compensates zero
frequency due to ESR (equivalent series resistor) of the output capacitance of the flyback converter.
By taking into account the scheme in Figure 40, these poles and zero frequency are reported as follows:

f ZFB = 2 ∙ π ∙ C1 ∙ R (9)
FB FB
RFB DYN − RFB1
f PFB = (10)
2 ∙ π ∙ CFB ∙ RFB DYN ∙ RFB1

1
f PFB = (11)
2 ∙ π ∙ CFB1 ∙ RFB1 + RFB DYN

RFB(DYN) is the dynamic resistance seen by FB pin and reported in Section 5 ,Feedback pin, . CFB1 capacitor
fixes the OLP delay and usually it is much higher than CFB. Eq. (8) calculates the OLP delay time but CFB1 has
to be considered. Using the alternative compensation network, the designer can satisfy the loop stability and OLP
delay time.

DS10628 - Rev 5 page 26/38

 VIPER35
Feedback and overload protection (OLP)

Figure 39. FB pin configuration (minimal BOM)

Figure 40. FB pin configuration

DS10628 - Rev 5 page 27/38

 VIPER35
Burst mode operation at no-load or very light load

Figure 41. Timing diagram: overload protection

9.14 Burst mode operation at no-load or very light load

When the load decreases, the feedback loop lowers the feedback pin voltage. If it falls down the burst mode
threshold, VFBBm, the power MOSFET doesn’t switch on. After the MOSFET stops, the feedback pin voltage
increases and by exceeding the level, VFBbm + VFBbmhys, the power MOSFET starts switching again. The burst
mode thresholds are reported in Section 5 ,Feedback pin, and Figure 42 shows this behavior. System alternates
period of time where power MOSFET switches to period of time where power MOSFET doesn’t switch; this device
working mode is the burst mode. The power delivered to output during switching periods exceeds the load power
demands; the excess of power is balanced by the period where no power is processed. The advantage of burst
mode operation is an average switching frequency much lower than the normal operation working frequency, up
to some hundred of hertz, minimizing all frequency-related losses. During the burst mode the drain current peak is
clamped to the level, ID_BM, (see Section 5 ,Feedback pin, ).

Figure 42. Burstmode timing: light load management

DS10628 - Rev 5 page 28/38

 VIPER35
Brown-out

9.15 Brown-out
Brown-out protection is a not-latched shutdown function active when a condition of mains undervoltage is
detected. The brown-out comparator is internally referenced to VBRth threshold (see Section 6 ) and disables
the PWM if the voltage applied to BR pin is below this internal reference. Under this condition the power MOSFET
turns off.
Until the brown-out condition is present, the VDD voltage continuously oscillates between the VDDon and the UVLO
thresholds, as shown in the timing diagram of Figure 43. A voltage hysteresis improves the noise immunity.
The switching operation restarts as the voltage on the pin is above the reference plus the voltage hysteresis. The
brown-out comparator is provided with a current hysteresis, IBRhyst.
The designer has to set the rectified input voltage above which the power MOSFET starts switching after
brown-out event, VINon, and below which the power MOSFET switches off, VINoff. Thanks to the IBRhyst, see
Section 5 ,Feedback pin, , these two thresholds can be set separately.
When VINon and VINoff levels are fixed, with reference to Figure 43, the following relationships can be established
to calculate RH and RL resistors:
VBRhyst VINon − VINoff − VBRhyst VBRth
RL = − I + ∙I (12)
BRhyst VINon − VBRth BRhyst

VINon − VINoff − VBRhyst RL

RH = ∙ (13)
IBRhyst VBRhyst
RL + I
BRhyst

Figure 43. Brown-out: external setting and timing diagram

VINon must be less than the peak voltage at minimum mains and VINoff voltage has to be less than the minimum
voltage on the input bulk capacitor at minimum mains and maximum load.
BR pin is a high impedance input connected to high value resistors, thus it is ready to pick up noise, which might
alter the VINoff threshold when the converter operates or causes the undesired switch-off of the device during ESD
tests.
The pin ca be bypassed to ground with a small film capacitor (1-10 nF) to prevent any malfunctioning.
If the brown-out function is not used, BR pin has to be connected to GND, ensuring that the voltage is lower than
the minimum VDIS threshold (50 mV, see Section 5 ,Feedback pin, ). In order to enable the brown-out function,
BR pin voltage has to be higher than the maximum VDIS threshold (150 mV, see Section 5 ,Feedback pin, ).

DS10628 - Rev 5 page 29/38

 VIPER35
Package information

10 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

DS10628 - Rev 5 page 30/38

 VIPER35
SO16N package information

10.1 SO16N package information

Figure 44. SO16N package outline

DS10628 - Rev 5 page 31/38

 VIPER35
SO16N package information

Table 9. SO16N mechanical data

Milimeters
Symbol
Min. Typ. Max.

A 1.75
A1 0.10 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.80 9.90 10.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27
h 0.25 0.50
L 0.40 1.27
k 0 8°
ccc 0.10

DS10628 - Rev 5 page 32/38

 VIPER35
Ordering information

11 Ordering information

Table 10. Order codes

Order code FOsclim RDS(on) Peak drain current Package

SO16N
VIPER35LD
(tube)
136 kHz
SO16N
VIPE35LDTR
(tape and reel)
4.5 Ω 1A
SO16N
VIPER35HD
(tube)
225 kHz
SO16N
VIPER35HDTR
(tape and reel)

DS10628 - Rev 5 page 33/38

 VIPER35

Revision history
Table 11. Document revision history

Date Version Changes

23-Feb-2015 1 Initial release.

Updated title in cover page.
19-Mar-2015 2
Minor text changes.
Document status promoted frompreliminary data to production data.
08-Jul-2015 3 Updated Section 4: Electrical ratings.
Minor text changes.
Added SDIP10 package
Updated Figure 1 title in cover page from “Internal schematic diagram” to
“Basic application schematic”.
10-Feb-2016 4 Updated Section 3:Pin settings, Table 2: Pin description, Table 4: Thermal
data and Section 10 Ordering information. Added Section 9.2 :SDIP10
package information
Minor text changes.
Changed picture of package Cover image, changed Section 3 configuration,
12-Dec-2022 5
and some values in Table 4

DS10628 - Rev 5 page 34/38

 VIPER35
Contents

Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Typical output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4 Absolute maximum ratings and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Typical circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
8 Efficiency performance for a typical flyback converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
9 Operation description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
9.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.2 High voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.3 Power-up and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.4 Power-down description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.5 Auto-restart description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.6 Quasi-resonant operation (QR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.7 Frequency foldback function and valley-skipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.8 Blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.9 Starter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.10 Current limit set-point and feed-forward option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.11 Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.12 ZCD pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.13 Feedback and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.14 Burst mode operation at no-load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.15 Brown-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
10.1 SO16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

DS10628 - Rev 5 page 35/38

 VIPER35
List of tables

List of tables
Table 1. Typical output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. Power supply efficiency, VOUT = 12 V, VIN = 115 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Power supply efficiency, VOUT = 12 V, VIN = 230 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. ZCD pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. SO16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DS10628 - Rev 5 page 36/38

 VIPER35
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. VDDon vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. VDD(RESTART) vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. IDlim vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. VDRAIN_START vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. HFB vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. VDD(RESTART) vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. VBRhyst vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11. IBRhys vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12. IDD0 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 13. IDD1 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 14. VZCD vs IZCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 15. IDlim vs IZCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 16. RDS(on) vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 17. VBVDSS vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 18. IDDch1 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 19. IDDch2 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 20. FOSClim_L vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 21. FOSClim_H vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 22. Thermal shutdown timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 23. Min-feature quasi-resonant flyback (isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 24. Full-feature quasi-resonant flyback (isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 25. Power supply consumption at light output loads,VOUT = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Power supply consumption at no output load, VOUT = 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 27. IDD current during start-up and burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28. Timing diagram: normal power-up and power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 29. Timing diagram: start-up phase and soft-start (case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 30. Timing diagram: start-up phase and soft-start (case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 31. Timing diagram: behavior after short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 32. Switching frequency vs power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 33. Zero-current detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 34. Drain ringing cycle skipping as the load progressively reduces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 35. Timing diagram: doubleblanking time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 36. Typical power capability vs input voltage in quasi-resonant converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 37. ZCD pin typical external configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 38. Timing diagram:OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 39. FB pin configuration (minimal BOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 40. FB pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 41. Timing diagram: overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 42. Burstmode timing: light load management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 43. Brown-out: external setting and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 44. SO16N package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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 VIPER35

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DS10628 - Rev 5 page 38/38