FN 6453
FN 6453
FN 6453
ISL6236A
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6236A
Pinout
ISL6236A
(32 LD 5x5 QFN)
TOP VIEW
PHASE2
UGATE2
REFIN2
POK2
OUT2
ILIM2
SKIP
EN2
32 31 30 29 28 27 26 25
REF 1 24 BOOT2
TON 2 23 LGATE2
VCC 3 22 PGND
EN LDO 4 21 GND
VREF3 5 20 SECFB
VIN 6 19 PVCC
LDO 7 18 LGATE1
LDOREFIN 8 17 BOOT1
9 10 11 12 13 14 15 16
OUT1
ILIM1
BYP
FB1
POK1
EN1
UGATE1
PHASE1
2 FN6453.3
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ISL6236A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Limits established by characterization and are not production tested.
4. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
Electrical Specifications No load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
VEN_LDO = 5V, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C.
MIN MAX
PARAMETER CONDITIONS (Note 4) TYP (Note 4) UNITS
3.3V Output Voltage in Fixed Mode VIN = 4.5V to 25V, REFIN2 > (VCC - 1V), SKIP = 5V 3.285 3.330 3.375 V
1.05V Output Voltage in Fixed Mode VIN = 4.5V to 25V, 3.0 < REFIN2 < (VCC - 1.1V), 1.038 1.05 1.062 V
SKIP = 5V
1.5V Output Voltage in Fixed Mode VIN = 4.5V to 25V, FB1 = VCC, SKIP = 5V 1.482 1.500 1.518 V
5V Output Voltage in Fixed Mode VIN = 5.5V to 25V, FB1 = GND, SKIP = 5V 4.975 5.050 5.125 V
FB1 in Output Adjustable Mode VIN = 4.5V to 25V 0.693 0.700 0.707 V
SMPS2 Output Voltage Accuracy REFIN2 = 0.7V to 2.5V, SKIP = VCC -1.0 1.0 %
(Referred for REFIN2)
Line Regulation Either SMPS, 6V < VIN < 24V 0.005 %/V
Current-Limit Current Source Temperature = +25°C 4.75 5 5.25 µA
3 FN6453.3
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ISL6236A
Electrical Specifications No load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
VEN_LDO = 5V, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued)
MIN MAX
PARAMETER CONDITIONS (Note 4) TYP (Note 4) UNITS
Current-Limit Threshold (Positive, Default) ILIM = VCC, GND - PHASE 93 100 107 mV
(No temperature compensation)
On-Time Pulse Width VtON = GND (400kHz/500kHz) VOUT1 = 5.00V 0.895 1.052 1.209 µs
VOUT2 = 3.33V 85 %
VOUT2 = 3.33V 91 %
BYP = GND, 4.5V < VIN < 25V, LDOREFIN > (VCC - 1V), 3.250 3.300 3.350 V
0 < ILDO < 100mA
BYP = GND, 4.5V < VIN < 25V, LDOREFIN = 2V, 3.94 4.00 4.06 V
0 < ILDO < 100mA
LDO Output Accuracy in Adjustable Mode VIN = 4.5V to 25V, VLDOREFIN = 0.35V to 0.5V ±2.5 %
4 FN6453.3
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ISL6236A
Electrical Specifications No load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
VEN_LDO = 5V, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued)
MIN MAX
PARAMETER CONDITIONS (Note 4) TYP (Note 4) UNITS
LDO Output Current BYP = GND, VIN = 4.5V to 25V (Note 3) 100 mA
LDO Output Current During Switchover to 5V BYP = 5V, VIN = 5.5V to 25V, LDOREFIN < 0.3V 200 mA
LDO Output Current During Switchover BYP = 3.3V, VIN = 4.5V to 25V, LDOREFIN > (VCC - 1V) 100 mA
to 3.3V
LDO 5V Bootstrap Switch Threshold to BYP Rising edge at BYP regulation point 4.53 4.68 4.83 V
LDOREFIN = GND
LDO 3.3V Bootstrap Switch Threshold to Rising edge at BYP regulation point 3.0 3.1 3.2 V
BYP LDOREFIN = VCC
LDO 5V Bootstrap Switch Equivalent LDO to BYP, BYP = 5V, LDOREFIN > (VCC - 1V) 0.7 1.5 Ω
Resistance (Note 3)
LDO 3.3V Bootstrap Switch Equivalent LDO to BYP, BYP = 3.3V, LDOREFIN < 0.3V (Note 3) 1.5 3.0 Ω
Resistance
VREF3 Output Voltage No external load, VCC > 4.5V 3.235 3.300 3.365 V
VIN Standby Supply Current VIN = 5.5V to 25V, both SMPSs off, EN LDO = VCC 180 250 µA
VIN Shutdown Supply Current VIN = 4.5V to 25V, EN1 = EN2 = EN LDO = 0V 20 30 µA
Quiescent Power Consumption Both SMPSs on, FB1 = SKIP = GND, REFIN2 = VCC, 5 7 mW
VOUT1 = BYP = 5.3V, VOUT2 = 3.5V
FAULT DETECTION
Overvoltage Trip Threshold FB1 with respect to nominal regulation point +8 +11 +14 %
Overvoltage Fault Propagation Delay FB1 or REFIN2 delay with 50mV overdrive 10 µs
POK_ Threshold FB1 or REFIN2 with respect to nominal output, falling -12 -9 -6 %
edge, typical hysteresis = 1%
Output Undervoltage Shutdown Threshold FB1 or REFIN2 with respect to nominal output voltage 65 70 75 %
5 FN6453.3
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ISL6236A
Electrical Specifications No load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
VEN_LDO = 5V, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued)
MIN MAX
PARAMETER CONDITIONS (Note 4) TYP (Note 4) UNITS
INPUTS AND OUTPUTS
EN1, EN2 Input Voltage Clear fault level/SMPS off level 0.8 V
Delay start level 1.7 2.3 V
IBOOT LEAKAGE Leakage Current VBOOT = 30V, PHASE = 25V, PVCC = 5V 500 nA
MOSFET DRIVERS
LGATE Gate-Driver Source Current LGATE1 (source), LGATE2 (source), forced to 2V 1.7 A
LGATE Gate-Driver Sink Current LGATE1 (sink), LGATE2 (sink), forced to 2V 3.3 A
6 FN6453.3
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ISL6236A
Pin Descriptions
PIN NAME FUNCTION
1 REF 2V Reference Output. Bypass to GND with a 0.1µF (min) capacitor. REF can source up to 50µA for external loads.
Loading REF degrades FB and output accuracy according to the REF load-regulation error.
2 TON Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to REF (or leave OPEN) for
400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies,
respectively).
3 VCC Analog Supply Voltage Input for PWM Core. Bypass to GND with a 1µF ceramic capacitor.
4 EN LDO LDO Enable Input. The LDO is enabled if EN LDO is within logic high level and disabled if EN LDO is less than the logic
low level.
5 VREF3 3.3V Reference Output. VREF3 can source up to 5mA for external loads. Bypass to GND with a 0.01µF capacitor if
loaded. Leave open if there is no load.
6 VIN Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power the
linear regulators. The linear regulators are powered by SMPS1 if OUT1 is set greater than 4.78V and BYP is tied to
OUT1. Connect VIN to the battery input and bypass with a 1µF capacitor.
7 LDO Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulates at 5V If LDOREFIN is
connected to GND. When the LDO is set at 5V and BYP is within 5V switchover threshold, the internal regulator shuts
down and the LDO output pin connects to BYP through a 0.7Ω switch. The LDO regulates at 3.3V if LDOREFIN is
connected to VCC. When the LDO is set at 3.3V and BYP is within the 3.3V switchover threshold, the internal regulator
shuts down and the LDO output pin connects to BYP through a 1.5Ω switch. Bypass LDO output with a minimum of
4.7µF ceramic.
8 LDOREFIN LDO Reference Input. Connect LDOREFIN to GND for fixed 5V operation. Connect LDOREFIN to VCC for fixed 3.3V
operation. LDOREFIN can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the
voltage of LDOREFIN. There is no switchover in adjustable mode.
9 BYP BYP is the switchover source voltage for the LDO when LDOREFIN is connected to GND or VCC. Connect BYP to 5V
if LDOREFIN is tied to GND. Connect BYP to 3.3V if LDOREFIN is tied to VCC.
10 OUT1 SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. OUT1 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode.
11 FB1 SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation.
Connect FB1 to a resistive voltage-divider from OUT1 to GND to adjust the output from 0.7V to 5.5V.
12 ILIM1 SMPS1 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM1. Connect ILIM1 to REF for a fixed 200mV
threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V.
13 POK1 SMPS1 Power-Good Open-Drain Output. POK1 is low when the SMPS1 output voltage is more than 10% below the
normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK1 is low in shutdown.
14 EN1 SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than
the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start). Drive
EN1 below 0.8V to clear fault level and reset the fault latches.
15 UGATE1 High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1.
16 PHASE1 Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver.
PHASE1 is the current-sense input for the SMPS1.
17 BOOT1 Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the “Typical Application
Circuits” on page 19 (Figures 66, 67 and 68). See “MOSFET Gate Drivers (UGATE, LGATE)” on page 29.
18 LGATE1 SMPS1 Synchronous-Rectifier Gate-Drive Output. LGATE1 swings between GND and PVCC.
19 PVCC PVCC is the supply voltage for the low-side MOSFET driver LGATE. Connect a 5V power source to the PVCC pin and
bypass to PGND with a 1µF MLCC ceramic capacitor. Refer to Figure 70 - A switch connects PVCC to VCC with 10Ω
when in normal operation and is disconnected when in shutdown mode. An external 10Ω resistor from PVCC to VCC
is prohibited as it will create a leakage path from VIN to GND in shutdown mode.
20 SECFB The SECFB is used to monitor the optional external 14V charge pump. Connect a resistive voltage-divider from 14V
charge pump output to GND to detect the output. If SECFB drops below the threshold voltage, LGATE1 turns on for
300ns. This will refresh the external charge pump driven by LGATE1 without over-discharging the output voltage.
7 FN6453.3
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ISL6236A
21 GND Analog Ground for both SMPS and LDO. Connect externally to the underside of the exposed pad.
22 PGND Power Ground for SMPS controller. Connect PGND externally to the underside of the exposed pad.
23 LGATE2 SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC.
24 BOOT2 Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the “Typical Application
Circuits” on page 19 (Figures 66, 67 and 68). See “MOSFET Gate Drivers (UGATE, LGATE)” on page 29.
25 PHASE2 Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver.
PHASE2 is the current-sense input for the SMPS2.
26 UGATE2 High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE1 swings between PHASE2 and BOOT2.
27 EN2 SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than
the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start). Drive
EN2 below 0.8V to clear fault level and reset the fault latches.
28 POK2 SMP2 Power-Good Open-Drain Output. POK2 is low when the SMPS2 output voltage is more than 10% below the
normal regulation point or during soft-start. POK2 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK2 is low in shutdown.
29 SKIP Low-Noise Mode Control. Connect SKIP to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM
mode (fixed frequency). Connect to REF or leave floating for ultrasonic skip mode operation.
30 OUT2 SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. OUT2 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode.
31 ILIM2 SMPS2 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM2 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM2. Connect ILIM2 to REF for a fixed 200mV.
The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V.
32 REFIN2 Output voltage control for SMPS2. Connect REFIN2 to VCC for fixed 3.3V. Connect REFIN2 to VREF3 for fixed 1.05V.
REFIN2 can be used to program SMPS2 output voltage from 0.5V to 2.50V. SMPS2 output voltage is 0V if
REFIN2 < 0.5V.
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C.
70 70
EFFICIENCY (%)
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 1. VOUT2 = 1.05V EFFICIENCY vs LOAD (300kHz) FIGURE 2. VOUT1 = 1.5V EFFICIENCY vs LOAD (200kHz)
8 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
7VIN SKIP MODE 12VIN ULTRA SKIP MODE 7VIN SKIP MODE 12VIN ULTRA SKIP MODE
7VIN PWM MODE 25VIN SKIP MODE 7VIN PWM MODE 25VIN SKIP MODE
7VIN ULTRA SKIP MODE 25VIN PWM MODE 7VIN ULTRA SKIP MODE 25VIN PWM MODE
12VIN SKIP MODE 25VIN ULTRA SKIP MODE 12VIN SKIP MODE 25VIN ULTRA SKIP MODE
12VIN PWM MODE 12VIN PWM MODE
100 100
90 90
80 80
EFFICIENCY (%)
EFFICIENCY (%)
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 3. VOUT2 = 3.3V EFFICIENCY vs LOAD (500kHz) FIGURE 4. VOUT1 = 5V EFFICIENCY vs LOAD (400kHz)
7VIN SKIP MODE 12VIN ULTRA SKIP MODE 7VIN SKIP MODE 12VIN ULTRA SKIP MODE
7VIN PWM MODE 25VIN SKIP MODE 7VIN PWM MODE 25VIN SKIP MODE
7VIN ULTRA SKIP MODE 25VIN PWM MODE 7VIN ULTRA SKIP MODE 25VIN PWM MODE
12VIN SKIP MODE 25VIN ULTRA SKIP MODE 12VIN SKIP MODE 25VIN ULTRA SKIP MODE
12VIN PWM MODE 12VIN PWM MODE
1.070 1.540
1.068 1.535
1.066
OUTPUT VOLTAGE (V)
1.530
1.064
1.062 1.525
1.060 1.520
1.058 1.515
1.056
1.510
1.054
1.052 1.505
1.050 1.500
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 5. VOUT2 = 1.05V REGULATION vs LOAD (300kHz) FIGURE 6. VOUT1 = 1.5V REGULATION vs LOAD (200kHz)
7VIN SKIP MODE 12VIN ULTRA SKIP MODE 7VIN SKIP MODE 12VIN ULTRA SKIP MODE
7VIN PWM MODE 25VIN SKIP MODE 7VIN PWM MODE 25VIN SKIP MODE
7VIN ULTRA SKIP MODE 25VIN PWM MODE 7VIN ULTRA SKIP MODE 25VIN PWM MODE
12VIN SKIP MODE 25VIN ULTRA SKIP MODE 12VIN SKIP MODE 25VIN ULTRA SKIP MODE
12VIN PWM MODE 12VIN PWM MODE
3.38 5.16
3.37 5.14
OUTPUT VOLTAGE (V)
5.12
3.36
5.10
3.35
5.08
3.34
5.06
3.33
5.04
3.32 5.02
3.31 5.00
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 7. VOUT2 = 3.3V REGULATION vs LOAD (500kHz) FIGURE 8. VOUT1 = 5V REGULATION vs LOAD (400kHz)
9 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
7VIN SKIP MODE 12VIN ULTRA SKIP MODE 7VIN SKIP MODE 12VIN ULTRA SKIP MODE
7VIN PWM MODE 25VIN SKIP MODE 7VIN PWM MODE 25VIN SKIP MODE
7VIN ULTRA SKIP MODE 25VIN PWM MODE 7VIN ULTRA SKIP MODE 25VIN PWM MODE
12VIN SKIP MODE 25VIN ULTRA SKIP MODE 12VIN SKIP MODE 25VIN ULTRA SKIP MODE
12VIN PWM MODE 12VIN PWM MODE
2.5 2.5
POWER DISSIPATION (W)
1.5 1.5
1.0 1.0
0.5 0.5
0.0 0.0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 9. VOUT2 = 1.05V POWER DISSIPATION vs LOAD FIGURE 10. VOUT1 = 1.5V POWER DISSIPATION vs LOAD
(300kHz) (200kHz)
7VIN SKIP MODE 12VIN ULTRA SKIP MODE 7VIN SKIP MODE 12VIN ULTRA SKIP MODE
7VIN PWM MODE 25VIN SKIP MODE 7VIN PWM MODE 25VIN SKIP MODE
7VIN ULTRA SKIP MODE 25VIN PWM MODE 7VIN ULTRA SKIP MODE 25VIN PWM MODE
12VIN SKIP MODE 25VIN ULTRA SKIP MODE 12VIN SKIP MODE 25VIN ULTRA SKIP MODE
12VIN PWM MODE 12VIN PWM MODE
3.5 3.5
3.0 3.0
POWER DISSIPATION (W)
POWER DISSIPATION (W)
2.5 2.5
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0.0 0.0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 11. VOUT2 = 3.3V POWER DISSIPATION vs LOAD FIGURE 12. VOUT1 = 5V POWER DISSIPATION vs LOAD
(500kHz) (400kHz)
1.064 1.068
NO LOAD PWM
1.062 1.066
1.064
OUTPUT VOLTAGE (V)
1.060
1.062 NO LOAD PWM
1.058
1.060
1.056 1.058
10 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
1.518 1.530
1.516 1.525
OUTPUT VOLTAGE (V)
1.506 1.505
1.504 1.500
5 7 9 11 13 15 17 19 21 23 25 5 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
FIGURE 15. VOUT1 = 1.5V OUTPUT VOLTAGE REGULATION FIGURE 16. VOUT1 = 1.5V OUTPUT VOLTAGE REGULATION
vs VIN (PWM MODE) vs VIN (SKIP MODE)
3.340 3.380
3.370
3.335 NO LOAD PWM
OUTPUT VOLTAGE (V)
3.360
NO LOAD PWM
3.330
3.350
3.330
3.320
3.320
MID LOAD PWM
3.315
3.310 MID LOAD PWM
MAX LOAD PWM
3.310 3.300
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
FIGURE 17. VOUT2 = 3.3V OUTPUT VOLTAGE REGULATION FIGURE 18. VOUT2 = 3.3V OUTPUT VOLTAGE REGULATION
vs VIN (PWM MODE) vs VIN (SKIP MODE)
5.065
NO LOAD PWM 5.14
5.060
OUTPUT VOLTAGE (V)
5.12
11 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
300 50
45
250
40
FREQUENCY (kHz)
35
200
RIPPLE (mV)
PWM 30
150 25 PWM
ULTRA-SKIP
20
100
ULTRA-SKIP 15
10
50
5 SKIP
SKIP
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 21. VOUT2 = 1.05V FREQUENCY vs LOAD FIGURE 22. VOUT2 = 1.05V RIPPLE vs LOAD
250 50
PWM 45
200 40
FREQUENCY (kHz)
PWM
35
RIPPLE (mV)
150 30
25
100 20 ULTRA-SKIP SKIP
ULTRA-SKIP
15
50 10
SKIP 5
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 23. VOUT1 = 1.5V FREQUENCY vs LOAD FIGURE 24. VOUT1 = 1.5V RIPPLE vs LOAD
600 14
PWM PWM
500 12
FREQUENCY (kHz)
10
400
RIPPLE (mV)
8 ULTRA-SKIP
300 SKIP
6
200
ULTRA-SKIP 4
100 2
SKIP
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 25. VOUT2 = 3.3V FREQUENCY vs LOAD FIGURE 26. VOUT2 = 3.3V RIPPLE vs LOAD
12 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
450 40
PWM
400 35
350 30
FREQUENCY (kHz)
PWM ULTRA-SKIP
300
RIPPLE (mV)
25
250
20
200 SKIP
15
150
100 ULTRA-SKIP 10
50 5
SKIP
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 27. VOUT1 = 5V FREQUENCY vs LOAD FIGURE 28. VOUT1 = 5V RIPPLE vs LOAD
5.04 3.35
5.02
BYP = 0V 3.30
5.00
OUTPUT VOLTAGE (V)
4.98 3.25
BYP = 0V
4.96
3.20
4.94
4.92 3.15
FIGURE 29. LDO OUTPUT 5V vs LOAD FIGURE 30. LDO OUTPUT 3.3V vs LOAD
3.5 15.5
3.0
15.0
OUTPUT VOLTAGE (V)
2.5
14.5
2.0
14.0
1.5
13.5
1.0
0.5 13.0
0 12.5
0 2 4 6 8 10 0 2 4 5 8 10
OUTPUT LOAD (mA) OUTPUT LOAD (mA)
FIGURE 31. VREF3 vs LOAD FIGURE 32. CHARGE PUMP vs LOAD (PWM)
13 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
50 1400
45 1200
INPUT CURRENT (mA)
20 0.0
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
FIGURE 33. PWM NO LOAD INPUT CURRENT vs VIN FIGURE 34. SKIP NO LOAD INPUT CURRENT vs VIN
(EN = EN2 = EN LDO = VCC) (EN1 = EN2 = EN LDO = VCC)
177.5 26.5
177.0 26.0
176.5 25.5
INPUT CURRENT (µA)
176.0 25.0
175.5 24.5
175.0 24.0
174.5 23.5
174.0 23.0
173.5 22.5
173.0 22.0
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
FIGURE 35. STANDBY INPUT CURRENT vs VIN FIGURE 36. SHUTDOWN INPUT CURRENT vs VIN
(EN = EN2 = 0, EN LDO = VCC) (EN = EN2 = EN LDO = 0)
VREF3 500mV/DIV
EN1 5V/DIV
VOUT1 2V/DIV
LDO 1V/DIV
CP 5V/DIV
POK1 2V/DIV
FIGURE 37. REF, VREF3, LDO = 5V, CP, NO LOAD FIGURE 38. START-UP VOUT1 = 5V (NO LOAD, SKIP MODE)
14 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
FIGURE 39. START-UP VOUT1 = 5V (NO LOAD, PWM MODE) FIGURE 40. START-UP VOUT1 = 5V (FULL LOAD, PWM MODE)
IL2 2A/DIV
IL2 2A/DIV
POK2 2V/DIV POK2 2V/DIV
FIGURE 41. START-UP VOUT2 = 3.3V (NO LOAD, SKIP MODE) FIGURE 42. START-UP VOUT1 = 3.3V (NO LOAD, PWM MODE)
EN2 5V/DIV
EN2 5V/DIV
VOUT2 2V/DIV
FIGURE 43. START-UP VOUT1 = 3.3V (FULL LOAD, FIGURE 44. DELAYED START-UP (VOUT1 = 5V, VOUT2 = 3.3V,
PWM MODE) EN1 = REF)
15 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
EN1 5V/DIV
EN1 5V/DIV VOUT2 2V/DIV
FIGURE 45. DELAYED START-UP (VOUT1 = 5V, VOUT2 = 3.3V, FIGURE 46. SHUTDOWN (VOUT1 = 5V, VOUT2 = 3.3V,
EN2 = REF) EN2 = REF)
FIGURE 47. LOAD TRANSIENT VOUT1 = 5V FIGURE 48. LOAD TRANSIENT VOUT1 = 5V (SKIP)
IL2 5A/DIV
FIGURE 49. LOAD TRANSIENT VOUT1 = 3.3V (PWM) FIGURE 50. LOAD TRANSIENT VOUT1 = 3.3V (SKIP)
16 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
FIGURE 51. VOUT2 TRACKING TO REFIN2 FIGURE 52. LDO TRACKING TO LDOREFIN
IL1 2A/DIV
IL1 2A/DIV
FIGURE 53. START-UP VOUT1 = 1.5V (NO LOAD, SKIP MODE) FIGURE 54. START-UP VOUT1 = 1.5V (NO LOAD, PWM MODE)
VOUT2 0.5V/DIV
FIGURE 55. START-UP VOUT1 = 1.5V (FULL LOAD, FIGURE 56. START-UP VOUT2 = 1.05V (NO LOAD,
PWM MODE) SKIP MODE)
17 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
EN2 5V/DIV
EN2 5V/DIV VOUT2 0.5V/DIV
VOUT2 0.5V/DIV
IL2 2A/DIV
IL2 2A/DIV
FIGURE 57. START-UP VOUT1 = 1.05V (NO LOAD, FIGURE 58. START-UP VOUT1 = 1.05V (FULL LOAD,
PWM MODE) PWM MODE)
EN1 500mV/DIV
VOUT2 0.5V/DIV
FIGURE 59. DELAYED START-UP (VOUT1 = 1.5V, FIGURE 60. DELAYED START-UP (VOUT1 = 1.5V,
VOUT2 = 1.05V, EN1 = REF) VOUT2 = 1.05V, EN2 = REF)
LGATE1 5V/DIV
EN1 5V/DIV
VOUT1 2V/DIV
IL1 5A/DIV
FIGURE 61. SHUTDOWN (VOUT1 = 1.5V, VOUT2 = 1.05V, FIGURE 62. LOAD TRANSIENT VOUT1 = 1.5V (PWM)
EN2 = REF)
18 FN6453.3
March 18, 2008
ISL6236A
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C. (Continued)
FIGURE 63. LOAD TRANSIENT VOUT1 = 1.5V (SKIP) FIGURE 64. LOAD TRANSIENT VOUT1 = 1.05V (PWM)
LGATE2 5V/DIV
IL2 5A/DIV
VOUT2 RIPPLE 20mV/DIV
19 FN6453.3
March 18, 2008
ISL6236A
addition, SMPS2 can also use REFIN2 to track its output from as measured by the VIN input and proportional to the output
0.5V to 2.50V. The ISL6236A contains fault-protection circuits voltage. This algorithm results in a nearly constant switching
that monitor the main PWM outputs for undervoltage and frequency despite the lack of a fixed-frequency clock
overvoltage conditions. A power-on sequence block controls generator. The benefit of a constant switching frequency is
the power-up timing of the main PWMs and monitors the that the frequency can be selected to avoid noise-sensitive
outputs for undervoltage faults. The ISL6236A includes an frequency regions, as shown in Equation 1:
adjustable low drop-out linear regulator. The bias generator K ( V OUT + I LOAD ⋅ r DS ( ON ) ( LOWERQ ) )
t ON = ---------------------------------------------------------------------------------------------------------- (EQ. 1)
blocks include the linear regulator, 3.3V precision reference, 2V V IN
precision reference and automatic bootstrap switchover circuit.
See Table 2 for approximate K- factors. Switching frequency
The synchronous-switch gate drivers are directly powered
increases as a function of load current due to the increasing
from PVCC, while the high-side switch gate drivers are
drop across the synchronous rectifier, which causes a faster
indirectly powered from PVCC through an external capacitor
inductor-current discharge ramp. On-times translate only
and an internal Schottky diode boost circuit.
roughly to switching frequencies. The on-times established
An automatic bootstrap circuit turns off the LDO linear in the “Electrical Specifications” table on page 4 are
regulator and powers the device from BYP if LDOREFIN is influenced by switching delays in the external high-side
set to GND or VCC. See Table 1. power MOSFET. Also, the dead-time effect increases the
TABLE 1. LDO OUTPUT VOLTAGE TABLE
effective on-time, reducing the switching frequency. It occurs
only in PWM mode (SKIP = VCC) and during dynamic output
LDO VOLTAGE CONDITIONS COMMENT voltage transitions when the inductor current reverses at
VOLTAGE at BYP LDOREFIN < 0.3V, Internal LDO is light or negative load currents. With reversed inductor
BYP > 4.63V disabled. current, the inductor's EMF causes PHASE to go high earlier
VOLTAGE at BYP LDOREFIN > VCC - 1V, Internal LDO is than normal, extending the on-time by a period equal to the
BYP > 3V disabled. UGATE-rising dead time.
5V LDOREFIN < 0.3V, Internal LDO is TABLE 2. APPROXIMATE K-FACTOR ERRORS
BYP < 4.63V active.
SWITCHING APPROXIMATE
3.3V LDOREFIN > VCC - 1V, Internal LDO is FREQUENCY K-FACTOR K-FACTOR
BYP < 3V active. SMPS (kHz) (µs) ERROR (%)
2 x LDOREFIN 0.35V < LDOREFIN < 2.25V Internal LDO is (tON = GND, REF, 400 2.5 ±10
active. or OPEN), VOUT1
20 FN6453.3
March 18, 2008
ISL6236A
5V
C5
1µF
C8
1µF
PVCC VCC LDO NC
Q3a Q1
SI4816BDY UGATE1 UGATE2 IRF7821
OUT1 – PCI-e C9 C4 OUT2-GFX
L1: 3.3µH L2: 2.2µH TRACK REFIN2/10A
1.25V/5A 0.1µF 0.22µF
PHASE1 PHASE2
Q3b Q2
C11 LGATE2 C2
LGATE1
330µF IRF7832
2 x 330µF
9mΩ 4mΩ
6.3V OUT1 PGND 6.3V
VCC
R1 OUT2
EN1
7.87kΩ
5V BYP VCC 2 BITS
ISL6236A EN2
DAC
REFIN2: DYNAMIC 0V TO 2.5V
FB1 REFIN2 TIED TO VREF3 = 1.05V
FB1 TIED TO GND = 5V
FB1 TIED TO VCC = 1.5V REFIN2 TIED TO VCC = 3.3V + -
AGND REFIN2 + DROOP
R2 R3 R5
200kΩ +
10kΩ 200kΩ
ILIM1 ILIM2
C3 VCC VCC
OPEN
SKIP VREF3
C7
R4 R6
GND EN LDO 0.1µF
REF 200kΩ 200kΩ
FREQUENCY-DEPENDENT COMPONENTS
L1 3.3µH
L2 2.7µH
C2 2 x 330µF
C11 330µF
21 FN6453.3
March 18, 2008
ISL6236A
5V
C5
1µF
LDOREFIN TIED TO GND = 5V
C8 LDOREFIN TIED TO VCC = 3.3V
1µF LDO
PVCC VCC LDO
VCC C6
VIN LDOREFIN F
4.7µF
C10 C1
10µF SI4816BDY BOOT1 BOOT2 10
10µF
Q3a
UGATE2 Q1a
UGATE1
OUT1 C9 C4 OUT2
L1: 3.3µH L2: 2.2µF 1.05V/5A
1.5V/5A 0.1µF 0.22µF
PHASE1 PHASE2
Q3b
C11 LGATE2 Q1b SI4816BDY C2
LGATE1
330µF 330µF
9mΩ 4mΩ
6.3V OUT1 PGND 6.3V
VCC
EN1 OUT2
FREQUENCY-DEPENDENT COMPONENTS
L1 3.3µH
L2 2.7µH
C2 330µF
C11 330µF
FIGURE 67. ISL6236A TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITHOUT CHARGE PUMP
22 FN6453.3
March 18, 2008
ISL6236A
R7 C5
10Ω 1µF
Q3b
C11 LGATE2 Q1b SI4816BDY C2
LGATE1
330µF 330µF
9mΩ 4mΩ
6.3V OUT1 PGND 6.3V
VCC
EN1 OUT2
*NOTE: To prevent noise in high loading conditions, place a 10Ω resistor between VIN and PVCC. Additional
electrolytic bulk decoupling can also be used for this purpose
FREQUENCY-DEPENDENT COMPONENTS
L1 3.3µH
L2 2.7µH
C2 330µF
C11 330µF
FIGURE 68. ISL6236A TYPICAL LOW INPUT VOLTAGE SYSTEM REGULATOR APPLICATION CIRCUIT WITHOUT CHARGE PUMP
23 FN6453.3
March 18, 2008
ISL6236A
C5
1µF
LDOREFIN TIED TO GND = 5V
LDOREFIN TIED TO VCC = 3.3V
VCC LDO
PVCC LDO
C6
VIN LDOREFIN
4.7µF
C10 C1
10µF BOOT1 BOOT2 10µF
10
Q3 Q1
IRF7807V UGATE1 UGATE2 IRF7821
OUT1 C9 C4 OUT2
L1: 4.7µH 0.1µF L2: 4.7µH 3.3V/11A
5V/7A 0.1µF
PHASE1 PHASE2
Q4 Q2
C11 LGATE1 LGATE2 C2
IRF7811AV IRF7832
330µF 330µF
9mΩ 9mΩ
6.3V OUT1 PGND 4V
VCC
D3 EN1 ISL6236A OUT2
FREQUENCY-DEPENDENT COMPONENTS
tON = REF
5V/3.3V SMPS
tON = VCC (OR OPEN) tON = GND
SWITCHING
FREQUENCY 200kHz/300kHz 400kHz/300kHz 400kHz/500kHz
FIGURE 69. ISL6236A TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITH 14V CHARGE PUMP
24 FN6453.3
March 18, 2008
ISL6236A
TON SKIP
BOOT1 BOOT2
UGATE1 UGATE2
PHASE1 PHASE2
PVCC PVCC
ILIM1 ILIM2
EN1 EN2
SECFB
FB1 POK1 POK2 REFIN2
OUT1 OUT2
OUT1 OUT2
BYP POK2
SW THRESHOLD
-
POK1
LDO
LDO
VCC
LDOREFIN INTERNAL
LOGIC
10Ω
VIN
PVCC
EN LDO
VREF3
POWER-ON VREF3
EN1 SEQUENCE
SQUENCE
CLEAR FAULT
CLEAR FAULT
LATCH
EN2 LATCH THERMAL
THERMAL REF
SHUTDOWN
SHUTDOWN REF
25 FN6453.3
March 18, 2008
ISL6236A
tON
MIN. tOFF
VIN Q TRIG
ONE SHOT
+ TO UGATE DRIVER
OUT Q
R Q
S Q
Q
REFIN2 (SMPS2)+
+
VREF +
ILIM +
COMP
+ SLOPE COMP +
BOOT BOOT
UV
5µA DETECT
VCC +
TO LGATE DRIVER
Σ
Â
+
PHASE
OUT
+ Q
S Q
R Q
Q
SKIP ONE-SHOT
SECFB
+
2V
FB + SMSP1 ONLY
PGOOD
DECODER 0.9VREF
FB +
OV LATCH
1.1VREF FAULT
FAULT
LATCH
UV LATCH LATCH
LOGIC
+
20ms
0.7VREF
BLANKING
26 FN6453.3
March 18, 2008
ISL6236A
Automatic Pulse-Skipping Switchover conduction, the output voltage has a DC regulation higher
(Idle Mode) than the trip level by 50% of the ripple. In discontinuous
conduction (SKIP = GND, light load), the output voltage has
In Idle Mode (SKIP = GND), an inherent automatic
a DC regulation higher than the trip level by approximately
switchover to PFM takes place at light loads. This switchover
1.0% due to slope compensation.
is affected by a comparator that truncates the low-side
switch on-time at the inductor current's zero crossing. This Forced-PWM Mode
mechanism causes the threshold between pulse-skipping
The low-noise, forced-PWM (SKIP = VCC) mode disables
PFM and nonskipping PWM operation to coincide with the
the zero-crossing comparator, which controls the low-side
boundary between continuous and discontinuous
switch on-time. Disabling the zero-crossing detector causes
inductor-current operation (also known as the critical
the low-side, gate-drive waveform to become the
conduction point):
complement of the high-side, gate-drive waveform. The
K ⋅ V OUT V IN – V OUT
I LOAD ( SKIP ) = ------------------------ -------------------------------- (EQ. 3) inductor current reverses at light loads as the PWM loop
2⋅L V IN
strives to maintain a duty ratio of VOUT/VIN. The benefit of
forced-PWM mode is to keep the switching frequency fairly
where K is the on-time scale factor (see “ON-TIME ONE-
constant, but it comes at a cost: the no-load battery current
SHOT (tON)” on page 20). The load-current level at which
can be 10mA to 50mA, depending on switching frequency
PFM/PWM crossover occurs, ILOAD(SKIP), is equal to half
and the external MOSFETs.
the peak-to-peak ripple current, which is a function of the
inductor value (Figure 72). For example, in the ISL6236A Forced-PWM mode is most useful for reducing
typical application circuit with VOUT1 = 5V, VIN = 12V, audio-frequency noise, improving load-transient response,
L = 7.6µH, and K = 5µs, switchover to pulse-skipping providing sink-current capability for dynamic output voltage
operation occurs at ILOAD = 0.96A or about on-fifth full load. adjustment, and improving the cross-regulation of
The crossover point occurs at an even lower value if a multiple-output applications that use a flyback transformer or
swinging (soft-saturation) inductor is used. coupled inductor.
27 FN6453.3
March 18, 2008
ISL6236A
where:
I LOAD
simultaneously shutting down the internal linear regulator. ΔI
No switchover action in adjustable mode.
I LIMIT
In Figure 68, the external 14V charge pump is driven by I LOAD(MAX)
LGATE1. When LGATE1 is low, D1a charged C8 sourced
from OUT1. C8 voltage is equal to OUT1 minus a diode ΔI
ILIM (VAL) = I
drop. When LGATE1 transitions to high, the charges from C8 LOAD - 2
will transfer to C12 through D1b and charge it to VLGATE1
plus VC8. As LGATE1 transitions low on the next cycle, C12 TIME
will charge C14 to its voltage minus a diode drop through
FIGURE 74. “VALLEY” CURRENT LIMIT THRESHOLD POINT
28 FN6453.3
March 18, 2008
ISL6236A
29 FN6453.3
March 18, 2008
ISL6236A
• PVCC is 5V When the output voltage of VOUT1 is 11% (16% for VOUT2)
above the set voltage, the overvoltage fault protection
• CGS is the gate capacitance of the high-side MOSFET activates. This latches on the synchronous rectifier MOSFET
with 100% duty cycle, rapidly discharging the output
Boost-Supply Refresh Monitor capacitor until the negative current limit is achieved. Once
In pure skip mode, the converter frequency can be very low negative current limit is met, UGATE is turned on for a
with little to no output loading. This produces very long off minimum on-time, followed by another LGATE pulse until
times, where leakage can bleed down the BOOT capacitor negative current limit. This effectively regulates the
voltage. If the voltage falls too low, the converter may not be discharge current at the negative current limit in an effort to
able to turn on UGATE when the output voltage falls to the prevent excessively large negative currents that cause
reference. To prevent this, the ISL6236A monitors the BOOT potentially damaging negative voltages on the load. Once an
capacitor voltage, and if it falls below 3V, it initiates an overvoltage fault condition is set, it can only be reset by
LGATE pulse, which will refresh the BOOT voltage. toggling SHDN, EN, or cycling VIN (POR).
30 FN6453.3
March 18, 2008
ISL6236A
Power-Up Sequencing and On/Off Controls (EN ) second SMPS remains on until the first SMPS turns off, the
EN1 and EN2 control SMPS power-up sequencing. EN1 or device shuts down, a fault occurs or PVCC goes into
EN2 rising above 2.4V enables the respective outputs. EN1 undervoltage lockout. Both supplies begin their power-down
or EN2 falling below 1.6V disables the respective outputs. sequence immediately when the first supply turns off. Driving
EN below 0.8V clears the overvoltage, undervoltage and
Connecting EN1 or EN2 to REF will force its outputs off while thermal fault latches.
the other output is below regulation. The sequenced SMPS
will start once the other SMPS reaches regulation. The
Power-Up PVCC < UVLO threshold. Transitions to discharge mode after a VIN POR and after REF becomes valid. LDO,
VREF3 and REF remain active.
Overvoltage Either output > 111% (VOUT1) or LGATE is forced high. LDO, VREF3 and REF active. Exited by a VIN POR, or by
Protection 116% (VOUT2) of nominal level. toggling EN1 or EN2.
Undervoltage Either output < 70% of nominal after The internal 25Ω switch turns on. LDO, VREF3 and REF are active. Exited by a VIN
Protection 20ms time-out expires and output is POR or by toggling EN1 or EN2.
enabled.
Discharge Either SMPS output is still high in Discharge switch (25Ω) connects OUT to GND. One output may still run while the
either standby mode or shutdown other is in discharge mode. Activates when PVCC is in UVLO, or transition to UVLO,
mode standby, or shutdown has begun. LDO, VREF3 and REF active.
Standby EN1, EN2 < start-up threshold, EN LDO, VREF3 and REF active.
LDO = High
Shutdown EN1, EN2, EN LDO = low Discharge switch (25Ω) connects OUT to PGND. All circuitry off except VREF3.
Thermal Shutdown TJ > +150°C All circuitry off. Exited by VIN POR or cycling EN. VREF3 remain active.
31 FN6453.3
March 18, 2008
ISL6236A
Adjustable-Output Feedback (Dual-Mode FB) condition. The minimum practical inductor value is one
Connect FB1 to GND to enable the fixed 5V or tie FB1 to that causes the circuit to operate at critical conduction
(where the inductor current just touches zero with every
VCC to set the fixed 1.5V output. Connect a resistive
cycle at maximum load). Inductor values lower than this
voltage-divider at FB1 between OUT1 and GND to adjust the
grant no further size-reduction benefit.
respective output voltage between 0.7V and 5.5V (see
The ISL6236A pulse-skipping algorithm (SKIP = GND)
Figure 77). Choose R2 to be approximately 10k and solve for
initiates skip mode at the critical conduction point, so the
R1 using Equation 6.
inductor's operating point also determines the load
⎛ V OUT1 ⎞ current at which PWM/PFM switchover occurs. The
R 1 = R 2 ⋅ ⎜ ------------------- – 1⎟
⎝ V FB1 ⎠ optimum LIR point is usually found between 25% and
(EQ. 6)
50% ripple current.
where VFB1 = 0.7V nominal.
VIN
Likewise, connect REFIN2 to VCC to enable the fixed 3.3V
or tie REFIN2 to VREF3 to set the fixed 1.05V output. Set
UGATE1 Q3
REFIN2 from 0V to 2.50V for SMPS2 tracking mode (see
Figure 78).
OUT1
R 3 = R 4 ⋅ ⎛ ------------------- – 1⎞
VR
⎝V ⎠ ISL6236A
OUT2 (EQ. 7)
LGATE1 Q4
where:
32 FN6453.3
March 18, 2008
ISL6236A
Example: ILOAD(MAX) = 5A, VIN = 12V, VOUT2 = 5V, 4.17A is greater than the valley current of 4.12A, so the
f = 200kHz, 35% ripple current or LIR = 0.35: circuit can easily deliver the full-rated 5A using the 30mV
5V ( 12V – 5V ) (EQ. 9)
nominal current-limit threshold voltage.
L = ----------------------------------------------------------------- = 8.3μH
12V ⋅ 200kHz ⋅ 0.35 ⋅ 5A
Output Capacitor Selection
Find a low-loss inductor having the lowest possible DC The output filter capacitor must have low enough equivalent
resistance that fits in the allotted dimensions. Ferrite cores series resistance (ESR) to meet output ripple and
are often the best choice. The core must be large enough load-transient requirements, yet have high enough ESR to
not to saturate at the peak inductor current (IPEAK) shown in satisfy stability requirements. The output capacitance must
Equation 10: also be high enough to absorb the inductor energy while
IPEAK = I LOAD ( MAX ) + [ ( LIR ⁄ 2 ) ⋅ I LOAD ( MAX ) ] (EQ. 10) transitioning from full-load to no-load conditions without
tripping the overvoltage fault latch. In applications where the
output is subject to large load transients, the output
The inductor ripple current also impacts transient response
capacitor's size depends on how much ESR is needed to
performance, especially at low VIN - VOUT differences. Low
prevent the output from dipping too low under a load
inductor values allow the inductor current to slew faster,
transient. Ignoring the sag due to finite capacitance:
replenishing charge removed from the output filter capacitors
by a sudden load step. The peak amplitude of the output V DIP
R SER ≤ ---------------------------------- (EQ. 15)
transient (VSAG) is also a function of the maximum duty I LOAD ( MAX )
factor, which can be calculated from the on-time and
minimum off-time: where VDIP is the maximum-tolerable transient voltage drop.
⎛ ⎛ V OUT_ ⎞⎞ In non-CPU applications, the output capacitor's size
2
( ΔI LOAD ( MAX ) ) ⋅ L ⎜ K ⎜ ------------------- + t OFF ( MIN )⎟ ⎟ depends on how much ESR is needed to maintain an
⎝ ⎝ V IN ⎠⎠
VSAG = ---------------------------------------------------------------------------------------------------------------------------- acceptable level of output voltage ripple:
⎛ V IN – V OUT⎞
2 ⋅ C OUT ⋅ V OUT K ⎜ --------------------------------⎟ - t VP – P
⎝ V IN ⎠ OFF ( MIN ) R ESR ≤ ----------------------------------------------- (EQ. 16)
L IR ⋅ I LOAD ( MAX )
(EQ. 11)
where VP-P is the peak-to-peak output voltage ripple. The
where minimum off-time = 0.35µs (max) and K is from actual capacitance value required relates to the physical size
Table 2. needed to achieve low ESR, as well as to the chemistry of
Determining the Current Limit the capacitor technology. Thus, the capacitor is usually
selected by ESR and voltage rating rather than by
The minimum current-limit threshold must be great enough
capacitance value (this is true of tantalum, OS-CON, and
to support the maximum load current when the current limit
other electrolytic-type capacitors).
is at the minimum tolerance value. The valley of the inductor
current occurs at ILOAD(MAX) minus half of the ripple When using low-capacity filter capacitors such as polymer
current; therefore: types, capacitor size is usually determined by the capacity
required to prevent VSAG and VSOAR from tripping the
I LIMIT ( LOW ) > I LOAD ( MAX ) – [ ( LIR ⁄ 2 ) ⋅ I LOAD ( MAX ) ] (EQ. 12)
undervoltage and overvoltage fault latches during load
transients in ultrasonic mode.
where: ILIMIT(LOW) = minimum current-limit threshold
voltage divided by the rDS(ON) of Q2/Q4. For low input-to-output voltage differentials (VIN/ VOUT < 2),
additional output capacitance is required to maintain stability
Use the worst-case maximum value for rDS(ON) from the
and good efficiency in ultrasonic mode. The amount of
MOSFET Q2/Q4 data sheet and add some margin for the
overshoot due to stored inductor energy can be calculated
rise in rDS(ON) with temperature. A good general rule is to
as shown in Equation 17:
allow 0.2% additional resistance for each °C of temperature 2
rise. I PEAK ⋅ L
V SOAR = ------------------------------------------------ (EQ. 17)
2 ⋅ C OUT ⋅ V OUT_
33 FN6453.3
March 18, 2008
ISL6236A
34 FN6453.3
March 18, 2008
ISL6236A
while both switches are off (dead time). The drop is where VDROP1 and VDROP2 are the parasitic voltage drops
I L ⋅ r DS ( ON ) when the low-side switch conducts. in the discharge and charge paths (see “ON-TIME ONE-
SHOT (tON)” on page 20), tOFF(MIN) is from “Electrical
The rectifier is a clamp across the synchronous rectifier that
Specifications” table on page 6 and K is taken from Table 2.
catches the negative inductor swing during the dead time
The absolute minimum input voltage is calculated with h = 1.
between turning the high-side MOSFET off and the
synchronous rectifier on. The MOSFETs incorporate a Operating frequency must be reduced or h must be
high-speed silicon body diode as an adequate clamp diode if increased and output capacitance added to obtain an
efficiency is not of primary importance. Place a Schottky acceptable VSAG if calculated VIN(MIN) is greater than the
diode in parallel with the body diode to reduce the forward required minimum input voltage. Calculate VSAG to be sure
voltage drop and prevent the Q2/Q4 MOSFET body diodes of adequate transient response if operation near dropout is
from turning on during the dead time. Typically, the external anticipated.
diode improves the efficiency by 1% to 2%. Use a Schottky
Dropout Design Example:
diode with a DC current rating equal to one-third of the load
current. For example, use an MBR0530 (500mA-rated) type ISL6236A: With VOUT2 = 5V, fsw = 400kHz, K = 2.25µs,
for loads up to 1.5A, a 1N5817 type for loads up to 3A, or a tOFF(MIN) = 350ns, VDROP1 = VDROP2 = 100mV, and
1N5821 type for loads up to 10A. The rectifier's rated h = 1.5, the minimum VIN is:
reverse breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating ( 5V + 0.1V ) (EQ. 24)
V IN ( MIN ) = ---------------------------------------------- + 0.1V – 0.1V = 6.65V
0.35μs ⋅ 1.5
factor. 1 – ⎛ -------------------------------⎞
⎝ 2.25μs ⎠
35 FN6453.3
March 18, 2008
ISL6236A
approached in terms of fractions of centimeters, where a Group the gate-drive components (BOOT capacitor, VIN
single mΩ of excess trace resistance causes a bypass capacitor) together near the controller device.
measurable efficiency penalty.
Make the DC/DC controller ground connections as follows:
• PHASE (ISL6236A) and GND connections to the
synchronous rectifiers for current limiting must be made 1. Near the device, create a small analog ground plane.
using Kelvin-sense connections to guarantee the 2. Connect the small analog ground plane to GND and use
current-limit accuracy with 8 Ld SO MOSFETs. This is best the plane for the ground connection for the REF and VCC
done by routing power to the MOSFETs from outside using bypass capacitors, FB dividers and ILIM resistors (if any).
the top copper layer, while connecting PHASE traces 3. Create another small ground island for PGND and use
inside (underneath) the MOSFETs. the plane for the VIN bypass capacitor, placed very close
• When trade-offs in trace lengths must be made, it is to the device.
preferable to allow the inductor charging path to be made 4. Connect the GND and PGND planes together at the
longer than the discharge path. For example, it is better to metal tab under device.
allow some extra distance between the input capacitors On the board's top side (power planes), make a star ground
and the high-side MOSFET than to allow distance
to minimize crosstalk between the two sides. The top-side
between the inductor and the synchronous rectifier or
star ground is a star connection of the input capacitors and
between the inductor and the output filter capacitor.
synchronous rectifiers. Keep the resistance low between the
• Ensure that the OUT connection to COUT is short and star ground and the source of the synchronous rectifiers for
direct. However, in some cases it may be desirable to accurate current limit. Connect the top-side star ground
deliberately introduce some trace length between the OUT (used for MOSFET, input, and output capacitors) to the small
connector node and the output filter capacitor.
island with a single short, wide connection (preferably just a
• Route high-speed switching nodes (BOOT, UGATE, via). Create PGND islands on the layer just below the
PHASE, and LGATE ) away from sensitive analog areas top-side layer (refer to ISL6236 Evaluation Kit Application
(REF, ILIM, and FB ). Use PGND1 and PGND2 as an EMI Notes, AN1271 and AN1272 for an example) to act as an EMI
shield to keep radiated switching noise away from the IC's shield if multiple layers are available (highly recommended).
feedback divider and analog bypass capacitors. Connect each of these individually to the star ground via,
• Make all pin-strap control input connections (SKIP, ILIM, which connects the top side to the PGND plane. Add one
etc.) to GND or VCC of the device. more solid ground plane under the device to act as an
additional shield, and also connect the solid ground plane to
Layout Procedure
the star ground via.
Place the power components first with ground terminals
adjacent (Q2/Q4 source, CIN, COUT ). If possible, make all Connect the output power planes (VCORE and system
these connections on the top layer with wide, copper-filled ground planes) directly to the output filter capacitor positive
areas. and negative terminals with multiple vias.
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36 FN6453.3
March 18, 2008
ISL6236A
4X 3.5
5.00 A 28X 0.50
6
B
25 32 PIN #1 INDEX AREA
6
PIN 1 24 1
INDEX AREA
5.00
3 .30 ± 0 . 15
17 8
(4X) 0.15
16 9
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10 4 32X 0.23 - 0.05
0.10 C
0 . 90 ± 0.1 C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
( 28X 0 . 5 )
SIDE VIEW
( 3. 30 )
(32X 0 . 23 )
C 0 . 2 REF 5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
NOTES:
37 FN6453.3
March 18, 2008