SiP32431DN, SiP32431DR, SiP32432DN, SiP32432DR

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10 pA, Ultra Low Leakage and Quiescent Current,
Load Switch with Reverse Blocking
DESCRIPTION FEATURES
The SiP32431 and SiP32432 are ultra low leakage and • 1.5 V to 5.5 V input voltage range
quiescent current slew rate controlled high side switches • No bias power rail required
with reverse blocking capability. The switches are of a low • Low on-resistance RDS(on), 
on resistance p-channel MOSFET that supports continuous typically 105 m at 5 V and 135 m at 3 V for
current up to 1.4 A. TDFN4 1.2 mm x 1.6 mm package
The SiP32431 and SiP32432 operate with an input voltage • Typical 147 m at 5 V and 178 m at 3 V for Available

from 1.5 V to 5.5 V. SC-70-6 package

The SiP32431 and SiP32432 feature low input logic level to • Slew rate controlled turn-on time: 100 μs
interface with low control voltage from microprocessors. • Ultra low leakage and quiescent current:
The SiP32431 is of logic high enable control, while SiP32432 - VIN quiescent current = 0.01 nA
is of logic low enable control. Both devices have a very low - VIN shutdown leakage = 0.20 nA
operating current, typically 10 pA at 3.3 V power supply.
• Reverse blocking capability
The SiP32431 and SiP32432 are available in lead (Pb)-free
• SC-70-6 and TDFN4 1.2 mm x 1.6 mm packages
package options including 6 pin SC-70-6, and 4 pin TDFN4
• Material categorization: for definitions of compliance
1.2 mm x 1.6 mm DFN4 packages. The operation please see www.vishay.com/doc?99912
temperature range is specified from -40 °C to +85 °C.
The SiP32431 and SiP32432 compact package options, APPLICATIONS
operation voltage range, and low operating current make it • Wireless sensor network
a good fit for battery power applications. • Smart meters
• Wearable
• Internet of things
• Portable medical devices
• Security systems
• Battery powered devices
• Portable Instruments

TYPICAL APPLICATION CIRCUIT

VIN IN OUT VOUT

SiP32431 / SiP32432

C IN C OUT
1 µF 0.1 µF
ON/OFF
ON/OFF GND

GND GND
Fig. 1 - SiP32431, SiP32432 Typical Application Circuit

ORDERING INFORMATION
PART NUMBER MARKING ENABLE PACKAGE TEMPERATURE RANGE
SiP32431DR3-T1GE3 MAxx High enable
SC-70-6
SiP32432DR3-T1GE3 MDxx Low enable
-40 °C to +85 °C
SiP32431DNP3-T1GE4 Dx High enable
TDFN4 1.2 mm x 1.6 mm
SiP32432DNP3-T1GE4 Vx Low enable
Notes
• x = lot code

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• -GE3 denotes halogen-free and RoHS-compliant
• Please use the SiP32431DR3-T1GE3 to replace SiP32431DR3-T1-E3

ABSOLUTE MAXIMUM RATINGS

PARAMETER LIMIT UNIT
Supply input voltage (VIN) -0.3 to +6
Enable input voltage (VON/OFF) -0.3 to +6 V
Output voltage (VOUT) -0.3 to +6
SC-70-6 package 1.2
Maximum continuous switch current (Imax.)
TDFN4 1.2 mm x 1.6 mm 1.4
A
Maximum pulsed current (IDM) VIN VIN  2.5 V 3
(pulsed at 1 ms, 10 % duty cycle) VIN < 2.5 V 1.6
ESD rating (HBM) 4000 V
Junction temperature (TJ) -40 to +125 °C
6 pin SC-70-6 b 220
Thermal resistance (JA) a c
°C/W
4 pin TDFN4 1.2 mm x 1.6 mm 170
6 pin SC-70- 6 b 250
Power dissipation (PD) a mW
4 pin TDFN4 1.2 mm x 1.6 mm c 324
Notes
a. Device mounted with all leads and power pad soldered or welded to PC board
b. Derate 4.5 mW/°C above TA = 70 °C
c. Derate 5.9 mW/°C above TA = 70 °C, see PCB layout

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating / conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING RANGE

PARAMETER LIMIT UNIT
Input voltage range (VIN) 1.5 to 5.5 V
Operating temperature range -40 to +85 °C

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SPECIFICATIONS
TEST CONDITIONS UNLESS SPECIFIED LIMITS
PARAMETER SYMBOL VIN = 5, TA = -40 °C to +85 °C -40 °C to +85 °C UNIT
(Typical values are at TA = 25 °C) MIN. a TYP. b MAX. a
Operating voltage c VIN 1.5 - 5.5 V
VIN = 3.3 V, Von/off = 3.3 V - 0.01 100
Quiescent current IQ
VIN = 5 V, Von/off = 5 V - 0.05 1000
VIN = 3.3 V, Von/off = 0 V, OUT = open - 0.01 100
Off supply current IQ(off)
VIN = 5 V, Von/off = 0 V, OUT = open - - 1000 nA
VIN = 3.3 V, Von/off = 0 V, OUT = 1 V - 0.2 100
Off switch current ISD(off)
VIN = 5 V, Von/off = 0 V, OUT = 0 V - - 1000
Reverse blocking current IRB VOUT = 5.5 V, VIN = 0, Von/off = inactive - 130 1000
SC-70-6 - 147
VIN = 5 V, IL = 500 mA, TA = 25 °C 230
TDFN4 - 105
SC-70-6 - 155
VIN = 4.2 V, IL = 500 mA, TA = 25 °C 250
TDFN4 - 110
SC-70-6 - 178
On-resistance RDS(on) VIN = 3 V, IL = 500 mA, TA = 25 °C 290 m
TDFN4 - 135
SC-70-6 - 275
VIN = 1.8 V, IL = 500 mA, TA = 25 °C 480
TDFN4 - 230
SC-70-6 - 395
VIN = 1.5 V, IL = 500 mA, TA = 25 °C 520
TDFN4 - 350
On-resistance temp.-coefficient TDRDS - 2800 - ppm/°C
VIN  1.5 V to < 1.8 V - - 0.3
On / off input low voltage c VIL VIN  1.8 V to < 2.7 V - - 0.4
VIN  2.7 V to  5.5 V - - 0.6
V
VIN  1.5 V to < 2.7 V 1.3 - -
On / off input low voltage c VIH VIN  2.7 V to < 4.2 V 1.5 - -
VIN  4.2 V to  5.5 V 1.8 - -
Von/off = 3.3 V - 0.014 100
On / off input leakage ION/OFF nA
Von/off = 5.5 V - 0.042 1000
Output turn-on delay time td(on) - 20 40
Output turn-on rise time t(on) VIN = 5 V, Rload = 10 , TA = 25 °C - 140 180 μs
Output turn-off delay time td(off) - 4 10
Notes
a. The algebriac convention whereby the most negative value is a minimum and the most positive a maximum
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing
c. For VIN outside this range consult typical on / off threshold curve

PIN CONFIGURATION

OUT 1 6 N/C
ON/OFF 4 1 OUT

GND 2 5 GND GND

IN 3 2 GND

ON/OFF 3 4 IN

Bottom View
Top View

Fig. 2 - SC-70-6 Package Fig. 3 - TDFN4 1.2 mm x 1.6 mm Package

PIN DESCRIPTION
PIN NUMBER
NAME FUNCTION
SC-70-6 TDFN4
4 3 IN This pin is the p-channel MOSFET source connection. Bypass to ground through a 1 μF capacitor

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PIN DESCRIPTION
PIN NUMBER
NAME FUNCTION
SC-70-6 TDFN4
2, 5 2 GND Ground connection
3 4 ON / OFF Enable input
1 1 OUT This pin is the p-channel MOSFET drain connection. Bypass to ground through a 0.1 μF capacitor

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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)

0.12 300
VIN = 5 V

0.10 250

ISD(OFF) - Off Switch Current (nA)

IQ - Quiescent Current (nA)

0.08 200

0.06 150

0.04 100

0.02 50

0 0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 - 40 - 20 0 20 40 60 80 100
VIN (V) Temperature (°C)

Fig. 4 - Quiescent Current vs. Input Voltage Fig. 7 - Off Switch Current vs. Temperature

350 550

500 for SC70-6 package

300
450 IL = 1.2 A
ISD(OFF) - Off Switch Current (nA)

RDS - On-Resistance (mΩ)

250 400
IL = 500 mA
350
200
300
150
250

100 200

150 IL = 100 mA
50
100

0 50
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V) VIN (V)

Fig. 5 - Off Switch Current vs. Input Voltage Fig. 8 - RDS(on) vs. VIN for SC-70-6 Package

10 550

500 for TDFN4 package

450
IQ - Quiescent Current (nA)

1
RDS - On-Resistance (mΩ)

400 IL = 1.2 A

350

0.1 300
VIN = 5 V IL = 500 mA
250

200
0.01
150
VIN = 3 V IL = 100 mA
100

0.001 50
- 40 - 20 0 20 40 60 80 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (°C) VIN (V)

Fig. 6 - Quiescent Current vs. Temperature Fig. 9 - RDS(on) vs. Input Voltage

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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)

1000 600

VOUT = 5.5 V
VIN = 0 V
IRB - Reverse Blocking Current (nA)

500 VIN = 0 V

IRB - Reverse Blocking Current (nA)

100

400
10

300

1
200

0.1
100

0.01 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 - 40 - 20 0 20 40 60 80 100
VOUT (V) Temperature (°C)

Fig. 10 - Reverse Blocking Current vs. VOUT Fig. 13 - Reverse Blocking Current vs. Temperature

220 1.6

210 ILOAD = 500 mA

for SC70-6 package 1.4
200
On/Off Threshold Voltage (V)
RDS - On-Resistance (mΩ)

190
1.2
180
VIH
170 1.0
VIN = 3 V VIL
160 VIN = 5 V
0.8
150

140
0.6
130

120 0.4
- 40 - 20 0 20 40 60 80 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Temperature (°C) VIN (V)

Fig. 11 - RDS(on) vs. Temperature Fig. 14 - On / Off Threshold vs. Input Voltage

Axis Title
180 40 000 10000
ILOAD = 500 mA
for TDFN4 package
35 000
160
RDS - On-Resistance (mΩ)

30 000 VEN = 5 V
IEN Current (pA)

140 1000
VIN = 3 V 25 000
1 t li

120 20 000

15 000
100 VEN = 3.6 V 100
VIN = 5 V
10,000
80
5000

60 0 10
- 40 - 20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C)
Fig. 12 - RDS(on) vs. Temperature Fig. 15 - IEN Current vs. Temperature

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TYPICAL WAVEFORMS

Fig. 16 - Switching (VIN = 3 V) Fig. 18 - Turn-Off (VIN = 3 V)

Fig. 17 - Switching (VIN = 5 V) Fig. 19 - Turn-Off (VIN = 5 V)

BLOCK DIAGRAM

Reverse
Blocking
IN OUT

Turn-On
Level
Slew Rate
Shift
Control

ON/OFF

GND

Fig. 20 - Functional Block Diagram

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PCB LAYOUT

Fig. 21 - Top, TDFN4 1.2 mm x 1.6 mm PCB Layout Fig. 22 - Bottom, TDFN4 1.2 mm x 1.6 mm PCB Layout

DETAILED DESCRIPTION Protection Against Reverse Voltage Condition

The SiP32431 and SiP32432 are p-channel MOSFET power The SiP32431 and SiP32432 contain a body snatcher that
switches designed for high-side slew rate controlled normally connects the body to the source (IN) when the
load-switching applications. Once turned on, the slew-rate device is enabled. In case where the device is disabled but
control circuitry is activated and current is ramped in a linear the VOUT is higher than the VIN, the n-type body is switched
fashion until it reaches the level required for the output load to out, reverse bias the body diode to prevent the current
condition. This is accomplished by first elevating the gate from going back to the input.
voltage of the MOSFET up to its threshold voltage and then Thermal Considerations
by linearly increasing the gate voltage until the MOSFET The physical limitations of the layout and assembly of the
becomes fully enhanced. At this point, the gate voltage is device limit the maximum current levels as stated in the
then quickly increased to the full input voltage to reduce Absolute Maximum Ratings table. However, another limiting
RDS(on) of the MOSFET switch and minimize any associated characteristic for the safe operating load current is the
power losses. thermal power dissipation of the package. To obtain the
highest power dissipation, the power pad of the TDFN4
APPLICATION INFORMATION package should be connected to a heat sink on the printed
Input Capacitor circuit board.
While a bypass capacitor on the input is not required, a 1 μF The maximum power dissipation in any application is
or larger capacitor for CIN is recommended in almost all dependent on the maximum junction temperature,
applications. The bypass capacitor should be placed as TJ (max.) = 125 °C, the junction-to-ambient thermal resistance
physically close as possible to the input pin to be effective for the TDFN4 1.2 mm x 1.6 mm package, J-A = 170 °C/W,
in minimizing transients on the input. Ceramic capacitors are and the ambient temperature, TA, which may be
recommended over tantalum because of their ability to formulaically expressed as:
withstand input current surges from low impedance sources
such as batteries in portable devices. T J (max.) – T A 125 – T A
P (max.) = --------------------------------- = ----------------------
Output Capacitor J – A 170
A 0.1 μF capacitor or larger across VOUT and GND is It then follows that, assuming an ambient temperature of
recommended to insure proper slew operation. COUT may
70 °C, the maximum power dissipation will be limited to
be increased without limit to accommodate any load about 324 mW.
transient condition with only minimal affect on the SiP32431
and SiP32432 turn on slew rate time. There are no ESR or So long as the load current is below the absolute maximum
capacitor type requirement. limits, the maximum continuous switch current becomes a
function two things: the package power dissipation and the
Enable RDS(on) at the ambient temperature.
The on / off pin is compatible with both TTL and CMOS logic
voltage levels. As an example let us calculate the worst case maximum
load current at TA = 70 °C. The worst case RDS(on) at 25 °C

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occurs at an input voltage of 1.5 V and is equal to 520 m. 
The RDS(on) at 70 °C can be extrapolated from this data using 
the following formula 
RDS(on) (at 70 °C) = RDS(on) (at 25 °C) x (1 + TC x T) 

Where TC is 3300 ppm/°C. Continuing with the calculation

we have

RDS(on) (at 70 °C) = 520 m x (1 + 0.0033 x (70 °C - 25 °C)) = 
597 m 
The maximum current limit is then determined by 

P (max.)
I LOAD (max.)  ---------------------- 
R DS  on  

which in case is 0.74 A. Under the stated input voltage

condition, if the 0.74 A current limit is exceeded the internal

die temperature will rise and eventually, possibly damage
the device.


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PRODUCT SUMMARY
Part number SiP32431DN SiP32431DR SiP32432DN SiP32432DR
1.5 V to 5.5 V, 105 1.5 V to 5.5 V, 147 1.5 V to 5.5 V, 105 1.5 V to 5.5 V, 147
m, 10 pA IQ, m, 10 pA IQ, m, 10 pA IQ, m, 10 pA IQ,
Description bidirectional off bidirectional off bidirectional off bidirectional off
isolation, EN active isolation, EN active isolation, EN active isolation, EN active
high high low low
Configuration Single Single Single Single
Slew rate time (μs) 140 140 140 140
On delay time (μs) 20 20 20 20
Input voltage min. (V) 1.5 1.5 1.5 1.5
Input voltage max. (V) 5.5 5.5 5.5 5.5
On-resistance at input voltage min. (m) 350 395 350 395
On-resistance at input voltage max. (m) 105 147 105 147
Quiescent current at input voltage min. (μA) 0.000002 0.000002 0.000002 0.000002
Quiescent current at input voltage max. (μA) 0.00004 0.00004 0.00004 0.00004
Output discharge (yes / no) No No No No
Reverse blocking (yes / no) Yes Yes Yes Yes
Continuous current (A) 1.4 1.4 1.4 1.4
Package type TDFN4 SC-70-6 TDFN4 SC-70-6
Package size (W, L, H) (mm) 1.2 x 1.6 x 0.5 2.0 x 2.0 x 0.5 1.2 x 1.6 x 0.5 2.0 x 2.0 x 0.5
Status code 2 2 2 2
Product type Slew rate Slew rate Slew rate Slew rate
Computers, Computers, Computers, Computers,
consumer, industrial, consumer, industrial, consumer, industrial, consumer, industrial,
Applications
healthcare, healthcare, healthcare, healthcare,
networking, portable networking, portable networking, portable networking, portable
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?66597.

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 Package Information
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TDFN4 1.2 x 1.6 Case Outline

D
D2

b
4 3
Pin #1 ID
3 4 (Optional)

E2
E

K
2 1

L
1 2
e
Index Area
(D/2 x E/2)

Top View Bottom View

A3

A1

Side View

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.45 0.55 0.60 0.017 0.022 0.024
A1 0.00 - 0.05 0.00 - 0.002
A3 0.15 REF. or 0.127 REF. (1) 0.006 or 0.005 (1)

b 0.20 0.25 0.30 0.008 0.010 0.012

D 1.15 1.20 1.25 0.045 0.047 0.049
D2 0.81 0.86 0.91 0.032 0.034 0.036
e 0.50 BSC 0.020
E 1.55 1.60 1.65 0.061 0.063 0.065
E2 0.45 0.50 0.55 0.018 0.020 0.022
K 0.25 typ. 0.010 typ.
L 0.25 0.30 0.35 0.010 0.012 0.014
ECN: T16-0143-Rev. C, 18-Apr-16
DWG: 5995
Note
(1) The dimension depends on the leadframe that assembly house used.

Revision: 18-Apr-16 1 Document Number: 65734

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 Package Information
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SC-70: 3/4/5/6-LEADS (PIC ONLY)

D 0.15 (0.006) C

e1
A A
D
N5 N4 N3

E/2
E1/2
E
E/1

0.15 (0.006) C
Pin 1

N1 N2

e B

See Detail A
C 0.10 (0.004) M C A B b

U1

A2 A SEATING
PLANE

A1 C
0.10 (0.004) C

H
(b)
b1 0.15 (0.0059)
GAGE PLANE

c1 c
Base Metal U
L
SECTIION A-A DETAIL A

Pin LEAD COUNT NOTES:

Code 3 4 5 6 1. Dimensioning and tolerancing per ANSI Y14.5M-1994.

N1 − − 2 2 2. Controlling dimensions: millimeters converted to inch dimensions are

2 2 3 3 not necessarily exact.
N2
N3 − 3 4 4 3. Dimension “D” does not include mold flash, protrusion or gate burr.
Mold flash, protrusion or gate burr shall not exceed 0.15 mm
N4 3 − − 5 (0.006 inch) per side.
N5 − 4 5 6
4. The package top shall be smaller than the package bottom.
Dimension “D” and “E1” are determined at the outer most extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate burrs
and interlead flash, but including any mismatch between the top and
bottom of the plastic body.

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MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A 0.80 − 1.10 0.031 − 0.043

A1 0.00 − 0.10 0.000 − 0.004

A2 0.80 0.90 1.00 0.031 0.035 0.040

b 0.15 − 0.30 0.006 − 0.012

b1 0.15 0.20 0.25 0.006 0.008 0.010

c 0.08 − 0.25 0.003 − 0.010

c1 0.08 0.13 0.20 0.003 0.005 0.008

D 1.90 2.10 2.15 0.074 0.082 0.084

E 2.00 2.10 2.20 0.078 0.082 0.086

E1 1.15 1.25 1.35 0.045 0.050 0.055

e 0.65 BSC 0.0255 BSC

e1 1.30 BSC 0.0512 BSC

L 0.26 0.36 0.46 0.010 0.014 0.018

U 0_ − 8_ 0_ − 8_

U1 4_ 10_ 4_ 10_
ECN: S-42145—Rev. A, 22-Nov-04
DWG: 5941

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2 19-Nov-04
 PAD Pattern
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR TDFN4 1.2 x 1.6

0.86
0.50
0.30

0.55
4 3

0.20

2.0
0.50
0.20
0.55
1 2

Recommended Minimum Pads

Dimensions in mm

Document Number: 66558 www.vishay.com

Revision: 05-Mar-10 1
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Revision: 01-Jan-2023 1 Document Number: 91000