Viper31: Energy Saving Offline High Voltage Converter
Viper31: Energy Saving Offline High Voltage Converter
Viper31: Energy Saving Offline High Voltage Converter
Datasheet
Features
• 800 V avalanche-rugged power MOSFET to cover ultra-wide VAC input range
• Embedded HV startup and sense FET
• Current mode PWM controller
• Drain current limit protection (OCP):
– 710 mA (VIPER317)
~ AC DIN RIN
– 850 mA (VIPER318)
OVP
VCC DRAIN
VIPER31
– 990 mA (VIPER319)
FB
CONTROL
• Wide supply voltage range: 4.5 V to 30 V
COMP UVP GND
CIN
DAUX – < 20 mW @ 230 VAC in no-load;
R1
C1
R2 C2 D2
– < 430 mW @ 230 VAC, 25 0mW output load
C3
LOUT
VOUT
• Jittered switching frequency reduces the EMI filter cost:
– 30 kHz ± 7% (type X)
D1 COUT
GND GND
– 60 kHz ± 7% (type L)
– 132 kHz ±7% (type H)
• Embedded E/A with 1.2 V reference
• Built-in soft-start for improved system reliability
• Protections with automatic restart:
– overload/short-circuit (OLP)
– thermal shutdown
– overvoltage
Product status link
• Protections without automatic restart:
VIPER31 – pulse-skip protection to avoid flux runaway
– undervoltage/disable
Product label
– max. duty cycle
Application
• Low power SMPS for home appliances, home automation, industrial,
consumers, lighting
• Low power adapters
Description
The VIPER31 device is a high-voltage converter that smartly integrates an 800
V avalanche rugged power MOSFET with PWM current-mode control. The 800 V
breakdown allows extended input voltage range to be applied, as well as to reduce
the size of the DRAIN snubber circuit. The IC can meet the most stringent energy-
saving standards as it has very low consumption and operates in pulse frequency
modulation at light load. Overvoltage and undervoltage protections with separate and
settable intervention thresholds are available at OVP and UVP pins respectively. UVP
can also be used as a disabling input for the entire SMPS, with ultra-low residual
input power consumption. Integrated HV startup, sense FET, error amplifier and
oscillator with frequency jitter allow a complete application to be designed with a
minimum component count. Flyback, buck and buck boost topologies are supported.
1 Pin setting
GND DRAIN
N.C. DRAIN
VCC DRAIN
N. A. DRAIN
UVP N. C.
OVP N. C.
FB N. C.
COMP N. C.
Pin
Name Function
number
Ground and MOSFET source. Connection of both the source of the internal MOSFET and the return of
1 GND the bias current of the device. All of the groundings of bias components must be tied to a trace going to
this pin and kept separate from the pulsed current return.
2 N. C. Not connected. When designing the PCB, this pin can be soldered to GND.
Controller Supply. An external storage capacitor has to be connected across this pin and GND. The
pin, internally connected to the high-voltage current source, provides the VCC capacitor charging current
3 VCC
at startup. A small bypass capacitor (0.1 μF typ.) in parallel, placed as close as possible to the IC, is also
recommended, for noise filtering purposes.
Not available for user. This pin is mechanically connected to the controller die pad of the frame. In order
4 N.A.
to improve noise immunity, it is highly recommended to connect it to GND.
Undervoltage Protection. If VUVP falls below the internal threshold VUVP_th (0.4 V typ.) for more than
tUVP_DEB time (30 ms, typ.), the IC is disabled, and its consumption reduced to ultra-low values. When
VUVP rises above VUVP_th, the device waits for a tUVP_REST time interval (30 ms, typ.) then resumes
5 UVP
switching. The pin can be used to realize an input undervoltage protection or as a disabling input for the
entire SMPS, with ultra-low residual input power consumption. If the feature is not required, the pin must
be left open, which excludes the function.
Overvoltage protection. If VOVP exceeds the internal threshold VOVP_th (4 V typ.) for more than
tOVP_DEB time (250 μsec, typ.), the PWM is disabled in auto-restart for tOVP_REST (500 msec, typ.) until
the OVP condition is removed, after that it restarts switching with soft-start phase. OVP pin can be
6 OVP used to realize an input overvoltage protection (or, in non-isolated topologies, an output overvoltage
protection).
If the feature is not required, the pin must be connected to GND, which excludes the function.
Direct feedback. It is the inverting input of the internal transconductance E/A, internally referenced to
1.2 V with respect to GND. In non-isolated converter, the output voltage information is directly fed into the
7 FB
pin through a voltage divider. In primary regulation, the FB voltage divider is connected to the VCC. The
E/A is disabled if FB is connected to GND pin.
Pin
Name Function
number
Compensation. This is the output of the internal E/A. A compensation network is placed between
this pin and GND to achieve stability and good dynamic performance of the control loop. In case of
8 COMP
secondary feedback, the internal E/A must be disabled and the COMP directly driven by the optocoupler
to control the DRAIN peak current setpoint.
9 to 12 N.C. Not connected. These pins must be left floating in order to get a safe clearance distance.
MOSFET drain. The internal high-voltage current source sources current from these pins to charge
the VCC capacitor at startup. The pins are mechanically connected to the internal metal PAD of the
13 to 16 DRAIN
MOSFET in order to facilitate heat dissipation. On the PCB, some copper areas under these pins
decreases the total junction-to-ambient thermal resistance thus facilitating the power dissipation.
Internally
VOVP OVP voltage -0.3 V
limited(3)
Internally
VUVP UVP voltage -0.3 V
limited (3)
VFB FB voltage -0.3 5 (4) V
Internally
VCOMP COMP voltage -0.3 V
limited (3)
PTOT Power Dissipation @ Tamb < 50°C 1(5) W
1. stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability
3. by internal clamp between 4.75 V and 5.25 V or Vcc + 0.6 V, whichever is lower
4. the AMR value is intended when VCC ≥ 5 V, otherwise the value VCC + 0.3 V has to be considered.
5. when mounted on a standard single side FR4 board with 100 mm² (0.155² inch) of Cu (35 μm thick)
Max. value
Symbol Parameter Unit
SO16N
1. when mounted on a standard single side FR4 board with minimum copper area
2. when mounted on a standard single side FR4 board with 100mm² (0.155² inch) of Cu (35 μm thick)
RthJA/(RthJA@ A = 100mm2)
1.500
1.375
1.250
1.125
1.000
0.875
0.750
0 25 50 75 100 125 150 175 200 225
A (mm2)
IAS = IAR,
ICH1 VCC charging current at startup VDRAIN = 100V, VCC ≤ 1V 0.5 1 1.5
Note: 1. Current supplied only during the main MOSFET OFF time.
2. Parameter assured by design and characterization.
E/A
VFB_REF Reference voltage 1.175 1.2 1.225 V
VCOMP=1.5 V,
GM Trans conductance 400 550 700 µA/V
VFB >VFBREF
VCOMP=1.5 V,
ICOMP1 Max. source current 75 100 125 µA
VFB =0.5 V
VFB=2 V,
ICOMP2 Max. sink current 75 100 125 µA
VCOMP=1.5 V
VCOMP=2.7 V,
RCOMP(DYN) Dynamic resistance 13 15 17 kΩ
VFB =GND
VIPER317L 30.2
VIPER317H 66.5
VIPER318X 21.7
Power coefficient VIPER318L 43.4
I2f -10% +10% A2·kHz
2
IDLIM_TYP x FOSC_TYP VIPER318H 95.4
VIPER319X 29.4
VIPER319L 58.8
VIPER319H 129.4
TJ=25°C, VCOMP=VCOMPL(2)
IDlim_PFM Drain current limitation at light load 100 130 160 mA
VIPER318*(1)
TJ=25°C, VCOMP=VCOMPL(2)
120 150 180
VIPER319*(1)
VCC=9 V,
tON_MIN Minimum turn-on time VCOMP=1 V, 250 300 350 ns
VFB=VFB_REF
UVP
VCC =9 V,
VUVP_th UVP threshold VCOMP=1 V, 0.38 0.4 0.42 V
VFB=VFB_REF
OVP
VCC=9 V,
VOVP_th Overvoltage protection threshold VCOMP=1 V, 3.85 4 4.15 V
VFB=VFB_REF
FOSC MIN Min. switching frequency TJ= 25ºC (3) 13.5 15 16.5 kHz
1. Measured at Vin = 100 Vdc in Flyback topology, with 1.5 mH transformer primary inductance
2. See Section 4.10 Pulse frequency modulation
3. See Section 4.7 Pulse skipping
4. Parameter assured by design and characterization.
IDLIM/(IDLIM@25°C) FOSC/(FOSC@25°C)
1.2 1.1
1.1 1.05
1 1
0.9 0.95
0.8 0.9
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj [°C] Tj [°C]
VHV_START/(VHV_START@25°C) VFB_REF/(VFB_REF@25°C)
1.2 1.05
1.1 1.025
1 1
0.9 0.975
0.8 0.95
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj [°C] Tj [°C]
Iq/(Iq@25°C) ICC/(ICC@25°C)
1.1 1.2
1.05 1.1
1 1
0.95 0.9
0.9 0.8
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj [°C] Tj [°C]
ICH1/(ICH1@25°C) ICH2/(ICH2@25°C)
1.5 1.2
1.3
1.1
1.1
0.9
0.9
0.7
0.5 0.8
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj [°C] Tj [°C]
Figure 11. ICH1 vs. VDRAIN Figure 12. ICH2 vs. VDRAIN
1.05 1.05
1 1
0.95 0.95
0.9 0.9
0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 800
VDRAIN [V] VDRAIN [V]
GM/(GM@25°C) ICOMP/(ICOMP@25°C)
1.2 1.1
1.1 1.05
1 1
0.9 0.95
0.8 0.9
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj [°C] Tj [°C]
RDS(on)/(RDS(on)@25°C)
2.50
2.00
1.50
1.00
0.5 T = 25°C
0.50
0.00
-50 -25 0 25 50 75 100 125 150
Tj [°C] 0
0 50 100 150 200 250 300 350 400
IDRAIN [mA]
1000
100
10
1
0 1 10 100 1000
VDS [V]
-40°C
4.4
1.08
4.0
3.6
1.04
3.2 25°C
2.8
1
2.4
ID = 1 mA 2.0
0.96 125°C
1.6
1.2
0.92
0.8
0.4
0.88
0.0
-50 0 50 100 150
0.0 4.0 8.0 12.0 16.0 VDS20.0
[V]
TJ [°C]
Single pulse,
ID = 1A, VDD = 50 V
3
tp = 1 ms
RDS(on) limit 2
tp = 10 ms
0.1
tp = 100 ms 1
tp = 1 ms
0.01
0.1 1 10 100 1000 V10000
DS [V] 0
-50 0 50 Tj [°C] 100 150
4 General description
JITTERED THERMAL
SOFT START OSCILLATOR DIODE
(OTP)
IDLIM ref TURN ON
+ LEB LOGIC
E/A - OCP S
Q
FB -
+ R
+
-
- PWM OCP tOVL filter
VFB_REF PROTECTION
IC_DIS_SET IC_DIS_RESET
+ LOGIC
UVLO VCC
VCC_clamp tRESTART
tUVP_DEB filter OVP LOGIC
tOVP_DEB filter tOVP_REST
+
-
VUVP_th + +
VOVP_th
- - RSENSE
Adapter (1) Open Frame (2) Adapter (1) Open Frame (2)
27 W 31 W 16 W 19 W
Figure 24. Typical deliverable output power vs. TAMB (Vin: 85-265VAC)
PHV(VIN) = VIN2/RG
At nominal input voltage (230 VAC), typical and worst-case consumptions are 2.4 mW and 3.0 mW respectively
(corresponding to RG_typ = 45 Mohm and RG_min = 36 Mohm). This means that, with a careful design, the
overall no-load input power consumption of the application can be maintained very low (typically, below 10 mW
@230 VAC)
Power-off: when the IC is disconnected from the mains, or there is a mains interruption, for some time the
converter keeps on working, powered by the energy stored in the input bulk capacitor. When it is discharged
below a critical value, the converter is no longer able to keep the output voltage regulated. During the power
down, when the DRAIN voltage becomes too low, the HV current source remains off and the IC is stopped as
soon as VCC drops below the UVLO threshold, VCcoff.
VHV_START
Power-on:
HV current source enabled
t
VDRAIN
HV current source is
VCC disabled here
HV current source is no
VCCon more activated because
of too low VDRAIN
VCSon UVLO
ICH2
VCCoff
ICH1 1V t
VOUT
time
VCOMP
VCOMPH
time
VOUT
VOUT
time
4.6 Oscillator
The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by
approximately ±7%·FOSC at 200 Hz rate. The purpose of the jittering is to get a spread-spectrum action that
distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having
the same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially
when measured with the average detection method or, which is the same, to pass the EMI tests with an input
filter of smaller size with respect to the one that should be needed in absence of jittering feature. Three switching
frequency options, FOSC, are available: 30 kHz (X type), 60 kHz (L type) and 132 kHz (H type).
time
IDRAIN
without pulse skipping
with pulse skipping
IDLIM
time
skipped cycles
This kind of operation, together with the extremely low IC quiescent current, allows very low input power
consumption in no-load and light load, while the low DRAIN peak current value, IDLIM_PFM, prevents any
audible noise which could arise from low switching frequency values. When the output load is increased, VCOMP
increases and PFM is exited. VCOMP reaches its maximum at VCOMPH, corresponding to the DRAIN current
limitation (IDLIM).
VCCon
VCSon
IDRAIN
time
IDLIM
tSS tSS
If VUVP falls below VUVP_th, the DEB counter is incremented. If VUVP increases above VUVP_th before uvp_eoc
is reached, the counter is decremented. If the count goes back down to zero, a disturbance on the UVP pin is
assumed and there is no consequence on the IC behavior.
If VUVP stays below VUVP_th until the counter reaches deb_eoc: the device is disabled; most of the internal blocks
are turned off and the internal consumption is reduced to Iq_DIS; VCC is maintained between VCson and VCcon
by the periodical activation of the internal HV-current source; the DEB counter is reset. Of course, if during the
count-up VUVP exceeds VUVP_th for some time, the DEB counter is decremented during that time and the IC
disable is delayed accordingly.
With IC disabled: if VUVP rises above VUVP_th, the REST counter is incremented, and when it reaches rest_eoc
(corresponding to tUVP_REST), the IC resumes switching. Of course, if during the count-up, VUVP falls below
VUVP_th for some time, the REST counter is decremented during that time and the IC re-enabling is delayed
accordingly.
VUVP
VUVP_th
VDD
VCCon
VCSon
DEB counter
deb_eoc
rest_eoc
tUVP_REST
IDRAIN IC re-enabled
IC disabled
Restart
delay
An input undervoltage protection can be easily realized connecting the rectified mains to UVP pin through a
voltage divider, as shown in Figure 30. Connection for input undervoltage protection/disable (isolated or non-
isolated topologies).
Figure 30. Connection for input undervoltage protection/disable (isolated or non-isolated topologies)
~ AC DIN
RH
VIPER31
VCC DRAIN
OVP
CIN
Cs CONTROL
FB
R2
RL C1
GND C2
If UVP function is not required, the UVP pin must be left floating. In this case, noise immunity of the pin is
guaranteed by the internal pull-up IUVP_pull-up (1 uA, typ.) present in the UVP block.
If UVP function is required, RH value can be set arbitrarily, but some Mohms at least are recommended in order to
minimize the power consumption of the UVP network. Then, if Vin_UVP is the desired input undervoltage threshold,
the value of RL can be found from the following formula:
Equation 2
(2)
V
UVP_th
RL = V
in_UVP − VUVP_th + I
RH UVP_pull − up
Equation 3
(3)
2
PUVP Vin = RHVin
+ RL
Thanks to the ultra-low consumption, the UVP pin can be used as an input to disable the SMPS from external,
reaching the lowest input power consumption while the SMPS is still connected to the AC mains but not delivering
power to its output.
The purpose of the UVP debounce time tUVP_DEB is also to guarantee some hold-up in case of a missing cycle of
the input line, as illustrated in Figure 31. Hold-up in case of input line missing cycles.
VUVP
VUVP_th
tUVP_DEB tUVP_DEB
IC disabled
IDRAIN
here
VCCon
VDD
VCSon
OVP count
ovp_eoc
An input overvoltage protection can be easily realized connecting the rectified mains to OVP pin through a voltage
divider, as shown in Figure 33. Connection for input overvoltage protection (iso/non-iso topologies).
In case of non-isolated topologies, with the same principle an output overvoltage protection can be implemented,
as shown in Figure 34. Connection for output overvoltage protection (non-iso topologies).
If the OVP feature is not required, OVP pin must be connected to GND, which excludes the function.
If the OVP feature is required, RH value can be set arbitrarily, but some Mohms at least are recommended in
order to minimize the power consumption of the OVP network. Then, if Vin/out_OVP is the desired input/output
overvoltage threshold, the value of RL can be calculated from the following formula:
Equation 4
(4)
RH
RL = V
in/out_OVP
VOVP_tℎ − 1
The power consumption of the OVP network at given Vin is expressed as:
Equation 5
(5)
2
POVP Vin = RHVin
+ RL
VOUT 2
POVP VOUT = RH + RL
~ AC DIN
RH
VIPER31
VCC DRAIN
OVP
CIN
Cs CONTROL
FB
R2
RL C1
GND C2
COUT
from VAUX or VOUT
VIPER31 GND
VCC DRAIN
OVP
Rfb1 RH
CONTROL
FB
Cs
COMP UVP GND
R2
C1 Rfb2 RL
C2
Figure 35. Connection for input and output overvoltage protections (iso/non-iso topologies)
~ AC DIN
VIPER31
VCC DRAIN
OVP
CIN
Cs CONTROL
FB
RM
COMP UVP GND
R2
RL C1
GND C2
Equation 8
(8)
Vin_OVP = VOVP tℎ − RH + RH
RM + RL · RL · IUVP_pull − up · RHRM
+ RM + RL
+ RL
Considering that the value of RH is much higher than the values of RM and RL (Mohms vs. kohms), equations 7
and 8 can be approximated into Eq. 7.a) and Eq. 8.a) respectively:
Equation 7.a
(7.a)
VUVP
tℎ
Vin_UVP RL − IUVP_pull − up · RH + RL · IUVP_pull − up
Equation 8.a
(8.a)
Selecting arbitrarily the RH value, Equation 7.a) can be solved for RL:
Equation 9
(9)
2
Vin_UVP + IUVP_pull − up · RH − Vin_UVP + IUVP_pull − up · RH − 4 · VUVP · IUVP_pull − up · RH
tℎ
RL = 2 · IUVP_pull − up
(10)
RM = VOVP tℎ − RL · IUVP_pull − up · V RH − RL
in_OVP
The power consumption of the UVP-OVP network at given Vin is expressed as:
Equation 11
(11)
in V2
PUVP_OVP Vin = RH + RM + RL
As an example, if Vin_UVP and Vin_OVP design values are 50 Vdc and 450 Vdc respectively, and RH is set to 6
Mohm: from Equations 9 and 10 we have RL = 43 kohm, and RM = 60 kohm respectively, while from Equation 11
the power consumption of the network at 230 Vac is about 17 mW.
TSD
VCC
VCCon
VCSon
t
tRESTART tRESTART
5 Application information
~ AC
Din Rin Dout Vout
T
Ccl
Cout
Cin
Rcl
GND
VIPER31
VCC DRAIN
OVP
CONTROL
RH
FB
Cs COMP UVP GND
R2 RL
C1
C2
Cin Ccl
Cout
Rcl
Raux
Daux GND2
VIPER31 R3
VCC DRAIN
RH
OVP OPTO
CONTROL R4
FB
Cs
COMP UVP GND
C2
OPTO
C1
RL
GND1
Cout
Ccl
Rcl
GND2
Daux
VIPER31
RH VCC DRAIN
Cin
OVP
Cs
CONTROL
FB
RL
C2
C1
R2
GND1
Daux
VIPER31
VCC DRAIN
RH
OVP
Cs C3
CONTROL
FB
D2
C1
Cin
R2 C2
Lout Vout
D1
Cout
GND GND
Daux
VIPER31
VCC DRAIN
RH
OVP Cs
CONTROL
FB C3
D2
C1
D1 Vout
R2 C2
Cout
Lout
GND GND
30
PIN [mW]
20
10
50 100 150 200 250 300
VIN [VAC]
400
POUT = 250mW
350
300
PIN [mW]
250
200
150
POUT = 50mW
100
POUT = 25mW
50
0
50 100 150 200 250 300
VIN [VAC]
CIN CCL
COUT
RCL
DAUX
GROUND
Cs
ROPTO
OPTO RH
RC CC
VIPER31
CONTROL
OPTO RL
C1
CIN
VIPER31
CONTROL
Cc
DAUX
Cs RH
C1
RL D1
LOUT VOUT
COUT
DOUT
GROUND
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
mm
Dim.
Min. Typ. Max.
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1
7 Order code
VIPER318XDTR 850 mA
30 kHz ± 7%
VIPER319XDTR 990 mA
VIPER317LDTR 710 mA
VIPER318LDTR 850 mA 60 kHz ± 7%
SO16N tape and reel
VIPER319LDTR 990 mA
VIPER317HDTR 710 mA
VIPER318HDTR 850 mA 132 kHz ± 7%
VIPER319HDTR 990 mA
Revision history
Contents
1 Pin setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Avalanche characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 6. Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 7. Controller section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 8. Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Power supply efficiency, VOUT = 15 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. SO16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of figures
Figure 1. Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Rth_JA versus copper area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. IDLIM vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. FOSC vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. VHV_START vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. VFB_REF vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Quiescent Current Iq vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Operating current ICC vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. ICH1 vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. ICH2 vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11. ICH1 vs. VDRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12. ICH2 vs. VDRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 13. GM vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 14. ICOMP vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 15. RDSON vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 16. RDSON vs. IDRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 17. Static drain-source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 18. Power MOSFET COSS vs. VDS @ VGS=0, f=1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 19. VBVDSS vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 20. Output characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 21. SOA SO16N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 22. Maximum avalanche energy vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 23. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 24. Typical deliverable output power vs. TAMB (Vin: 85-265VAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 25. Power ON and power OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Soft startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 27. Pulse skipping during startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28. Overload protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 29. UVP timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 30. Connection for input undervoltage protection/disable (isolated or non-isolated topologies) . . . . . . . . . . . . . . . 20
Figure 31. Hold-up in case of input line missing cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 32. OVP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 33. Connection for input overvoltage protection (iso/non-iso topologies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 34. Connection for output overvoltage protection (non-iso topologies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 35. Connection for input and output overvoltage protections (iso/non-iso topologies). . . . . . . . . . . . . . . . . . . . . . 24
Figure 36. Thermal shutdown timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 37. Flyback converter (non-isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 38. Flyback converter (isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 39. Flyback converter (primary regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 40. Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 41. Buck-boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 42. PIN versus VIN in no-load, VOUT = 15V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 43. PIN versus VIN in light-load, VOUT = 15V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 44. Recommended routing for flyback converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 45. Recommended routing for buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 46. SO16N package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32