CD74HC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS512 JULY 2003

D D D D D D D D

Qualification in Accordance With AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Buffered Inputs Typical Propagation Delay 7 ns at VCC = 5 V, CL = 15 pF, TA = 25C Fanout (Over Temperature Range) Standard Outputs . . . 10 LSTTL Loads Bus Driver Outputs . . . 15 LSTTL Loads Extended Temperature Performance of 40C to 125C

D D D D D

Balanced Propagation Delay and Transition Times Significant Power Reduction, Compared to LSTTL Logic ICs 2-V to 6-V VCC Operation High Noise Immunity NIL or NIH = 30% of VCC at VCC = 5 V CMOS Input Compatibility, Il 1 A at VOL, VOH
M PACKAGE (TOP VIEW)

Contact factory for details. Q100 qualification data available on request.

1A 1B 1Y 2A 2B 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

VCC 4B 4A 4Y 3B 3A 3Y

description/ordering information
The CD74HC08 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates, with the low power consumption of standard CMOS integrated circuits. The device can drive 10 LSTTL loads. ORDERING INFORMATION
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING

40C to 125C SOIC M Tape and reel CD74HC08QM96Q1 HC08Q Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y H L L

logic diagram (positive logic)

A B Y

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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CD74HC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS512 JULY 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI < 0.5 V or VI > VCC + 0.5 V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0.5 V or VO > VCC + 0.5 V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO > 0.5 or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Lead temperature (during soldering): At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 2 V VCC = 4.5 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 ns V V V V NOM 5 MAX 6 UNIT V

VCC = 6 V 400 TA Operating free-air temperature 40 125 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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CD74HC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS512 JULY 2003

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IO (mA) 0.02 CMOS loads VOH VI = VIH or VIL TTL loads 0.02 0.02 4 5.2 0.02 CMOS loads VOL VI = VIH or VIL TTL loads II ICC Ci VI = VCC or GND VI = VCC or GND 0.02 0.02 4 5.2 0 VCC 2V 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V MIN 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 2 10 TA = 25C TYP MAX CD74HC08-Q1 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1 40 10 A A pF V V MAX UNIT

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) CONDITIONS VCC 2V tpd d A or B Y CL = 50 pF CL = 15 pF tt Y CL = 50 pF 4.5 V 6V 5V 2V 4.5 V 6V 7 75 15 13 110 22 19 ns MIN TA = 25C TYP MAX 90 18 15 CD74HC08-Q1 MIN MAX 135 27 23 ns UNIT

operating characteristics, TA = 25C, VCC = 5V

PARAMETER Cpd Power dissipation capacitance per gate (see Note 4) NOTE 4: Cpd is used to determine the dynamic power consumption, per gate. PD = VCC2 fI (Cpd + CL) fI = input frequency CL = output load capacitance VCC = supply voltage TEST CONDITIONS No load TYP 37 UNIT pF

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CD74HC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS512 JULY 2003

PARAMETER MEASUREMENT INFORMATION

From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output Input VCC 50% tPLH 50% 10% tPHL Out-of-Phase Output 90% 50% 10% tf 90% tr Input 50% 10% 90% 90% VCC 50% 10% 0 V tf tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL

LOAD CIRCUIT

tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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PACKAGE OPTION ADDENDUM

www.ti.com

25-Feb-2005

PACKAGING INFORMATION
Orderable Device CD74HC08QM96Q1
(1)

Status (1) ACTIVE

Package Type SOIC

Package Drawing D

Pins Package Eco Plan (2) Qty 14 2500 None

Lead/Ball Finish CU NIPDAU

MSL Peak Temp (3) Level-1-235C-UNLIM

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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