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    Design Rule Check: By:-Chandan ROLL NO. 15/914 B.SC (Hons.) ELECTRONICS Science

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    Chandan Kumar
    Design rule checking (DRC) determines if a chip layout satisfies recommended design rules. It checks for minimum widths, spacings, and enclosures. The main objective of DRC is to achieve high yield and reliability by verifying a design meets process constraints. DRC software takes the layout and design rules to produce a report of any violations for the designer to address. Example DRC checks for integrated circuits include active to active spacing, well to well spacing, minimum transistor dimensions, and metal density rules.

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    Design Rule Check: By:-Chandan ROLL NO. 15/914 B.SC (Hons.) ELECTRONICS Science

    Uploaded by

    Chandan Kumar
    311 views9 pages
    Design rule checking (DRC) determines if a chip layout satisfies recommended design rules. It checks for minimum widths, spacings, and enclosures. The main objective of DRC is to achieve high yield and reliability by verifying a design meets process constraints. DRC software takes the layout and design rules to produce a report of any violations for the designer to address. Example DRC checks for integrated circuits include active to active spacing, well to well spacing, minimum transistor dimensions, and metal density rules.

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    Electrical design rule check in PCb fabrication

    Original Title

    Design Rule Check

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    Design rule checking (DRC) determines if a chip layout satisfies recommended design rules. It checks for minimum widths, spacings, and enclosures. The main objective of DRC is to achieve high yield and reliability by verifying a design meets process constraints. DRC software takes the layout and design rules to produce a report of any violations for the designer to address. Example DRC checks for integrated circuits include active to active spacing, well to well spacing, minimum transistor dimensions, and metal density rules.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    311 views9 pages

    Design Rule Check: By:-Chandan ROLL NO. 15/914 B.SC (Hons.) ELECTRONICS Science

    Uploaded by

    Chandan Kumar
    Design rule checking (DRC) determines if a chip layout satisfies recommended design rules. It checks for minimum widths, spacings, and enclosures. The main objective of DRC is to achieve high yield and reliability by verifying a design meets process constraints. DRC software takes the layout and design rules to produce a report of any violations for the designer to address. Example DRC checks for integrated circuits include active to active spacing, well to well spacing, minimum transistor dimensions, and metal density rules.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 9

    DESIGN RULE CHECK

    BY:- CHANDAN
    ROLL NO. 15/914
    B.Sc (Hons.)ELECTRONICS
    SCIENCE
    DESIGN RULE CHECK

    Design rule checking(DRC) is the area of electronic


    design automation that determines whether the
    physical layout of a particular chip layout satisfies
    a series of recommended parameters called design
    rules.
     
    Design rule checking is a major step during
    physical verification signoff on the design, which
    also involves LVS (layout versus schematic) check,
    XOR checks, ERC (electrical rule check) and
    antenna checks.
     
    For advanced processes some fabrications also
    insist upon the use of more restricted rules to
    improve yield.
    1 Design rules

    The three basic DRC checks


    width,

    WIDTH

    SPACING
    SPACING

    WIDTH

    SPACING
    Enclosure
    The most basic design rules are shown
    in the diagram on the right. The first
    are single layer rules.
    A width rule specifies the minimum
    width of any shape in the design.
    A spacing rule specifies the minimum
    distance between two adjacent
    objects.
    These rules will exist for each layer of
    semiconductor manufacturing
    process, with the lowest layers having
    the smallest rules (typically 100 nm as
    of 2007) and the highest metal layers
    having larger rules(perhaps 400 nm
    as of 2007).
    OBJECTIVE OF DESIGN RULE CHECK
    The main objective of design rule checking (DRC)
    is to achieve a high overall yield and reliability
    for the de-sign. If design rules are violated the
    design may not be functional.
    To meet this goal of improving die yields, DRC has
    evolved from simple measurement and Boolean
    checks, to more involved rules that modify
    existing features, insert new features, and check
    the entire design for process limitations such as
    layer density.
    A completed layout consists not only of the
    geometric representation of the design, but also
    data that provides support for the manufacture of
    the design.
    While design rule checks do not validate that the
    design will operate correctly, they are
    constructed to verify that the structure meets the
    process constraints for a given design type and
    process technology.
    DRC SOFTWARE

    DRC software usually takes as input


    a layout in the GDSII standard
    format and a list of rules specific to
    the semiconductor process chosen for
    fabrication.
    From these it produces a report of
    design rule violations that the
    designer may or may not choose to
    correct.
    Carefully “stretching” or waiving
    certain design rules is often used to
    increase performance and component
    density at the expense of yield.
    Example of DRC’s in IC design include:

    Active to active spacing

    Well to well spacing

    Minimum channel length of the transistor

    Minimum metal width

    Metal to metal spacing

    Metal fill density (for processes using CMP) Poly


    density

    ESD and I/O rules

    Antenna effect

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