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    Pre Place

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    sree yarasi
    This document summarizes the steps in the Pre_place stage of the SD_BUILD2 design implementation flow. It describes how tap cells, fiducial cells, and FIB cells are inserted to meet design rules and specifications. Tap cells ensure n-well connectivity and can be configured in different patterns. Fiducial cells are placed in a checkerboard pattern for post-silicon debug. FIB cells are inserted in clusters and used for engineering change orders. Variables control the types of cells inserted and their placement locations and increments. Legalization is performed after cell insertion to ensure valid placements.

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    Pre Place

    Uploaded by

    sree yarasi
    115 views13 pages
    This document summarizes the steps in the Pre_place stage of the SD_BUILD2 design implementation flow. It describes how tap cells, fiducial cells, and FIB cells are inserted to meet design rules and specifications. Tap cells ensure n-well connectivity and can be configured in different patterns. Fiducial cells are placed in a checkerboard pattern for post-silicon debug. FIB cells are inserted in clusters and used for engineering change orders. Variables control the types of cells inserted and their placement locations and increments. Legalization is performed after cell insertion to ensure valid placements.

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    this is book for vlsi engineers

    Original Title

    Pre_place

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    This document summarizes the steps in the Pre_place stage of the SD_BUILD2 design implementation flow. It describes how tap cells, fiducial cells, and FIB cells are inserted to meet design rules and specifications. Tap cells ensure n-well connectivity and can be configured in different patterns. Fiducial cells are placed in a checkerboard pattern for post-silicon debug. FIB cells are inserted in clusters and used for engineering change orders. Variables control the types of cells inserted and their placement locations and increments. Legalization is performed after cell insertion to ensure valid placements.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    115 views13 pages

    Pre Place

    Uploaded by

    sree yarasi
    This document summarizes the steps in the Pre_place stage of the SD_BUILD2 design implementation flow. It describes how tap cells, fiducial cells, and FIB cells are inserted to meet design rules and specifications. Tap cells ensure n-well connectivity and can be configured in different patterns. Fiducial cells are placed in a checkerboard pattern for post-silicon debug. FIB cells are inserted in clusters and used for engineering change orders. Variables control the types of cells inserted and their placement locations and increments. Legalization is performed after cell insertion to ensure valid placements.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 13

    Pre_Place Steps in

    SD_BUILD2
    TUSHAR SUPE (PDS DDI RLS)
    DECEMBER 2016
    Steps in Pre_place

     Rdt_start
     Sd_tap_cells
     Sd_local_fiducial_cells
     Sd_fib_cells
     Sd_run_health_check
     Sd_outputs
     Rdt_done
    Sd_tap_cells

     Inserts tap cells to ensure n-well connectivity throughout the design


     The user can specify the tap cell by setting the G_TAP_CELL variable
    and can skip tap insertion by setting this variable to null
     The spacing between two tap cells can be specified by setting the
    G_TAP_MAX_SPACING variable
     The tool ensures that every cell site has a tap cell within half of the
    G_TAP_MAX_SPACING distance
     The tap insertion pattern can be controlled by the user by setting
    the G_TAP_PATTERN to “every_row” or “stagger”
    Sd_tap_cells (continued)
     The following image shows an example of tap cell insertion done with the
    G_TAP_MAX_SPACING set to 78
     It also shows additional tap cells being inserted around n-well breaking objects
    such as macros
     Flow handles narrow channels, identifies n-well breaks and ensures there is a tap
    accessible to all the cell sites
    Sd_tap_cells (continued)
     The following images show examples of taps being inserted in “every_row”
    and “stagger” patterns
     If the pattern isn’t specified then the tool will pick the every_row pattern for
    double height tap cells and a staggered pattern for the single height cells
    Sd_local_fiducial_cells

     Performs fiducial cell insertion on the entire design in a


    checkerboard pattern to meet the PDFx specifications
     These cells contain recognizable shape patterns that help to
    navigate through various parts of the chip to help with post-
    silicon debug and ECO purposes
     Fiducial cells have no logical function
     The user can choose to disable the insertion of these cells by
    setting the G_LOCAL_FIDUCIAL_PREPLACE_INSERT variable to 0
     The fiducial cell to be inserted can be set using the
    G_LOCAL_FIDUCIAL_PREPLACE_CELL variable
    Sd_local_fiducial_cells (continued)
     The user can control the placement of the fiducial cells using the
    following variables:
    G_LOCAL_FIDUCIAL_START_X,
    G_LOCAL_FIDUCIAL_START_Y,
    G_LOCAL_FIDUCIAL_INCREMENT_X
    G_LOCAL_FIDUCIAL_INCREMENT_Y
     The G_LOCAL_FIDUCIAL_START_* variables define the co-ordinates for
    the first (lower left most) fiducial cell
     The G_LOCAL_FIDUCIAL_INCREMENT_* variables define the
    horizontal/vertical spacing between two fiducial cells placed in the
    checkerboard pattern
     This is demonstrated with an example in the following slide
    Sd_local_fiducial_cells (continued)

     The following image shows the fiducial placement for the following
    variable values:

    G_LOCAL_FIDUCIAL_START_X = 5
    G_LOCAL_FIDUCIAL_START_Y = 5
    G_LOCAL_FIDUCIAL_INCREMENT_X = 20
    G_LOCAL_FIDUCIAL_INCREMENT_Y = 20
    Sd_fib_cells
     This step places FIB/spare/bonus cells into the design as clusters and ensures
    that they meet the PDFx specifications
     These cells are used for ECO purposes during pre and post silicon
     The user can choose to not insert these cells by setting G_INSERT_FIB_BONUS
    to 0
     The cells to be inserted per cluster are defined by the
    G_FIB_BONUSGARRAY_ROWS variable which is an array defining all the cells
    per row of the cluster, for example:

    G_FIB_BONUSGARRAY_ROWS(1) = e05qbnna2an1d10x5 e05qbnno2an1d10x5


    G_FIB_BONUSGARRAY_ROWS(2) = e05qbnna2an1d10x5 e05qbnno2an1d10x5
    G_FIB_BONUSGARRAY_ROWS(3) = e05qbnin1an1d24x5 e05qbnin1an1d24x5
    G_FIB_BONUSGARRAY_ROWS(4) = e05qbnbf1an1d24x5 e05qbnbf1an1d24x5
    Sd_fib_cells (continued)

     Unlike the SD_BUILD implementation of fib cell insertion, the


    placement of a cell in its specified row of the cluster is not
    strictly followed
     Therefore, a cell specified in the list of
    G_FIB_BONUSGARRAY_ROWS(1) may or may not be on the first
    row of the cluster
     Although, it is guaranteed that the cell will be present in each
    cluster that is placed by this step
     This implementation is consistent with and does not violate any
    PDFx specifications
    Sd_fib_cells (continued)
     The placement of the Fib clusters is based on similar variables as that of the
    fiducial insertion step: G_FIB_BONUS_START_X, G_FIB_BONUS_START_Y,
    G_FIB_BONUS_INCREMENT_X and G_FIB_BONUS_INCREMENT_Y
     For example:
    Common features in Pre_place

     For all the steps of the “pre_place” stage in SD_BUILD2, variant


    legalization is performed after the insertion of the cells, wherever
    required
     If the user wishes to not insert these cells even within hard
    placement blockages, he/she can do so by setting the
    G_IGNORE_PLACEMENT_BLK variable to 0
     All the cells placed in there steps have legal placements and
    are marked as fixed
    Thank You

     For issues regarding any of these steps, contact me at


    Tushar.d.supe@intel.com or please file an HSD

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