Title: Comparative Analysis of Scan Compression Techniques and

Optimization
Netlist given: Flash-interface
Work Done: Scan chain insertion and insertion of scan compression logic.
Description:
To insert the scan chain in the given netlist the following steps are carried out.
1. set_attribute lib_search_path $CWD/library :
Defines the search path for the libraries to be used.
2.set_attribute hdl_search_path $CWD/rtl :
Defines the search path for the netlist to be read.
3. set_attribute library "
tcbn40lpbwpbc0d990d99_ecsmhvt.lib
tcbn40lpbwpbc0d991d21_ecsm.lib

\
\

tcbn40lpbwpbc0d991d21_ecsmhvt.lib
tcbn40lpbwpml0d99_ecsm.lib

tcbn40lpbwpml0d99_ecsmhvt.lib

\
\

tcbn40lpbwpml1d210d99_ecsm.lib

tcbn40lpbwpml1d210d99_ecsmhvt.lib

tcbn40lpbwpwc0d990d99_ecsm.lib

tcbn40lpbwpwc0d990d99_ecsmhvt.lib

tcbn40lpbwpwc_ecsm.lib \
" :

Specifies the libraries to be read.

4. read_netlist flash_intf.et_netlist.v :

Reads and elaborates the given netlist.

5. define_dft shift_enable -create_port

SE -active high :

Creates the top level port Shift Enable.

6. define_dft test_mode -create_port TM -active high :

Creates the top level port Test Mode.

7. gui_show :

Displays the design in gui.

8. check_dft_rules :

Checks for the DFT rules (violations).

The log report for the above command as follows.
Checking DFT rules for 'flash_intf' module under 'muxed_scan' style
Checking DFT rules for clock pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for async. pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for shift registers.
Rerunning check_dft_rules due to definition of new test signals
Checking DFT rules for clock pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for async. pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for shift registers.
Detected 102 DFT rule violation(s)
Summary of check_dft_rules
**************************
Number of usable scan cells: 248
Clock Rule Violations:
--------------------Internally driven clock net: 102
Tied constant clock net: 0
Undriven clock net: 0
Conflicting async & clock net: 0
Misc. clock net: 0
Async. set/reset Rule Violations:
-------------------------------Internally driven async net:
Tied active async net:
Undriven async net:
Misc. async net:

0
0
0
0

Total number of DFT violations: 102

Warning : DFT Clock Rule Violation. [DFT-301]
: # 1 <vid_1_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin 'clk_gate_pcu_decodes_1_reg/latch/Q'
[CLOCK-05]
: Clock signal is not controllable. Affected registers will be excluded
from scan design.
Warning : DFT Clock Rule Violation. [DFT-301]
: # 2 <vid_2_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin 'clk_gate_flash_timing0_reg/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 3 <vid_3_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin 'clk_gate_flash_timing1_reg/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 4 <vid_4_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin 'clk_gate_pcu_decodes_0_reg/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 100 <vid_100_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[15]/latch/Q'
[CLOCK-05]

Warning : DFT Clock Rule Violation. [DFT-301]

: # 98 <vid_98_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[14]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 97 <vid_97_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[13]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 96 <vid_96_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[12]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 9 <vid_9_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin 'clk_gate_flash_datain_reg/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 10 <vid_10_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin 'clk_gate_read_counter_reg/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 95 <vid_95_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[11]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 94 <vid_94_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[10]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 13 <vid_13_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin 'clk_gate_pb_datain_reg/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 14 <vid_14_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin 'clk_gate_dll_control_0_reg/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 93 <vid_93_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[9]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 92 <vid_92_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[8]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 91 <vid_91_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'u_rd_ahead_buf/clk_gate_wclk_fifo_data_reg[7]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 19 <vid_19_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'dqs_pcu_inst/clk_gate_instruction_reg[6]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 20 <vid_20_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'dqs_pcu_inst/clk_gate_instruction_reg[7]/latch/Q'
[CLOCK-05]
Warning : DFT Clock Rule Violation. [DFT-301]
: # 21 <vid_21_clock>: internal or gated clock signal in module
'SNPS_CLOCK_GATE_HIGH', net 'ENCLK', inst/pin
'dqs_pcu_inst/clk_gate_instruction_reg[0]/latch/Q'
[CLOCK-05]
Warning : Suppressed printing of details of some DFT violations. [DFT-314]
: Did not print details of 82 message(s).
: Limited printing of details on DFT violations to avoid excessive data in
the log file. To control the number of violations printed to the log file, use the
'-max_print_violations' option. To print all details to the log file, use 'max_print_violations -1'. To print the output to a file, use '>' to redirect the
file.
Total number of Test Clock Domains: 2

Number of user specified non-Scan registers:

0
Number of registers that fail DFT rules: 1324
Number of registers that pass DFT rules: 195
Percentage of total registers that are scannable: 12%
102

Note: By default the tool shows only 20 violations and we can make the tool to print all the
violations also using -max_print_violations <integer>.
9. fix_dft_violations -violations vid_1_clock vid_2_clock
vid_3_clock vid_4_clock vid_100_clock vid_98_clock vid_97_clock
vid_96_clock vid_9_clock vid_10_clock vid_95_clock vid_94_clock
vid_13_clock vid_14_clock vid_93_clock vid_92_clock vid_91_clock
vid_19_clock vid_20_clock vid_21_clock -test_control TM

The above command fix the violations with the help of TM signal. The violations were due to
the derived clocks which are uncontrollable in testing and those are fixed with the help of TM
signal and a MUX.
Below shows the log results of fix_dft_violations on the above defined signals.

Checking DFT rules for clock pins

... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for async. pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for shift registers.
Detected 82 DFT rule violation(s)
Summary of check_dft_rules
**************************
Number of usable scan cells: 248
Clock Rule Violations:
--------------------Internally driven clock net: 82
Tied constant clock net: 0
Undriven clock net: 0
Conflicting async & clock net: 0
Misc. clock net: 0
Async. set/reset Rule Violations:
-------------------------------Internally driven async net:
Tied active async net:
Undriven async net:
Misc. async net:

0
0
0
0

Total number of DFT violations: 82

Warning : Suppressed printing of details of some DFT violations. [DFT-314]
: Did not print details of 82 message(s).
Total number of Test Clock Domains: 2
Number of user specified non-Scan registers:
0
Number of registers that fail DFT rules: 1004
Number of registers that pass DFT rules: 515
Percentage of total registers that are scannable: 33%

Mapping DFT logic introduced by fixing violations...

........................................
Mapping DFT logic done.

10.The remaining violations are fixed in the same manner as dd in 9th step until the
check_dft_rules provides no violations as below.
Checking DFT rules for 'flash_intf' module under 'muxed_scan' style
Checking DFT rules for clock pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for async. pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for shift registers.
Rerunning check_dft_rules due to definition of new test signals
Checking DFT rules for clock pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for async. pins
... Processed 250 registers
... Processed 500 registers
... Processed 1000 registers
Checking DFT rules for shift registers.
Detected 0 DFT rule violation(s)
Summary of check_dft_rules
**************************
Number of usable scan cells: 248
Clock Rule Violations:
--------------------Internally driven clock net: 0
Tied constant clock net: 0
Undriven clock net: 0
Conflicting async & clock net: 0
Misc. clock net: 0
Async. set/reset Rule Violations:
-------------------------------Internally driven async net:
Tied active async net:
Undriven async net:
Misc. async net:

0
0
0
0

Total number of DFT violations: 0

Total number of Test Clock Domains: 2
Number of user specified non-Scan registers:
0
Number of registers that fail DFT rules:
0
Number of registers that pass DFT rules: 1519
Percentage of total registers that are scannable: 100%
0

11. connect_scan_chains -auto_create_chains :

Stitches the scan flops in different chain according to clock domains, clock edges etc.
12. report dft_chains -summary :

Gives the summary of scan chains included in the design. The below shows the log
result of dft_chains on flash_intf

Reporting 3 scan chains (muxed_scan)

Chain 1: AutoChain_1
scan_in:
DFT_sdi_1
scan_out:
DFT_sdo_1
shift_enable: SE (active high)
clock_domain: word_clk (edge: rise)
length: 1413
-----------------------Chain 2: AutoChain_2
scan_in:
DFT_sdi_2
scan_out:
DFT_sdo_2
shift_enable: SE (active high)
clock_domain: byte_clk (edge: fall)
length: 8
-----------------------Chain 3: AutoChain_3
scan_in:
DFT_sdi_3
scan_out:
DFT_sdo_3
shift_enable: SE (active high)
clock_domain: byte_clk (edge: rise)
length: 98
------------------------

13. analyze_scan_compressibility -library "library/tcbn45gsbwphvt.v

library/tcbn45gsbwp.v" -ratio_list "20 50 100" :

Makes the analysis on compression ratios of 20, 50 and 100.

Note: The libraries with *.v files are necessary to analyze thw compressibility.
The above command creates the required environment to make the analysis. The ATPG
scripts are also generated with the all mentioned compression ratios and gives the analysis
results as shown below.
####################################
analyze_scan_compressibility Results
####################################
Design-flash_intf
Compressor-xor
Decompressor-broadcast
mask-none
Achieved compression table with fullscan topup vectors
##############################################################################
IC
TATR
TDVR
Cov.
CL
Cycles
Runtime
Gatecount
Area
##############################################################################
fs
1
1
99.85% 1413
492651
0:0
20
5
7
99.86% 71
88910
0:0
68
110.426
50
4
5
99.86% 29
100543
0:0
151
240.08
100
4
4
99.86% 15
120934
0:0
289
452.995
Achieved compression table without fullscan topup vectors
#############################################################
IC
TATR
TDVR
Cov.
CL
Cycles
#############################################################
fs
1
1
99.85% 1413
492651
20
17
52
98.72% 71
28024
50
34
104
97.71% 29
14178

100
46
140
97.39% 15
10502
Total atpg runtime for exp. 0:0 hrs.
IC
TATR
TDVR
Cov.
CL.
Cycles Runtimefs
-

Inserted compression
Test application time reduction
Test data volume reduction
Atpg coverage
Channel Length
Total no. of cycles for test
Atpg runtime
fullscan run

Command has completed successfully

0

Note: By default the decompressor and compressor (compactor) are selected as broadcast and
xor respectively by the tool.
14. analyze_scan_compressibility -library "library/tcbn45gsbwphvt.v
library/tcbn45gsbwp.v" -ratio_list "40 50 60" :

The same analysis made with the ratios of 40, 50 and 60. The below shows the report with the
defined compression ratios.

15. compress_scan_chains -ratio 40 -decompressor broadcast

-compressor xor :

Inserts the compression logic with the compression ratio 40. The result of
compression ratio is as shown below.