Wire load model

• The wire load model is also used to estimate the length of a net-based upon the
number of its fanouts.
• The wire load model depends upon the area of the block, and designs with
different areas may choose different wire load models.
• The wire load model also maps the estimated length of the net into the
resistance, capacitance, and the corresponding area overhead due to routing.
The average wire length within a block increases as the block size is increased.
• Generally, a number of wire-load models are present in the Synopsys
technology library, each representing a particular size block of the logic. These
models define the capacitance, resistance, and area factor of the net.
• Typically a wire load model selection is based upon the chip area of the block.
However these WLM models can be modified or changed according to the
user’s requirement by the designers.
• Different areas (chip or block size),
having different wire load models
would typically be used in
determining the parasitics (RC)
• The wire load model specifies slope and fanout_length for the logic under consideration
along with Resistance, capacitance, and area overhead. The fanout_length attribute
specifies the value of the wire length that is associated with the number of fanouts.
• If any fan out number is not explicitly listed in the table, the interconnect length is
obtained by using linear extrapolation and interpolation with the specified given slope.
wire_load (“wlm_conservative”) {
resistance: 6.0; # resistance per unit length of the interconnect
capacitance: 1.2; # capacitance per unit length of the interconnect
area: 0.07; # area overhead per unit length of the interconnect.
slope: 0.5; #extrapolation slope used for data points that are not specified in the fan-out length table.
fanout_length (1, 2.6);
fanout_length (2, 3.1);
fanout_length (3, 3.6);
fanout_length (4, 4.1);
fanout_length (6, 5.1);
fanout_length (7, 5.6);
}
• For extrapolation
• Example1: for fan out of 8
• Fanout 8 is not present in the table then we used linear extrapolation to
calculate the length of interconnect, Resistance, capacitance, and area
overhead.
Length = Length of Last fanout number given in the table + (The fanout
number we want – Last fanout number in WLM) * Slope
Capacitance = New calculated Length * Capacitance coefficient given in
the table
Resistance = New calculated Length * Resistance coefficient given in the
table
Area overhead due to interconnect = New calculated Length * Area
coefficient given in the table
• For interpolation:
• Example3: for fan out of 5
• Since it is between fanout numbers 4 and 6 so we calculate the length
using linear interpolation and linear interpolation between the two
nearest pairs is used to estimate any points that are not in the lookup
table.
Length = Average of fanout lengths = (Net length at fanout 4 + Net length at
fanout 6)/2
Capacitance = New calculated Length * Capacitance coefficient given in the
table
Resistance = New calculated Length * Resistance coefficient given in the
table
Area overhead due to interconnect = New calculated Length * Area coefficient
given in the table
• Top:
Applying same wire load models to all nets as if the design has no hierarchy and uses
the wire load model specified for the top level of the design hierarchy for all nets in a
design and its sub designs
Here for the delay calculation of all the nets in the design, the tool takes the wire load
model equivalent to the design top’s area.
In this mode, all the nets within the hierarchy use the wire load model of the top-
level, and if any wire load models specified in lower-level blocks (sub-blocks) then
we ignored that WLM model. Only the top-level wire load model takes precedence
over all the WLM modes.
• Enclosed :
 Here for calculating the interconnect delay for a particular net, the tool sees to which smallest
sub block this particular net belongs to, calculate the area of this sub block and applies the
wire load model corresponding to this area. This way is more realistic than the Top wire load
mode.
 The wire load model of the smallest design that fully encloses the net is applied. If the design
enclosing the net has no wire load model, then traverses the design hierarchy upward until we
finds a wire load model. Enclosed mode is more accurate than top mode when cells in the
same design are placed in a contiguous region during layout.
 Use enclosed mode if the design has similar logical and physical hierarchies.
• Segmented:
• Wire load model for each segment of a net is determined by the design encompassing the
segment. Nets crossing hierarchical boundaries are divided into segments. For each net segment,
the wire load model of the design containing the segment is used. If the design contains a
segment that has no wire load model, then traverse the design hierarchy upward until it finds a
wire load model.
• In this if a net is going from one sub design to another, the delay of the net is calculated as per the
area of both the sub designs. Suppose n1 is the part of the net N which is inside sub design D1
and n2 is the part of the same net N which is inside sub design D2. Then the delay of n1 is
calculated as per the wireload model of sub design D1 and the delay of n2 is calculated as per the
wireload model corresponding to sub design D2.
• WLM Types
For flows that run timing-based logic optimization before placement, there are
three basic types of WLMs that can be used:
Statistical WLMs
Are based on averages over many similar designs using the same or similar
physical libraries.
Structural WLMs
Use information about neighboring nets, rather than just fanout and module size
information.
Custom WLMs
Are based on the current design after placement and routing, but before the
current iteration of preplacement synthesis.
• These wire load models are based on statistical info (average wire length
among different designs) and doesn't requires cell placement info (so it is easy,
faster method, but not very accurate) i.e. just a rough estimate of the load that
can be caused by wires. Wire load model information will be in the liberty files
(what we call .libs) provided by the foundry.
• Some companies create Custom WLM. - Just to have more accurate WLM for
their own designs. They did place (and route) of their design, collect info of all
wires (fanout and length for each net), and generate average length per fanout.
For example, Synopsys Jupiter has such capability