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Migration in Solid State Materials

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Migration in Solid State Materials

Migration in Solid State Materials

Stress Migration

Electromigration

Thermomigration

due to
mechanical stress

due to
electric field

due to
thermal gradient

Electrolytic electromigration

Solid state electromigration

Electromigration
Electromigration (EM) refers to the unwanted movement of
materials in a semiconductor.Under the conditions of high current
densities and high temperatures in metals, there is momentum
transfer between conducting electrons and diffusing metal atoms.
This causes gradual drift of the ions in the metal in the direction of
electron flow and result in mass transport. This process of material
transfer is called Electromigration(EM). The affect of EM in integrated
circuits is open circuit(void) or short circuit(Hillock) failures.

Why It Matters??

At older process nodes people worried mostly about EM on power wires


and clock wires. But now signal wires need to be considered as well.
Therefore, both DC (power) and AC (signal) EM are problematic.
FinFETs have more current density than planar transistors, and thus make
EM worse, especially in conjunction with narrow wires.
Copper interconnects worsen EM because the copper molecule moves
faster.
The lower supply voltages you get with scaling help reduce EM, but not
enough to offset all the other causes that amplify it.
EM is worse at higher temperatures.
EM mitigation techniques, such as widening wires, can not only increase
area - they can cause timing violations. EM fixing needs to be timing-driven.

Introduction: Electromigration

Electromigration is the forced movement of metal ions due to an electric field

Ftotal = Fdirect + Fwind

Direct action of
electric field on
metal ions

Anode
+

Force on metal ions resulting from


momentum transfer from the
conduction electrons

<<

A
All
+

Cathode
-

Note: For simplicity, the term electron wind force often refers to the net effect of these
two electrical forces

Cont...

Metal atoms (ions) travel toward the positive end of the conductor while
vacancies move toward the negative end

Depletion of atoms (Voids):


Slow reduction of connectivity
Interconnect failure
Deposition of atoms
(Hillocks,
Whisker):
Short cuts
Hillocks

Voids

Depletions
A) Line Depletion

e
Metal1 Cu

Metal2 Cu

Void

B) Via Depletion
Metal2 Cu

Metal1 Cu

Void

Blacks Equation

MTTF=Mean time to failure of a single wire due to electromigration


Cross-section-areadependent constant

Activation energy
for electromigration

Temperature
Current density

Scaling factor
(usually set to 2)

Boltzmann constant

-> Current density is the major parameter in addressing electromigration


during physical design

Which Physical Design Parameters Effect Electromigration?

Local current density

Wire widths and via


sizes (number of
vias)

Homogeneity of the current flow

Wire shapes, corner


bends, via
arrangements, etc.

Current distribution within


device pins

Current-density-correct
pin connections

Temperature-dependency of
the maximum current
density
Immortal wires

Temperature of the
chip/interconnect
Segment length below Blech
length

10

Factors affecting Electromigration

Temperature: There will be changes in the interconnect


temperature due to power dissipation of neighbouring
interconnects or transistors on the chip, self heating of
interconnect due to current flow, poor thermal conductivity to
the ambient. Whatever the cause of temperature rise,
electromigration occurs and reduces MTTF.
Once a void begins to develop it enters positive feedback to
reduce the width of metal wire. A void causes the metal width to
reduce, means increase in local current density. As a result of it
due to Joule heating the temperature of the wire increases. The
rise in temperatures accelerates the growth of the void, and this
cycle continues, and eventually it results in open circuit.

Cont..
Thermal acceleration loop during electromigration

Cont..

Metal Width: Wider metal lines have lower current density for the
same current, hence have high resistance to electromigration. But
if the width of the metal line is reduced below the grain size of the
metal material, increases the resistance again to EM.
Metal Length: There is a lower limit on the length of metal line
below which EM does not occur for a given current density and
material choice. This length is called Blech length. Any
interconnect length below Blech length can be treated as EM
proof.

Ways to reduce EM

Widen the wire to reduce current density

Reduce the frequency

Lower the supply voltage

Keep the wire length short

Reduce buffer size in clock lines

To control EM, foundries define current limits for each wire.It is noted that a
lot goes into this calculation, including wire width, layer, activity, frequency,
and temperature. The width and length of the wires then becomes part of
the design rule set. But it's not a simple matter of just following the rules. "If
you increase the width you change the spacing," . "You need to take care of
not just the width, but also the spacing of neighboring wires."

Analyzing EM

To prevent EM failures in the field, you need an effective EM analysis


solution that can show you how to mitigate EM without sacrificing too
much area and performance. Basically, an EM analysis solution
calculates the current on each wire and compares it to foundry EM
rules. It then ideally links to an IC implementation toolset for
automated or manually assisted fixing.
Tools to handle EM analysis:
1. The Quantus QRC Extraction Solution performs an "EM aware" RC extraction on
the layout. QRC understands the layout rules for EM.
2. For custom/analog designers, the Voltus-Fi Custom Power Integrity Solution
provides transistor-level EM and IR drop analysis.

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