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Analog Layout Engineer

G. Kiran Kumar is seeking a job that allows him to use and develop his skills in a creative environment. He has over 5 years of experience in layout design and has worked with Cadence Virtuoso. He has designed analog and standard cell layouts on both 180nm and 28nm technologies. He completed his M.Tech in electronics from Jawaharlal Nehru Technological University and his B.Tech in electronics and communication engineering. His technical skills include Cadence, Calibre, C programming, and Microsoft Office. He has participated in workshops and conferences and received an award for a technical paper presentation.

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Ajay Kumar Mattupalli
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298 views

Analog Layout Engineer

G. Kiran Kumar is seeking a job that allows him to use and develop his skills in a creative environment. He has over 5 years of experience in layout design and has worked with Cadence Virtuoso. He has designed analog and standard cell layouts on both 180nm and 28nm technologies. He completed his M.Tech in electronics from Jawaharlal Nehru Technological University and his B.Tech in electronics and communication engineering. His technical skills include Cadence, Calibre, C programming, and Microsoft Office. He has participated in workshops and conferences and received an award for a technical paper presentation.

Uploaded by

Ajay Kumar Mattupalli
Copyright
© © All Rights Reserved
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
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RESUME

G.KIRAN KUMAR Mail Id:g.kiranale28@gmail.com


Mobile No: 8499099529
9986332025

Career Objective:
To work in a creative environment that would comprehensively challenge my skills and grow
professionally along with the company.

Training on Layout Design:


Company : Digicomm Semiconductor Pvt ltd, Bengaluru.
Period : 5 May 2016 to Till date.
Tools learned : Cadence Virtuoso.
Technologies : 180nm, 28 nm.
Layout skills :
Designing Analog and Standard cell layouts.
Matching the devices using Inter digitization & Common-Centroid methods.
Making floor planning of circuits & routing of signals.
Checking DRC & LVS for the layouts.
Aware of the layout failure mechanisms like Electro-migration, Electrostatic
Discharge, Antenna Effect, Latch-up, IR drop and how to overcome those issues.
Familiar with Shallow Trench Isolation and Deep N-well concepts.
Familiar with P-Cells and creating it in Cadence.
Standard cells Designed:
Invertor, Nand, Nor, Mux, D-Latch on both 180nm and 28nm.
Project (Real Time):
Technology: TSMC 28nm , 180nm.
Period: Jan. 2016 to May. 2016
Tools Used: Cadence Virtuoso 6.1.6.
Description:
Bias (Transmitter):
Designed layouts for PMOS mirror.
Did top level integration of the bias block.
Checked LVS & DRC of the total block.
De-Serializer :
Designed the Multiplexer layout with fixed height.
Did top level integration & power routing of the De serializer.
Checked LVS & DRC for various layouts.
Routed clock signals in higher metals with more spacing.
Bias (Receiver):
Designed layouts for PMOS mirror, NMOS mirror.
Did top level integration of the bias block.
Designed current amplifier.

Educational Qualifications:
2013 2016 M.Tech

Jawaharlal Nehru Technological University, Kakinada


Indira Institute of Technology,Markapur
Percentage:70.17

2007 2011 B.Tech. in Electronics and Communication


Engineering Stream
Jawaharlal Nehru Technological University, Kakinada
SSN Engineering College, Ongole Percentage:60
Intermediate in MPC stream,
2005 2007
Board of Intermediate, Andhra Pradesh
Uma maheswara Junior College, Ongole Percentage:75
2004 2005 SSC
Board of Secondary Education, Andhra Pradesh
ST Josephs English Medium high School, Kadapa
Percentage: 75

Technical Skill Set:


IC Designing Tools : Cadence,Calibre
Programming Languages : C.
Package Tools : Microsoft Office.
Operating Systems : Windows, Linux (Basics).

Co-curricular Activities:

Played a key role in organizing the VLSI workshop held at our college.
Attended a national level workshop on Sixth-Sense Robotics at NIT Warangal.
Achievements:

Bagged II prize in Technical Paper Presentation on the topic Eye Gaze


Communication held at LBR College of Engineering, Mylavaram.
Strengths:

Active participation.
Never give up attitude.
Flexibility & friendly nature.
Willingness to learn new things.
Ability to work in teams.
Academic Project:

Title: 32 Bit32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier
Description: : A Multi precision (MP) reconfigurable multiplier that incorporates variable
precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and
dedicated MP operands scheduling to provide optimum performance for a variety of
operating conditions
The proposed novel MP multiplier can further benefit from an operands scheduler that
rearranges the input data, hence to determine the optimum voltage and frequency operating
conditions for minimum power consumption
The Architecture is designed using the fundamentals of Digital Design and Computer
Architectures, simulated in ModelSim and implemented by XILINX ISE, FPGA.

PERSONAL DETAILS:

Personal Details
Name G Kiran Kumar
Date of Birth April 28, 1990
Fathers Name G Rangaiah
Mothers Name G Rangamma
Nationality Indian
Gender Male
Languages Hindi, English, Telugu.
Hobbies Listening music, playing chess
Declaration:

I hereby declare that the above mentioned information is correct up to my


knowledge.

Place: Bengaluru.
Date: (KIRAN KUMAR G)

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