November 2002

UCT P RO D E P RO DU CT E T E L UT O BS O ter at BSTIT LE SU Support Cen /tsc IB S S PO al om FOR A our Technic ww.intersil.c t w c a r t c on SIL o INTER 1-888

CA3306, CA3306A, CA3306C

6-Bit, 15 MSPS, Flash A/D Converters

Features
CMOS Low Power with Video Speed (Typ) . . . . . 70mW Parallel Conversion Technique Signal Power Supply Voltage . . . . . . . . . . . 3V to 7.5V 15MHz Sampling Rate with Single 5V Supply 6-Bit Latched Three-State Output with Overflow Bit Pin-for-Pin Retrofit for the CA3300

Description
The CA3306 family are CMOS parallel (FLASH) analog-to-digital converters designed for applications demanding both low power consumption and high speed digitization. Digitizing at 15MHz, for example, requires only about 50mW. The CA3306 family operates over a wide, full scale signal input voltage range of 1V up to the supply voltage. Power consumption is as low as 15mW, depending upon the clock frequency selected. The CA3306 types may be directly retrofitted into CA3300 sockets, offering improved linearity at a lower reference voltage and high operating speed with a 5V supply. The intrinsic high conversion rate makes the CA3306 types ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3306s in series to increase the resolution of the conversion system. A series connection of two CA3306s may be used to produce a 7-bit high speed converter. Operation of two CA3306s in parallel doubles the conversion speed (i.e., increases the sampling rate from 15MHz to 30MHz). Sixty-four paralleled auto balanced comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the CA3306. Sixty-three comparators are required to quantize all input voltage levels in this 6-bit converter, and the additional comparator is required for the overflow bit.

Applications
TV Video Digitizing Ultrasound Signature Analysis Transient Signal Analysis High Energy Physics Research High Speed Oscilloscope Storage/Display General Purpose Hybrid ADCs Optical Character Recognition Radar Pulse Analysis Motion Signature Analysis Robot Vision

Part Number Information

PART NUMBER LINEARITY (INL, DNL) CA3306E CA3306CE CA3306M CA3306CM CA3306D CA3306CD CA3306J3 CA3306J3 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB SAMPLING RATE 15MHz (67ns) 10MHz (100ns) 15MHz (67ns) 10MHz (100ns) 15MHz (67ns) 10MHz (100ns) 15MHz (67ns) 10MHz (100ns) TEMP. RANGE (oC) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 18 Ld PDIP 18 Ld PDIP 20 Ld SOIC 20 Ld SOIC 18 Ld SBDIP 18 Ld SBDIP 20 Ld CLCC 20 Ld CLCC PKG. NO. E18.3 E18.3 M20.3 M20.3 D18.3 D18.3 J20.B J20.B

Pinouts
CA3306 (PDIP, SBDIP) TOP VIEW CA3306 (SOIC) TOP VIEW
(MSB) B6 1 OVERFLOW 2 VSS 3 NC 4 VZ 5 CE2 6 CE1 7 CLK 8 PHASE 9 VREF + 10 20 B5 19 B4 18 REF CENTER 17 B3 16 B2 15 B1 (LSB) 14 VDD 13 NC 12 VIN 11 VREF -

CA3306 (CLCC) TOP VIEW

OVERFLOW B6 (MSB) NC 3 VSS 4 VZ 5 NC 6 CE2 7 CE1 8 9 10 11 12 13 VREF + VREF CLK PHASE VIN 2

B5

OVERFLOW 2 VSS 3 VZ 4 CE2 5 CE2 6 CLK 7 PHASE 8 VREF + 9

17 B4 REF 16 CENTER 15 B3 14 B2 13 B1 (LSB) 12 VDD 11 VIN 10 VREF -

1 20 19 18 REF CENTER 17 B3 16 B2 15 B1 (LSB) 14 VDD

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

B4

(MSB) B6 1

18 B5

FN3102.2

CA3306, CA3306A, CA3306C Functional Block Diagram

VIN

1
R/2 VREF+ R

1 2

1 2
COMP 64 D Q CL THREE-STATE OVERFLOW

COMP 63

D Q CL

B6 (MSB)

120
REF CENTER

R COMP 32 COMPARATOR LATCHES AND ENCODER LOGIC

D Q CL

B5

D Q CL

B4

R COMP 2 R VREFR/2 COMP 1

D Q CL

B3

D Q CL

B2

D Q CL

B1 (LSB)

50k
CLOCK CE1

2 (SAMPLE UNKNOWN)
PHASE

1 (AUTO BALANCE)

CE2

ZENER 6.2V NOMINAL DIODE VSS VDD VSS

Typical Application Circuit

OF 1 2 6.2V 560 +12V +5V 5 6 CLOCK +12V 5k + CA741CE 7 8 9 CLK PH VREF+ VDD 12 VIN 11 VREF- 10 SIGNAL INPUT 0.2F CE2 CE1 B2 14 B1 13 +5V 10F 4 VZ B3 15 3 B6 OF VSS CA3306 B5 18 B4 17 0.1F RC 16 B6 B5 B4 B3 B2 B1 (LSB) DATA OUTPUT

0.1F

CA3306, CA3306A, CA3306C

Absolute Maximum Ratings
DC Supply Voltage Range, VDD Voltage Referenced to VSS Terminal . . . . . . . . . . . -0.5V to +8.5V Input Voltage Range All Inputs Except Zener. . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V DC Input Current CLK, PH, CE1, CE2, VIN . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . . . 75 24 PDIP Package . . . . . . . . . . . . . . . . . . . . . 95 N/A SOIC Package. . . . . . . . . . . . . . . . . . . . . 115 N/A CLCC Package . . . . . . . . . . . . . . . . . . . . 80 28 Maximum Junction Temperature Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)

Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 8V Temperature Range (TA) Ceramic Package (D Suffix) . . . . . . . . . . . . . . . . . -55oC to 125oC Plastic Package (E or M Suffix) . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL

TA = 25oC, VDD = 5V, VREF + = 4.8V, VSS = VREF - = GND, Clock = 15MHz Square Wave for CA3306 or CA3306A, 10MHz for CA3306C TEST CONDITIONS MIN TYP MAX UNITS

6 CA3306, CA3306C CA3306A -

0.25 0.2 0.25 0.2 0.5 0.25 0.5 0.25 +0.1 -0.1

0.5 0.25 0.5 0.25 1 0.5 1 0.5 -

Bits LSB LSB LSB LSB LSB LSB LSB LSB mV/oC mV/oC

Differential Linearity Error, DNL Offset Error (Unadjusted)

CA3306, CA3306C CA3306A CA3306, CA3306C (Note 1) CA3306A

Gain Error (Unadjusted)

CA3306, CA3306C (Note 2) CA3306A

Gain Temperature Coefficient Offset Temperature Coefficient DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale) Maximum Conversion Speed CA3306C CA3306, CA3306A Maximum Conversion Speed CA3306C CA3306, CA3306A Allowable Input Bandwidth -3dB Input Bandwidth Signal to Noise Ratio, SNR RMSSignal = -------------------------------RMSNoise Signal to Noise Ratio, SINAD RMSSignal = ----------------------------------------------------------RMSNoise+Distortion Total Harmonic Distortion, THD fS = 15MHz, fIN = 100kHz fS = 15MHz, fIN = 5MHz fS = 15MHz, fIN = 100kHz fS = 15MHz, fIN = 5MHz fS = 15MHz, fIN = 100kHz fS = 15MHz, fIN = 5MHz Effective Number of Bits, ENOB fS = 15MHz, fIN = 100kHz fS = 15MHz, fIN = 5MHz

10 15

13 20 30 34.6 33.4 34.2 29.0 -46.0 -30.0 5.5 4.5

fCLOCK/2 -

MSPS MSPS MSPS MSPS MHz MHz dB dB dB dB dBc dBc Bits Bits

1, 2 Minimum
(Note 4)

(Note 4)

12 18 DC -

CA3306, CA3306A, CA3306C

Electrical Specifications
PARAMETER ANALOG INPUTS Positive Full Scale Input Range Negative Full Scale Input Range Input Capacitance Input Current INTERNAL VOLTAGE REFERENCE Zener Voltage Zener Dynamic Impedance Zener Temperature Coefficient REFERENCE INPUTS Resistor Ladder Impedance DIGITAL INPUTS Maximum VIN , Logic 0 Maximum VIN , Logic 1 Digital Input Current Digital Input Current DIGITAL OUTPUTS Digital Output Three-State Leakage Digital Output Source Current Digital Output Sink Current TIMING CHARACTERISTICS Auto Balance Time (1) Sample Time (2) CA3306C CA3306, CA3306A CA3306C CA3306, CA3306A Aperture Delay Aperture Jitter Output Data Valid Delay, tD CA3306C CA3306, CA3306A Output Data Hold Time, tH Output Enable Time, tEN Output Disable Time, tDIS POWER SUPPLY CHARACTERISTICS IDD Current, Refer to Figure 4 CA3306C CA3306, CA3306A IDD Current NOTES: 1. OFFSET ERROR is the difference between the input voltage that causes the 00 to 01 output code transition and (VREF + - VREF -)/128. 2. GAIN ERROR is the difference the input voltage that causes the 3F16 to overflow output code transition and (VREF + - VREF -) x 127/128. 3. The total input voltage range, set by VREF + and VREF -, may be in the range of 1 to (VDD + 1) V. 4. Parameter not tested, but guaranteed by design or characterization. Continuous 1 Continuous Conversion (Note 4) 11 14 7.5 20 25 15 mA mA mA (Note 4) (Note 4) 50 33 33 22 15 8 100 35 30 25 20 15 VOUT = 0V, 5V VOUT = 4.6V VOUT = 0.4V -1.6 3.2 1 5 A mA mA All Digital Inputs (Note 4) All Digital Inputs (Note 4) Except CLK, VIN = 0V, 5V CLK Only 0.7 x VDD 1 100 0.3 x VDD 5 200 V V A A 650 1100 1550 IZ = 10mA IZ = 10mA, 20mA 5.4 6.2 12 -0.5 7.4 25 V mV/oC VIN = 4.92V, VDD = 5V (Notes 3, 4) (Notes 3, 4) 1 -0.5 4.8 0 15 VDD + 0.5 VDD - 1 500 V V pF A TA = 25oC, VDD = 5V, VREF + = 4.8V, VSS = VREF - = GND, Clock = 15MHz Square Wave for CA3306 or CA3306A, 10MHz for CA3306C (Continued) TEST CONDITIONS MIN TYP MAX UNITS

5000 5000 50 40 -

ns

ns ns ns psP-P ns ns ns ns ns

CA3306, CA3306A, CA3306C Timing Waveforms

COMPARATOR DATA IS LATCHED CLOCK IF PHASE IS HIGH DECODED DATA IS SHIFTED TO OUTPUT REGISTERS

CLOCK IF PHASE IS LOW

AUTO BALANCE

SAMPLE N+1 tD tH

AUTO BALANCE

SAMPLE N+2

DATA N-2

DATA N-1

DATA N

FIGURE 1. INPUT-TO-OUTPUT

CE1

CE2

tDIS

tEN tDIS HIGH IMPEDANCE tDIS HIGH IMPEDANCE DATA DATA

BITS 1-6

DATA

HIGH IMPEDANCE OF DATA DATA

FIGURE 2. OUTPUT ENABLE

CA3306, CA3306A, CA3306C Timing Waveforms

SAMPLE ENDS CLOCK SAMPLE ENDS

1
tD

CLOCK

2
tD

OUTPUT

OLD DATA

NEW DATA

OUTPUT

OLD DATA

OLD DATA +1 FIGURE 3B.

NEW DATA

FIGURE 3A. SAMPLE ENDS CLOCK

2
tD

OUTPUT

OLD DATA FIGURE 3C.

INVALID DATA

NEW DATA

FIGURE 3. PULSE MODE

Typical Performance Curves

50 AMBIENT TEMPERATURE (oC) TA = 25oC, VREF + = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 40 DISSIPATION LIMITED IDD (mA) 30 VDD VDD VDD VDD = 8V = 7V = 6V = 5V 125 fCLK = 3MHz fCLK = 10MHz fCLK = 15MHz fCLK = 20MHz fCLK = 1MHz

100

75

MAXIMUM AMBIENT TEMPERATURE - PLASTIC

20

50

10 VDD = 3V

VREF + = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 ZENER NOT CONNECTED

25 0.1 1 CLOCK FREQUENCY (MHz) 10 3 4 5 VDD (V) 6 7 8

FIGURE 4. TYPICAL IDD AS A FUNCTION OF VDD

FIGURE 5. TYPICAL MAXIMUM AMBIENT TEMPERATURE AS A FUNCTION OF SUPPLY VOLTAGE

CA3306, CA3306A, CA3306C Typical Performance Curves

0.35 TA = 25oC, VREF = 4.8V 0.30 VDD = 5V NON-LINEARITY (LSB) 0.25 INTEGRAL 0.20 0.15 DIFFERENTIAL 0.10 0.05 0 0.1 NON-LINEARITY (LSB) 1.2 1.0 0.8 INTEGRAL 0.6 0.4 DIFFERENTIAL 0.2 0 1 CLOCK FREQUENCY (MHz) 10 0 1 2 3 REFERENCE VOLTAGE (V) 4 5 TA = 25oC, VDD = 5V fCLK = 15MHz

(Continued)

FIGURE 6. TYPICAL NON-LINEARITY AS A FUNCTION OF CLOCK SPEED

FIGURE 7. TYPICAL NON-LINEARITY AS A FUNCTION OF REFERENCE VOLTAGE

+15 PEAK INPUT CURRENT (mA) +10 +5

VREF + = VDD , VREF - = VSS +400

fCLK = 15MHz, VREF + = VDD VREF - = VSS INPUT CURRENT (A)

VDD = 8V VDD = 5V

VDD = 8V +200 VDD = 5V +0 -200 -400 -600 -800

0 -5 -10 -15

4 5 6 7 INPUT VOLTAGE (V)

4 5 6 7 INPUT VOLTAGE (V)

FIGURE 8. TYPICAL PEAK INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE

FIGURE 9. TYPICAL AVERAGE INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE

CA3306, CA3306A, CA3306C Typical Performance Curves

TA = 25oC, VREF+ = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 30 25 20 15 10 5 0 3 4 5 6 7 8 SUPPLY VOLTAGE (V) 6 5 4 DECODER LIMITED DISSIPATION LIMITED

(Continued)
11 10 9 IDD (mA) 8 7

10 fS (MHz)

15

20

FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE

FIGURE 11. DEVICE CURRENT vs SAMPLE FREQUENCY

32.5 30.0

6.0 5.7 5.4 fS = 15MHz, fI = 1MHz

27.5 ENOB (LSB) -25 0 25 50 75 100 tD (ns) 25.0 22.5 20.0 17.5 15.0 -50

5.1 4.8 4.5 4.2 3.9 3.6 3.3 3.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90

TEMPERATURE (oC)

TEMPERATURE (oC)

FIGURE 12. DATA DELAY vs TEMPERATURE

FIGURE 13. ENOB vs TEMPERATURE

14.0 12.6 11.2 NON-LINEARITY (LSB) 9.8 8.4 IDD (mA) 7.0 5.6 4.2 2.8 1.4 0.0 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (oC) 60 70 80 90

1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.0 -40 -30 -20 -10 0 10 20 30 40 50 DNL INL fS = 15MHz

60

70

80

90

TEMPERATURE (oC)

FIGURE 14. IDD vs TEMPERATURE

FIGURE 15. NON-LINEARITY vs TEMPERATURE

CA3306, CA3306A, CA3306C Typical Performance Curves

6.00 5.70 5.40 5.10 ENOB (LSB) 4.80 4.50 4.20 3.90 3.60 3.30 3.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 fI (MHz) fS = 15MHz

(Continued)

FIGURE 16. ENOB vs INPUT FREQUENCY

Pin Descriptions
PIN NUMBER DIP 1 2 3 4 5 6 7 8 SOIC 1 2 3, 4 5 6 7 8 9 NAME B6 OF VSS VZ CE2 CE1 CLK Phase Bit 6, Output (MSB). Overflow, Output. Digital Ground. Zener Reference Output. Three-State Output Enable Input, Active Low. See Table 1. Three-State Output Enable Input, Active High. See Table 1. Clock Input. Sample clock phase control input. When PHASE is low, Sample Unknown occurs when the clock is low and Auto Balance occurs when the clock is high (see text). Reference Voltage Positive Input. Reference Voltage Negative Input. Analog Signal Input. Power Supply, +5V. Bit 1, Output (LSB). Bit 2, Output. Bit 3, Output. Reference Ladder Midpoint. Bit 4, Output. Bit 5, Output. DESCRIPTION

9 10 11 12 13 14 15 16 17 18

10 11 12 13, 14 15 16 17 18 19 20

VREF + VREF VIN VDD B1 B2 B3 REF(CTR) B4 B5

CA3306, CA3306A, CA3306C

TABLE 1. CHIP ENABLE TRUTH TABLE CE1 0 1 X X = Dont care CE2 1 1 0 B1 - B6 Valid Three-State Three-State OF Valid Valid Three-State

TABLE 2. OUTPUT CODE TABLE (NOTE 1) INPUT VOLTAGE VREF 6.40 (V) 0.00 0.10 0.20 VREF 5.12 (V) 0.00 0.08 0.16 3.10 3.20 3.30 2.48 2.56 2.64 6.20 6.30 6.40 4.96 5.04 5.12 4.65 4.725 4.80 3.10 3.15 3.20 0 0 1 1 1 1 1 1 1 2.325 2.40 2.475 1.55 1.60 1.65 0 0 0 0 1 1 1 0 0 VREF 4.80 (V) 0.00 0.075 0.15 VREF 3.20 (V) 0.00 0.05 0.10 BINARY OUTPUT CODE (LSB) DECIMAL COUNT 0 1 2 1 0 0 1 0 0 1 0 1 31 32 33 1 1 1 1 1 1 0 1 1 62 63 127

CODE DESCRIPTION Zero 1 LSB 2 LSB

1/ Full Scale - 1 LSB 2 1/ Full Scale 2 1/ Full Scale + 1 LSB 2

OF 0 0 0

B6 0 0 0

B5 0 0 0

B4 0 0 0 1 0 0 1 1 1

B3 0 0 0

B2 0 0 1

B1 0 1 0

Full Scale - 1 LSB Full Scale Overflow NOTE:

1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.

10

CA3306, CA3306A, CA3306C Device Operation

A sequential parallel technique is used by the CA3306 converter to obtain its high speed operation. The sequence consists of the Auto Balance phase 1 and the Sample Unknown phase 2. (Refer to the circuit diagram.) Each conversion takes one clock cycle (see Note). With the phase control low, the Auto Balance (1) occurs during the High period of the clock cycle, and the Sample Unknown (2) occurs during the low period of the clock cycle. During the Auto Balance phase, a transmission-gate switch is used to connect each of 64 commutating capacitors to their associated ladder reference tap. Those tap voltages will be as follows: VTAP (N) = [(VREF/64) x N] - [VREF/(2 x 64)] = VREF[(2N - 1)/126], Where: VTAP (N) = reference ladder tap voltage at point N, VREF = voltage across VREF - to VREF +, N = tap number (I through 64).
NOTE: This device requires only a single-phase clock The terminology of 1 and 2 refers to the High and Low periods of the same clock.

Continuous Clock Operation One complete conversion cycle can be traced through the CA3306 via the following steps. (Refer to timing diagram, Figure 1.) With the phase control in a High state, the rising edge of the clock input will start a sample phase. During this entire High state of the clock, the 64 comparators will track the input voltage and the 64 latches will track the comparator outputs. At the falling edge of the clock, after the specified aperture delay, all 64 comparator outputs are captured by the 64 latches. This ends the sample phase and starts the auto balance phase for the comparators. During this Low state of the clock the output of the latches propagates through the decode array and a 7-bit code appears at the D inputs of the output registers. On the next rising edge of the clock, this 7bit code is shifted into the output registers and appears with time delay to as valid data at the output of the three-state drivers. This also marks the start of a new sample phase, thereby repeating the conversion process for this next cycle. Pulse Mode Operation For sampling high speed nonrecurrent or transient data, the converter may be operated in a pulse mode in one of three ways. The fastest method is to keep the converter in the Sample Unknown phase, 2, during the standby state. The device can now be pulsed through the Auto Balance phase with a single pulse. The analog value is captured on the leading edge of 1 and is transferred into the output registers on the trailing edge of 1. We are now back in the standby state, 2, and another conversion can be started, but not later than 5s due to the eventual droop of the commutating capacitors. Another advantage of this method is that it has the potential of having the lowest power drain. The larger the time ratio between 2 and 1, the lower the power consumption. (See Timing Waveform, Figure 3.) The second method uses the Auto Balance phase, 1, as the standby state. In this state the converter can stay indefinitely waiting to start a conversion. A conversion is performed by strobing the clock input with two 2 pulses. The first pulse starts a Sample Unknown phase and captures the analog value in the comparator latches on the trailing edge. A second 2 pulse is needed to transfer the data into the output registers. This occurs on the leading edge of the second pulse. The conversion now takes slightly longer, but the repetition rate may be as slow as desired. The disadvantage to this method is the higher device dissipation due to the low ratio of 2 to 1. (See Timing Waveform, Figure 3B.) For applications requiring both indefinite standby and lowest power, standby can be in the 2 (Sample Unknown) state with two 1 pulses to generate valid data (see Figure 3C). Valid data now appears two full clock cycles after starting the conversion process. Analog Input Considerations The CA3306 input terminal is characterized by a small capacitance (see Specifications) and a small voltagedependent current (See Typical Performance Curves). The signal-source impedance should be kept low, however, when operating the CA3306 at high clock rates.

The other side of the capacitor is connected to a singlestage inverting amplifier whose output is shorted to its input by a switch. This biases the amplifier at its intrinsic trip point, which is approximately, (VDD - VSS)/2. The capacitors now charge to their associated tap voltages, priming the circuit for the next phase. In the Sample Unknown phase, all ladder tap switches are opened, the comparator amplifiers are no longer shorted, and VlN is switched to all 64 capacitors. Since the other end of the capacitor is now looking into an effectively open circuit, any voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators whose tap voltages were lower than VlN will drive the comparator outputs to a low state. All comparators whose tap voltages were higher than VlN will drive the comparator outputs to a high state. A second, capacitorcoupled, auto-zeroed amplifier further amplifies the outputs. The status of all these comparator amplifiers are stored at the end of this phase (2), by a secondary latching amplifier stage. Once latched, the status of the 64 comparators is decoded by a 64-bit 7-bit decode array and the results are clocked into a storage register at the rising edge of the next 2. A three-state buffer is used at the output of the 7 storage registers which are controlled by two chip-enable signals. CE1 will independently disable 81 through 86 when it is in a high state. CE2 will independently disable B1 through B6 and the OF buffers when it is in the low state (Table 1). To facilitate usage of this device a phase-control input is provided which can effectively complement the clock as it enters the chip. Also, an on-board zener is provided for use as a reference voltage.

11

CA3306, CA3306A, CA3306C

The CA3306 outputs a short (less than 10ns) current spike of up to several mA amplitude (See Typical Performance Curves) at the beginning of the sample phase. (To a lesser extent, a spike also appears at the beginning of auto balance.) The driving source must recover from the spike by the end of the same phase, or a loss of accuracy will result. A locally terminated 50 or 75 source is generally sufficient to drive the CA3306. If gain is required, a high speed, fast settling operational amplifier, such as the HA-5033, HA-2542, or HA5020 is recommended. Digital Input And Output Interfacing The two chip-enable and the phase-control inputs are standard CMOS units. They should be driven from less than 0.3 x VDD to at least 0.7 x VDD . This can be done from 74HC series CMOS (QMOS), TTL with pull-up resistors, or, if VDD is greater than the logic supply, open collector or open drain drivers plus pull-ups. (See Figure 20.) The clock input is more critical to timing variations, such as 1 becoming too short, for instance. Pull-up resistors should generally be avoided in favor of active drivers. The clock input may be capacitively coupled, as it has an internal 50k feedback resistor on the first buffer stage, and will seek its own trip point. A clock source of at least 1VP-P is adequate, but extremely non-symmetrical waveforms should be avoided. The output drivers have full rail-to-rail capability. If driving CMOS systems with VDD below the VDD of the CA3306, a CD74HC4050 or CD74HC4049 should be used to step down the voltage. If driving LSTTL systems, no step-down should be necessary, as most LSTTLs will take input swings up to 10V to 15V. Although the output drivers are capable of handling typical data bus loading, the capacitor charging currents will produce local ground disturbances. For this reason, an external bus driver is recommended. Increased Accuracy In most cases the accuracy of the CA3306 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, three adjustments can be made to obtain better accuracy; i.e., offset trim, gain trim, and midpoint trim. Offset Trim In general offset correction can be done in the preamp circuitry by introducing a DC shift to VlN or by the offset trim of the operational amplifier. When this is not possible the VREF- input can be adjusted to produce an offset trim. The theoretical input voltage to produce the first transition is 1/2 LSB. The equation is as follows: VIN (0 to 1 transition) = 1/2 LSB = 1/2(VREF/64) = VREF/128. If VlN for the first transition is less than the theoretical, then a single-turn 50 pot connected between VREF- and ground will accomplish the adjustment. Set VlN to 1/2 LSB and trim the pot until the 0 to 1 transition occurs. If VIN for the first transition is greater than the theoretical, then the 50 pot should be connected between VREF and a negative voltage of about 2 LSBs. The trim procedure is as stated previously. Gain Trim In general the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the operational amplifier. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, VlN should be set to the 63 to overflow transition. That voltage is 1/2 LSB less than VREF+ and is calculated as follows: VlN (63 to 64 transition) = VREF - VREF/128 = VREF(127/128). To perform the gain trim, first do the offset trim and then apply the required VlN for the 63 to overtlow transition. Now adjust VREF+ until that transition occurs on the outputs. Midpoint Trim The reference center (RC) is available to the user as the midpoint of the resistor ladder. To trim the midpoint, the offset and gain trims should be done first. The theoretical transition from count 31 to 32 occurs at 311/2 LSBs. That voltage is as follows: VlN (31 to 32 transition) = 31.5 (VREF/64) = VREF(63/128). An adjustable voltage follower can be connected to the RC pin or a 2K pot can be connected between VREF+ and VREF- with the wiper connected to RC. Set VlN to the 31 to 32 transition voltage, then adjust the voltage follower or the pot until the transition occurs on the output bits. The Reference Center point can also be used to create unique transfer functions. The user must remember, however, that there is approximately 120 in series with the RC pin.

Applications
7-Bit Resolution To obtain 7-bit resolution, two CA3306s can be wired together. Necessary ingredients include an open-ended ladder network, an overtlow indicator, three-state outputs, and chip-enabler controls - all of which are available on the CA3306. The first step for connecting a 7-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 17. Since the absolute resistance value of each ladder may vary, external trim of the mid-reference voltage may be required. The overflow output of the lower device now becomes the seventh bit. When it goes high, all counts must come from the upper device. When it goes low, all counts must come from the lower device. This is done simply by connecting the lower overflow signal to the CE1 control of the lower A/D converter and the CE2 control of the upper A/D converter. The three-state outputs of the two devices (bits 1 through 6) are now connected in parallel to complete the circuitry.

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CA3306, CA3306A, CA3306C

Doubled Sampling Speed The phase control and both positive and negative true chip enables allow the parallel connection of two CA3306s to double the sampling speed. Figure 18 shows this configuration. One converter samples on the positive phase of the clock, and the second on the negative. The outputs are also alternately enabled. Care should be taken to provide a near square-wave clock it operating at close to the maximum clock speed for the devices. 8-Bit to 12-Bit Conversion Techniques To obtain 8-bit to 12-bit resolution and accuracy, use a feedforward conversion technique. Two A/D converters will be needed to convert up to 11 bits; three A/D converters to convert 12 bits. The high speed of the CA3306 allows 12-bit conversions in the 500ns to 900ns range. The circuit diagram of a high-speed 12-bit A/D converter is shown in Figure 19. In the feed-forward conversion method two sequential conversions are made. Converter A first does a coarse conversion to 6 bits. The output is applied to a 6-bit D/A converter whose accuracy level is good to 12 bits. The D/A converter output is then subtracted from the input voltage, multiplied by 32, and then converted by a second flash A/D converter, which is connected in a 7-bit configuration. The answers from the first and second conversions are added together with bit 1 of the first conversion overlapping bit 7 of the second conversion. When using this method, take care that: The linearity of the first converter is better than 1/2 LSB. An offset bias of 1 LSB (1/64) Is subtracted from the first conversion since the second converter is unipolar. The D/A converter and its reference are accurate to the total number of bits desired for the final conversion (the A/D converter need only be accurate to 6 bits). The first converter can be offset-biased by adding a 20 resistor at the bottom of the ladder and increasing the reference voltage by 1 LSB. If a 6.4V reference is used in the system, for example, then the first CA3306 will require a 6.5V reference. Signal-to-Noise (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number of Bits (ENOB) The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: ENOB = (SINAD - 1.76 + VCORR)/6.02, where: VCORR = 0.5dB.

Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal.

Operating and Handling Considerations

HANDLING All inputs and outputs of Intersil CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in AN6525. Guide to Better Handling and Operation of CMOS Integrated Circuits. OPERATING Operating Voltage During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause VDD - VSS to exceed the absolute maximum rating. Input Signals To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS . Input currents must not exceed 20mA even when the power supply is off. The zener (pin 4) is the only terminal allowed to exceed VDD . Unused Inputs A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS , whichever is appropriate. Output Short Circuits Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation.

Definitions
Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the converter. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests.

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CA3306, CA3306A, CA3306C Application Circuits

OF B7 (MSB) B6

B6 V+ 1K VSS CA3306 VZ CLOCK INPUT CE2 CE1 CLK VSS PH OF

B5 B4 RC 0.1F

B5 B4 DATA OUTPUT

B3 B2 (LSB) B1 V+ VDD 0.2F VIN 10F

B3 B2 B1

0.1F

VREF + VREF -

ADJUST POT TO 1/2 VZ B6 B5

OF B4 CA3306 RC VSS V+ VZ CE2 CE1 CLK B3 B2 B1 VDD

0.1F

0.2F PH VIN VREF VREF + 0.1F

10F NOTE: VDD MUST BE VZ FOR CIRCUIT TO WORK WITH VZ CONNECTED TO VREF+ SIGNAL INPUT

FIGURE 17. TYPICAL CA3306 7-BIT RESOLUTION CONFIGURATION

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CA3306, CA3306A, CA3306C Application Circuits

(Continued)

(MSB) B6

B6 V+ OF

B5 B4 RC

B5 B4 DATA OUTPUT

VSS CA3306 VZ CLOCK INPUT CE2 CE1 CLK VSS PH VIN VREF + VREF B3 B2

0.1F B3 B2 (LSB) B1 V+ VDD 0.2F 10F B1

0.1F

ADJUST POT TO 1/2 VZ

B6 OF

B5 B4

CA3306 VSS V+ VZ B3 CE2 B2 CE1 CLK B1 VDD 0.2F V+ PH VIN VREF VREF + 0.1F 10F NOTE: VDD MUST BE VZ FOR CIRCUIT TO WORK WITH VZ CONNECTED TO VREF+ SIGNAL INPUT RC 0.1F

FIGURE 18. TYPICAL CA3306 6-BIT RESOLUTION CONFIGURATION WITH DOUBLE SAMPLING RATE CAPABILITY

15

Application Circuits

(Continued)
BINARY ADDER B6 B12 B6 + 0 B5 + 0 B4 + 0 B3 + 0 B2 + 0 B1 + B7 B6

S/H, VIN

NO. 1 6-BIT FLASH ADC

B1

X32 NO. 2 6-BIT FLASH ADC

6-BIT DAC (12 BIT ACCURACY) B6 B1 B1

B7 NO. 3 6-BIT FLASH ADC B6 B1

CONTROL LOGIC

FIGURE 19. TYPICAL CA3306, 800ns, 12-BIT ADC SYSTEM

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Application Circuits

(Continued)

5V

VDD 1K

CA3306

VDD

CA3306 INPUT TYPICAL FOR: CLK 5V 0.01F CA3306 50k

CA3306 INPUTS TYPICAL FOR: PHASE CE1 CE2

7406 OPEN COLLECTOR DRIVER CA3306 OUTPUTS TYPICAL FOR: B1 B2 B3 B4 B5 B6 OF

74LS04

CA3306

VDD

5V CD74HC 4049 (INV.), OR CD74HC4050 (NON-INV.), OR ANY LOW POWER SCHOTTKY TTL WITH HIGH INPUT VOLTAGE RATING (MANY LS DEVICES ARE RATED TO ACCEPT VOLTAGES UP TO 15V).

FIGURE 20. 5V LOGIC INTERFACE CIRCUIT FOR VDD > 5.5V

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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