Can Tutorial
Can Tutorial
Atmel Microcontrollers
CAN Tutorial
CAN Tutorial
® Agenda
Introduction or: What is CAN?
Why CAN?
CAN Protocol
CAN higher Layer Protocols
CAN Applications
Atmel CAN Microcontrollers Family
CAN Registers Details
Conclusion
Why CAN?
CAN Tutorial 16/03/2004 4
CAN Tutorial
® CAN Protocol
What is CAN? Frame Formats (1)
ISO-OSI Reference Model Frame Formats (2)
CAN Bus Logic Frame Formats (3)
Typical CAN Node Frame Formats (4)
CAN Bus Access and Fault Confinement (1)
Arbitration Fault Confinement (2)
CAN Bit Coding & Bit Undetected Errors
Stuffing
CAN Bus Synchronization
CAN Bit Construction
Relation between Baud Rate
and Bus Length
6. Presentation Layer
Partially implemented
5. Session Layer by Higher Layer
Protocols (HLP)
4. Transport Layer
3. Network Layer
“1” = recessive
Two logic states on
the CAN bus “0” = dominant
T89C51CC01/02
CAN_H
TxD Diff.
I/O CAN CAN
µController Line
Controller
RxD Driver CAN_L
CAN Bus
(terminated by 120 Ohm on each side)
TXd
TXd CANh
Dominant
CAN CAN CANh
Controller RXd Transceiver CANl Recessive
CANl
Dominant
RXd
Stub
Start of Frame
Arbitration Field
Node 1: TxD
Node 2: TxD
Node 3: TxD
CAN Bus
1 1 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 1 2 3 1 2 3 4
Data
Stream
Number of consecutive
$ = Staff Bits
bits with same polarity
$ $ $ CAN Bus
Bit Stream
1 1 1 2 3 4 5 1 1 2 3 4 5 1 2 3 4 5 1 1 1 2 3 1 2 3 4
SOF
Intermission / Idle ID10 ID9 ID8 ID7 ID6 ID5
1 Bit Time
8 to 25 Time Quanta
R
NRZ Signal
D
1 to16 tq
Sample Point
1000
500
200
Bit Rate
100
[kbps] 50
20
10
5
Bit Stuffing
SOF
ACK
del
del
Bus Frame ARBITRATION CTRL DATA CRC EOF IFS
SOF
RB0
IDE
RTR
CAN - V2.0A ID DLC DATA
RB1
RB0
CAN - V2.0B
RTR
SRR
IDE
ID[28..18] ID[17..0] DLC DATA
SOF Start of Frame EOF End of Frame RTR Remote Transmission Request
CRC Cyclic Redundancy Code IFS Inter Frame Spacing SRR Substitute Remote Request
del Delimiter ID Identifier RB0/1 Reserved bits
ACK Acknowledge IDE Identifier Extension DLC Data Length Code
SOF Start of Frame EOF End of Frame RTR Remote Transmission Request
CRC Cyclic Redundancy Code IFS Inter Frame Spacing SRR Substitute Remote Request
del Delimiter ID Identifier RB0/1 Reserved bits
ACK Acknowledge IDE Identifier Extension DLC Data Length Code
Bit Stuffing
SOF
ACK
del
del
ARBIT.* CTRL DATA CRC EOF IFS
Data Frame
1 12- 32 6 0…64 15 1 1 1 7 ≥3
Duration in Data Bit
(*) RTR = dominant
Bit Stuffing
SOF
ACK
del
del
Remote Frame ARBIT.* CTRL CRC EOF IFS
IFS or
Data Frame Superposition of Error Delimiter Overload
Error Flag Frame
Error Flag
Error Frame
Duration in Data Bit 6 6 8
Error Frame
Overload Frame
Re - Initialization only
CAN Protocol CAN Tutorial 16/03/2004 21
CAN Tutorial
® Fault Confinement (2)
y Cyclic Redundancy Check (CRC)
y The CRC is calculated over the non-stuffed bit stream
starting with the SOF and ending with the Data field by
the transmitting node
y The CRC is calculated again of the destuffed bit stream
by the receiving node
y A comparison of the received CRC and the calculated
CRC is made by the receiver
y In case of mismatch the erroneous data frame is
discarded . Instead of sending an acknowledge signal an
error frame is sent.
y Features
¾ Created by Honeywell
¾ Close to DeviveNet, CAL & CANopen
Building Automatisation
Domestic & Food distribution appliances
Automotive & Transportation
Robotic
Production Automatisation
Medical
Agriculture
s
annel
TimStmp (2) Ch. 0 - TimStmp (2) 15 Ch
(*) Number of Bytes
Status / Control
Registers
Host
CAN Bus
CPU
Interface CAN Host
Protocol Inter-
Controller Task / Message face
FIFO 0
Mask 0 Object 0
Task / Message
FIFO 1
Mask 1 Object 1
Task / Message
FIFO 14
Mask 14 Object 14
C51 X2 RAM
1.2K x 8
Core
Interrupt Unit
ADC Prog. Watchdog
10bit / 8 Channels Timer
Timers 0 / 1 / 2
PCA
5 Channels Port 0 8I/O
CAN
Port 4
Port 1 8I/O
Controller
15 Channels Port 2 8I/O
RAM
C51 X2 0.5K x 8
Core
Interrupt Unit
ADC Prog. Watchdog
10bit / 8 Channels Timer
Timers 0 / 1 / 2
PCA
2 Channels
Port 1 8I/O
CAN
Port 4
Port 2
1 2I/O
Controller
Port 3 8I/O
4 Channels
Emulation Test
Support Logic Support Logic
Port 4
CAN Controller
y 3 volts to 5.5 volts 15 Message
Objects
Port 2
bootloader
Packages: TQFP44, PLCC44, BGA8*8
y PLCC44, VQFP44, BGA64,
PLCC52(*) VQFP64(*) packages
(*) with SPI interface
y Performance:
¾ Processing Speed: 16MIPS AVR RISC Core
¾ 128KB Flash Program Memory; 4KB EEPROM; 4KB RAM
¾ V2.0A/B CAN Controller: Mail Box Message management up to 15 dynamic
messages at the same time
y Flexibility:
¾ Self-Programming Memory
9 Remote Programming or Field Upgrade
9 Read While Write
9 Lock Bit/Brownout Protection
9 Variable Boot Block Size: 1 to 8KB
y Higher Layer Protocol Software: CANopen and DeviceNetTM from Tool
Vendors Partners
y Hardware Multiplier
y IEEE 1149.1 Compliant JTAG Interface
y Atmel Commitment to CAN Networking: a Complete CAN
Microcontroller Family
CAN REGISTERS
C51 base Core
CAN Registers
CAN Tutorial
® C51 CAN General registers (1)
CANBT1
CANBT2
CANBT3
CANGCON
CANGSTA
- OVFG - TBSY RBSY ENFG BOFF ERRP
OVFG : Overload Frame Flag (set while the overload frame is sent. No IT)
TBSY : Transmitter Busy (Set while a transmission is in progress)
RBSY : Receive Busy (set while a reception is in progress)
ENFG : Enable On Chip CAN controller Flag. Cleared after completion of
on going transmit or receive after ENA has been cleared in CANGCON
BOFF : Bus Off indication
ERRP : Error Passive indication
CANGIT
CANIT - OVRTIM OVRBUF SERG CERG FERG AERG
General Interrupt
CANGIE
- - ENRX ENTX ENERCH ENBUF ENERG -
CANEN1
- ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8
CANEN2
ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0
CANSIT1
- SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8
CANSIT2
SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0
CANIE1
- IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8
CANIE2
IECH7 IECH6 IECH5 IECH4 IECH3 IECH2 IECH1 IECH0
CANTEC
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
CANREC
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
CANPAGE
CANCONCH
CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0
CONCH : 00 Disable
01 Transmit
10 Receive
11 Receive Buffer
RPLV : Automatic reply (0 to reply not ready, 1 to reply ready)
IDE : 0 for CAN2.0A (11 bit Identifier)
1 for CAN2.0B (29 bit identifier)
DLC : Data length code (0 to 8) indicate the number of valid Bytes
expected from a received message. Give number of valid byte to
transmit for a transmit message.
CANSTCH
DLCW TXOK RXOK BERR SERR CERR FERR AERR
CANIDT1
IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 IDT4 IDT3
CANIDT2
IDT2 IDT1 IDT0 - - - - -
CANIDT3
- - - - - - - -
CANIDT4
- - - - - RTRTAG - RBOTAG
CANIDT1
IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21
CANIDT2
IDT20 IDT19 IDT18 IDT17 IDT16 IDT15 IDT14 IDT13
CANIDT3
IDT12 IDT11 IDT10 IDT9 IDT8 IDT7 IDT6 IDT5
CANIDT4
IDT4 IDT3 IDT2 IDT1 IDT0 RTRTAG RB1TAG RBOTAG
CANIDM1
IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 IDMSK4 IDMSK3
CANIDM2
IDMSK2 IDMSK1 IDMSK0 - - - - -
CANIDM3
- - - - - - - -
CANIDM4
- - - - - RTRMSK - IDEMSK
CANIDM1
IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21
CANIDM2
IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13
CANIDM3
IDMSK12 IDMSK11 IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5
CANIDM4
IDMSK4 IDMSK3 IDMSK2 IDMSK1 IDMSK0 RTRMSK - IDEMSK
CANMSG
MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0
CANTCON
CANTIMH
CANTIML
CAN general timer (16 bit) receives clock from the prescaller CANTCON
CANSTAMPH
CANSTAMPL
CANTTCH
CANTTCL
CAN REGISTERS
AVR base Core
CAN Registers
CAN Tutorial
® AVR CAN Memory
CANBT2
CANBT3
CANGCON
CANGSTA
- OVFG - TXBSY RXBSY ENFG BOFF ERRP
OVFG : Overload Frame Flag (set while the overload frame is sent.
No IT)
TXBSY : Transmitter Busy (Set while a transmission is in progress)
RXBSY : Receive Busy (set while a reception is in progress)
ENFG : Enable On Chip CAN controller Flag. Cleared after
completion of on going transmit or receive after ENA has been
cleared in CANGCON
BOFF : Bus Off indication
ERRP : Error Passive indication
CANGIT
CANIT BOFFIT OVRTIM BXOK SERG CERG FERG AERG
General Interrupt
CANGIE
ENIT ENBOFF ENRX ENTX ENERR ENBX ENERG ENOVRT
CANEN1
- ENMOB14 ENMOB13 ENMOB12 ENMOB11 ENMOB10 ENMOB9 ENMOB8
CANEN2
ENMOB7 ENMOB6 ENMOB5 ENMOB4 ENMOB3 ENMOB2 ENMOB1 ENMOB0
CANSIT1
- SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8
CANSIT2
SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0
CANIE1
- IEMOB14 IEMOB13 IEMOB12 IEMOB11 IEMOB10 IEMOB9 IEMOB8
CANIE2
IEMOB7 IEMOB6 IEMOB5 IEMOB4 IEMOB3 IEMOB2 IEMOB1 IEMOB0
CANTEC
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
CANREC
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
CANPAGE
CANHPMOB
CANCDMOB
CONMOB1 CONMOB0 RPLV IDE DLC3 DLC2 DLC1 DLC0
CONMOB : 00 Disable
01 Enable Transmit
10 Enable Receive
11 Enable Receive Frame Buffer
RPLV : Automatic reply (0 to reply not ready, 1 to reply ready)
IDE : 0 for CAN2.0A (11 bit Identifier)
1 for CAN2.0B (29 bit identifier)
DLC : Data length code (0 to 8) indicate the number of valid Bytes
expected from a received message. Give number of valid byte to
transmit for a transmit message.
CANSTMOB
DLCW TXOK RXOK BERR SERR CERR FERR AERR
CANIDT1
IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 IDT4 IDT3
CANIDT2
IDT2 IDT1 IDT0 - - - - -
CANIDT3
- - - - - - - -
CANIDT4
- - - - - RTRTAG - RB0TAG
CANIDT1
IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21
CANIDT2
IDT20 IDT19 IDT18 IDT17 IDT16 IDT15 IDT14 IDT13
CANIDT3
IDT12 IDT11 IDT10 IDT9 IDT8 IDT7 IDT6 IDT5
CANIDT4
IDT4 IDT3 IDT2 IDT1 IDT0 RTRTAG RB1TAG RB0TAG
CANIDM1
IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 IDMSK4 IDMSK3
CANIDM2
IDMSK2 IDMSK1 IDMSK0 - - - - -
CANIDM3
- - - - - - - -
CANIDM4
- - - - - RTRMSK - IDEMSK
CANIDM1
IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21
CANIDM2
IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13
CANIDM3
IDMSK12 IDMSK11 IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5
CANIDM4
IDMSK4 IDMSK3 IDMSK2 IDMSK1 IDMSK0 RTRMSK - IDEMSK
CANMSG
MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0
CANTCON
CANTIMH
CANTIML
CAN general timer (16 bit) receives clock from the prescaller CANTCON
CANSTAMPH
CANSTAMPL
CANTTCH
CANTTCL
See the AT90CAN128 Software driver for source code. Above is only a
commented example.