14-Bit, 160 Msps 2 Interpolating Dual Txdac+: Ⴛ/4Ⴛ/8Ⴛ D/A Converter

AD9775
*
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved.
14-Bit, 160 MSPS 2/4/8
Interpolating Dual TxDAC+
D/A Converter
FUNCTIONAL BLOCK DIAGRAM
DIFFERENTIAL
CLK
COS
SIN
HALF-
BAND
FILTER 1
16
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
I AND Q
NONINTERLEAVED
OR
INTERLEAVED
DATA
WRITE
SELECT
CLOCK OUT
HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
*
GAIN
DAC
OFFSET
DAC
f
DAC
/2, 4, 8
SIN
COS
I/Q DAC
GAIN/OFFSET
REGISTERS
I
O
F
F
S
E
T
V
R
E
F
(f
DAC
)
PHASE DETECTOR
AND VCO
PRESCALER
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
16 16
/2
16
DATA
ASSEMBLER
16 16
16 16
14
14
MUX
CONTROL
/2
/2
I
LATCH
Q
LATCH
/2
HALF-
BAND
FILTER 2
HALF-
BAND
FILTER 3
* * *
AD9775
SPI INTERFACE AND
CONTROL REGISTERS
FILTER
BYPASS
MUX
IDAC
IDAC I
OUT
FEATURES
14-Bit Resolution, 160 MSPS/400 MSPS Input/Output
Data Rate
Selectable 2/4/8 Interpolating Filter
Programmable Channel Gain and Offset Adjustment
f
S
/4, f
S
/8 Digital Quadrature Modulation Capability
Direct IF Transmission Mode +or 70 MHz + IFs
Enables Image Rejection Architecture
Fully Compatible SPI Port
Excellent AC Performance
SFDR 71 dBc @ 2 MHz to 35 MHz
WCDMA ACPR 71 dB @ IF = 19.2 MHz
Internal PLL Clock Multiplier
Selectable Internal Clock Divider
Versatile Clock Input
Differential/Single-Ended Sine Wave or
TTL/CMOS/LVPECL Compatible
Versatile Input Data Interface
Twos Complement/Straight Binary Data Coding
Dual-Port or Single-Port Interleaved Input Data
Single 3.3 V Supply Operation
Power Dissipation: Typical 1.2 W @ 3.3 V
On-Chip 1.2 V Reference
80-Lead Thermally Enhanced TQFP Package
GENERAL DESCRIPTION
The AD9775 is the 14-bit member of the AD977x pin compatible,
high performance, programmable 2/4/8 interpolating TxDAC+
family. The AD977x family features a serial port interface (SPI)
that provides a high level of programmability, thus allowing for
enhanced system-level options. These options include select-
able 2/4/8 interpolation filters; f
S
/2, f
S
/4, or f
S
/8 digital
quadrature modulation with image rejection; a direct IF mode;
programmable channel gain and offset control; programmable
internal clock divider; straight binary or twos complement data
interface; and a single-port or dual-port data interface.
The selectable 2/4/8 interpolation filters simplify the require-
ments of the reconstruction filters while simultaneously enhancing
the TxDAC+ familys pass-band noise/distortion performance.
The independent channel gain and offset adjust registers allow
the user to calibrate LO feedthrough and sideband suppression
(continued on page 2)
APPLICATIONS
Communications
Analog Quadrature Modulation Architectures
3G, Multicarrier GSM, TDMA, CDMA Systems
Broadband Wireless, Point-to-Point Microwave Radios
Instrumentation/ATE
*Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Other patents pending.
REV. B
AD9775
2
(continued from page 1)
errors associated with analog quadrature modulators. The 6 dB
of gain adjustment range can also be used to control the output
power level of each DAC.
The AD9775 features the ability to perform f
S
/2, f
S
/4, and f
S
/8
digital modulation and image rejection when combined with an
analog quadrature modulator. In this mode, the AD9775 accepts
I and Q complex data (representing a single or multicarrier wave-
form), generates a quadrature modulated IF signal along with its
orthogonal representation via its dual DACs, and presents these
two reconstructed orthogonal IF carriers to an analog quadra-
ture modulator to complete the image rejection upconversion
process. Another digital modulation mode (i.e., the Direct IF
Mode) allows the original baseband signal representation to be
frequency translated such that pairs of images fall at multiples of
one-half the DAC update rate.
The AD977x family includes a flexible clock interface accepting
differential or single-ended sine wave or digital logic inputs. An
internal PLL clock multiplier is included and generates the
necessary on-chip high frequency clocks. It can also be disabled
to allow the use of a higher performance external clock source.
An internal programmable divider simplifies clock generation in
the converter when using an external clock source. A flexible data
input interface allows for straight binary or twos complement
formats and supports single-port interleaved or dual-port data.
Dual high performance DAC outputs provide a differential
current output programmable over a 2 mA to 20 mA range. The
AD9775 is manufactured on an advanced 0.35 micron CMOS
process, operates from a single supply of 3.1 V to 3.5 V, and
consumes 1.2 W of power.
Targeted at wide dynamic range, multicarrier and multistandard
systems, the superb baseband performance of the AD9775 is ideal
for wideband CDMA, multicarrier CDMA, multicarrier TDMA,
multicarrier GSM, and high performance systems employing
high order QAM modulation schemes. The image rejection
feature simplifies and can help to reduce the number of signal
band filters needed in a transmit signal chain. The direct IF
mode helps to eliminate a costly mixer stage for a variety of
communications systems.
PRODUCT HIGHLIGHTS
1. The AD9775 is the 14-bit member of the AD977x pin
compatible, high performance, programmable 2/4/8
interpolating TxDAC+ family.
2. Direct IF transmission capability for 70 MHz + IFs through
a novel digital mixing process.
3. f
S
/2, f
S
/4, and f
S
/8 digital quadrature modulation and user
selectable image rejection to simplify/remove cascaded
SAW filter stages.
4. A 2/4/8 user selectable interpolating filter eases data
rate and output signal reconstruction filter requirements.
5. User selectable twos complement/straight binary data
coding.
6. User programmable channel gain control over 1 dB
range in 0.01 dB increments.
7. User programmable channel offset control 10% over
the FSR.
8. Ultrahigh speed 400 MSPS DAC conversion rate.
9. Internal clock divider provides data rate clock for easy
interfacing.
10. Flexible clock input with single-ended or differential input,
CMOS, or 1 V p-p LO sine wave input capability.
11. Low power: Complete CMOS DAC operates on 1.2 W
from a 3.1 V to 3.5 V single supply. The 20 mA full-scale
current can be reduced for lower power operation and
several sleep functions are provided to reduce power dur-
ing idle periods.
12. On-chip voltage reference: The AD9775 includes a 1.20 V
temperature compensated band gap voltage reference.
13. 80-lead thermally enhanced TQFP.
REV. B 3
AD9775
DC SPECIFICATIONS
Parameter Min Typ Max Unit
RESOLUTION 14 Bits
DC Accuracy
1
Integral Nonlinearity 5 1.5 +5 LSB
Differential Nonlinearity 3 1.0 +3 LSB
ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)
Offset Error 0.02 0.01 +0.02 % of FSR
Gain Error (With Internal Reference) 1.0 +1.0 % of FSR
Gain Matching 1.0 0.1 +1.0 % of FSR
Full-Scale Output Current
2
2 20 mA
Output Compliance Range 1.0 +1.25 V
Output Resistance 200 k
Output Capacitance 3 pF
Gain, Offset Cal DACs, Monotonicity Guaranteed
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current
3
100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (REFLO = 3 V) 10 M
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/C
Gain Drift (With Internal Reference) 50 ppm of FSR/C
Reference Voltage Drift 50 ppm/C
POWER SUPPLY
AVDD
Voltage Range 3.1 3.3 3.5 V
Analog Supply Current (I
AVDD
)
4
72.5 76 mA
I
AVDD
in SLEEP Mode 23.3 26 mA
CLKVDD
Clock Supply Current (I
CLKVDD
)
4
8.5 10.0 mA
CLKVDD (PLL ON)
Clock Supply Current (I
CLKVDD
) 23.5 mA
DVDD
Digital Supply Current (I
DVDD
)
4
34 41 mA
Nominal Power Dissipation 380 410 mW
P
DIS
5
1.75 W
P
DIS
IN PWDN 6.0 mW
Power Supply Rejection RatioAVDD 0.4 % of FSR/V
OPERATING RANGE 40 +85 C
NOTES
1
Measured at I
OUTA
driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32 the I
REF
current.
3
Use an external amplifier to drive any external load.
4
100 MSPS f
DAC
with f
OUT
= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.
5
400 MSPS f
DAC
= 50 MSPS, f
S
/2 modulation, PLL enabled.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I
OUTFS
= 20 mA, unless
otherwise noted.)
AD9775SPECIFICATIONS
REV. B 4
AD9775
DYNAMIC SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I
OUTFS
= 20 mA,
Interpolation = 2, Differential Transformer-Coupled Output, 50 Doubly Terminated,
unless otherwise noted.)
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (f
DAC
) 400 MSPS
Output Settling Time (t
ST
) (to 0.025%) 11 ns
Output Rise Time (10% to 90%)* 0.8 ns
Output Fall Time (10% to 90%)* 0.8 ns
Output Noise (I
OUTFS
= 20 mA) 50 pA/Hz
AC LINEARITYBASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (f
OUT
= 0 dBFS)
f
DATA
= 100 MSPS, f
OUT
= 1 MHz 71 84.5 dBc
f
DATA
= 65 MSPS, f
OUT
= 1 MHz 84 dBc
f
DATA
= 65 MSPS, f
OUT
= 15 MHz 80 dBc
f
DATA
= 78 MSPS, f
OUT
= 1 MHz 84 dBc
f
DATA
= 78 MSPS, f
OUT
= 15 MHz 80 dBc
f
DATA
= 160 MSPS, f
OUT
= 1 MHz 82 dBc
f
DATA
= 160 MSPS, f
OUT
= 15 MHz 80 dBc
Spurious-Free Dynamic Range within a 1 MHz Window
(f
OUT
= 0 dBFS, f
DATA
= 100 MSPS, f
OUT
= 1 MHz) 73 91.3 dBc
Two-Tone Intermodulation (IMD) to Nyquist (f
OUT1
= f
OUT2
= 6 dBFS)
f
DATA
= 65 MSPS, f
OUT1
= 10 MHz; f
OUT2
= 11 MHz 81 dBc
f
DATA
= 65 MSPS, f
OUT1
= 20 MHz; f
OUT2
= 21 MHz 76 dBc
f
DATA
= 78 MSPS, f
OUT1
= 10 MHz; f
OUT2
= 11 MHz 81 dBc
f
DATA
= 78 MSPS, f
OUT1
= 20 MHz; f
OUT2
= 21 MHz 76 dBc
f
DATA
= 160 MSPS, f
OUT1
= 10 MHz; f
OUT2
= 11 MHz 81 dBc
f
DATA
= 160 MSPS, f
OUT1
= 20 MHz; f
OUT2
= 21 MHz 76 dBc
Total Harmonic Distortion (THD)
f
DATA
= 100 MSPS, f
OUT
= 1 MHz; 0 dBFS 71 82.5 dB
Signal-to-Noise Ratio (SNR)
f
DATA
= 78 MSPS, f
OUT
= 5 MHz; 0 dBFS 76 dB
f
DATA
= 160 MSPS, f
OUT
= 5 MHz; 0 dBFS 74 dB
Adjacent Channel Power Ratio (ACPR)
WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing
IF = Baseband, f
DATA
= 76.8 MSPS 71 dBc
IF = 19.2 MHz, f
DATA
= 76.8 MSPS 71 dBc
Four-Tone Intermodulation
21 MHz, 22 MHz, 23 MHz, and 24 MHz at 12 dBFS 75 dBFS
(f
DATA
= MSPS, Missing Center)
AC LINEARITYIF MODE
Four-Tone Intermodulation at IF = 200 MHz
201 MHz, 202 MHz, 203 MHz, and 204 MHz at 12 dBFS 72 dBFS
(f
DATA
= 160 MSPS, f
DAC
= 320 MHz)
*Measured single-ended into 50 load.
REV. B 5
AD9775
DIGITAL SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I
OUTFS
= 20 mA, unless
otherwise noted.)
DIGITAL INPUTS
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current 10 +10 A
Input Capacitance 5 pF
CLOCK INPUTS
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
SERIAL CONTROL BUS
Maximum SCLK Frequency (f
SLCK
) 15 MHz
Mimimum Clock Pulsewidth High (t
PWH
) 30 ns
Mimimum Clock Pulsewidth Low (t
PWL
) 30 ns
Maximum Clock Rise/Fall Time 1 ms
Minimum Data/Chip Select Setup Time (t
DS
) 25 ns
Minimum Data Hold Time (t
DH
) 0 ns
Maximum Data Valid Time (t
DV
) 30 ns
RESET Pulsewidth 1.5 ns
Inputs (SDI, SDIO, SCLK, CSB)
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Input Capacitance 5 pF
SDIO Output
Logic 1 Voltage DRVDD0.6 V
Logic 0 Voltage 0.4 V
Logic 1 Current 30 50 mA
Logic 0 Current 30 50 mA
REV. B
AD9775
6
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9775 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
Parameter With Respect To Min Max Unit
AVDD, DVDD, CLKVDD AGND, DGND, CLKGND 0.3 +4.0 V
AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD 4.0 +4.0 V
AGND, DGND, CLKGND AGND, DGND, CLKGND 0.3 +0.3 V
REFIO, REFLO, FSADJ1/2 AGND 0.3 AVDD + 0.3 V
I
OUTA
, I
OUTB
AGND 1.0 AVDD + 0.3 V
P1B13P1B0, P2B13P2B0 DGND 0.3 DVDD + 0.3 V
DATACLK, PLL_LOCK DGND 0.3 DVDD + 0.3 V
CLK+, CLK, RESET CLKGND 0.3 CLKVDD + 0.3 V
LPF CLKGND 0.3 CLKVDD + 0.3 V
SPI_CSB, SPI_CLK, DGND 0.3 DVDD + 0.3 V
SPI_SDIO, SPI_SDO
Junction Temperature 125 C
Storage Temperature 65 +150 C
Lead Temperature (10 sec) 300 C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option*
AD9775BSV 40C to +85C 80-Lead TQFP SV-80
AD9775EB Evaluation Board
*SV = Thin Plastic Quad Flatpack
THERMAL CHARACTERISTICS
Thermal Resistance
80-Lead Thermally Enhanced
TQFP Package
JA
= 23.5C/W*
*With thermal pad soldered to PCB.
REV. B 7
AD9775
PIN CONFIGURATION
80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17
18
20
19
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC = NO CONNECT
A
V
D
D
A
G
N
D
A
V
D
D
A
G
N
D
A
V
D
D
A
G
N
D
A
G
N
D
I
O
U
T
A
1
I
O
U
T
B
1
A
G
N
D
A
G
N
D
I
O
U
T
A
2
I
O
U
T
B
2
A
G
N
D
A
G
N
D
A
V
D
D
A
G
N
D
A
V
D
D
A
G
N
D
A
V
D
D
CLKVDD
LPF
CLKVDD
CLKGND
CLK+
CLK
DATACLK/PLL_LOCK
DGND
DVDD
P1B13 (MSB)
P1B12
P1B11
P1B10
P1B9
P1B8
DGND
DVDD
P1B7
P1B6
FSADJ1
FSADJ2
REFIO
RESET
SPI_CSB
SPI_CLK
SPI_SDIO
SPI_SDO
DGND
DVDD
NC
NC
P2B0 (LSB)
P2B1
P2B2
P2B3
P
1
B
5
P
1
B
4
P
1
B
3
P
1
B
2
D
G
N
D
D
V
D
D
P
1
B
1
P
1
B
0

(
L
S
B
)
N
C
N
C
O
N
E
P
O
R
T
C
L
K
/
P
2
B
1
2
P
2
B
1
1
P
2
B
1
0
D
G
N
D
D
V
D
D
I
Q
S
E
L
/
P
2
B
1
3

(
M
S
B
)
AD9775
TxDAC+
DGND
DVDD
P2B4
P2B5
P
2
B
9
P
2
B
8
P
2
B
7
P
2
B
6
CLKGND
PIN FUNCTION DESCRIPTIONS
Pin Number Mnemonic Description
1, 3 CLKVDD Clock Supply Voltage
2 LPF PLL Loop Filter
4, 7 CLKGND Clock Supply Common
5 CLK+ Differential Clock Input
6 CLK Differential Clock Input
8 DATACLK/PLL_LOCK With the PLL enabled, this pin indicates the state of the PLL. A read of a
Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the
PLL has not achieved lock. This pin may also be programmed to act as
either an input or output (Address 02h, Bit 3) DATACLK signal running at
the input data rate.
9, 17, 25, 35, 44, 52 DGND Digital Common
10, 18, 26, 36, 43, 51 DVDD Digital Supply Voltage
1116, 1924, 27, 28 P1B13 (MSB) to P1B0 (LSB) Port 1 Data Inputs
29, 30, 49, 50 NC No Connect
31 IQSEL/P2B13 (MSB) In one port mode, IQSEL = 1 followed by a rising edge of the differential
input clock will latch the data into the I channel input register. IQSEL = 0
will latch the data into the Q channel input register. In two port mode, this
pin becomes the Port 2 MSB.
32 ONEPORTCLK/P2B12 With the PLL disabled and the AD9775 in one port mode, this pin becomes
a clock output that runs at twice the input data rate of the I and Q channels.
This allows the AD9775 to accept and demux interleaved I and Q data to
the I and Q input registers.
33, 34, 3742, 4548 P2B11 to P2B0 (LSB) Port 2 Data Inputs
REV. B
AD9775
8
PIN FUNCTION DESCRIPTIONS (continued)
Pin Number Mnemonic Description
53 SPI_SDO In the case where SDIO is an input, SDO acts as an output. When SDIO
becomes an output, SDO enters a High-Z state. This pin can also be used as
an output for the data rate clock. For more information, see the Two Port
Data Input Mode section.
54 SPI_SDIO Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register
Address 00h. The default setting for this bit is 0, which sets SDIO as an input.
55 SPI_CLK Data input to the SPI port is registered on the rising edge of SPI_CLK.
Data output on the SPI port is registered on the falling edge.
56 SPI_CSB Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI
port logic and initializes instruction cycle.
57 RESET Logic 1 resets all of the SPI port registers, including Address 00h, to their
default values. A software reset can also be done by writing a Logic 1 to
SPI Register 00h, Bit 5. However, the software reset has no effect on the bits
in Address 00h.
58 REFIO Reference Output, 1.2 V Nominal
59 FSADJ2 Full-Scale Current Adjust, Q Channel
60 FSADJ1 Full-Scale Current Adjust, I Channel
61, 63, 65, 76, 78, 80 AVDD Analog Supply Voltage
62, 64, 66, 67, 70, 71, AGND Analog Common
74, 75, 77, 79
69, 68 I
OUTA2
, I
OUTB2
Differential DAC Current Outputs, Q Channel
73, 72 I
OUTA1
, I
OUTB1
Differential DAC Current Outputs, I Channel
REV. B
AD9775
9
DIGITAL FILTER SPECIFICATIONS
Half-Band Filter No. 1 (43 Coefficients)
Tap Coefficient
1, 43 8
2, 42 0
3, 41 29
4, 40 0
5, 39 67
6, 38 0
7, 37 134
8, 36 0
9, 35 244
10, 34 0
11, 33 414
12, 32 0
13, 31 673
14, 30 0
15, 29 1079
16, 28 0
17, 27 1772
18, 26 0
19, 25 3280
20, 24 0
21, 23 10364
22 16384
Tap Coefficient
1, 19 19
2, 18 0
3, 17 120
4, 16 0
5, 15 438
6, 14 0
7, 13 1288
8, 12 0
9, 11 5047
10 8192
Tap Coefficient
1, 11 7
2, 10 0
3, 9 53
4, 8 0
5, 7 302
6 512
f
OUT
Normalized to Input Data Rate
120
0 0.5
A
T
T
E
N
U
A
T
I
O
N

d
B
F
S
100
80
60
40
20
0
20
1.0 1.5 2.0
Figure 1a. 2 Interpolating Filter Response
f
OUT
120
0 0.5
A
T
T
E
N
U
A
T
I
O
N

d
B
F
S
100
80
60
40
20
0
20
1.0 1.5 2.0
Figure 1b. 4 Interpolating Filter Response
f
OUT
120
0 2
A
T
T
E
N
U
A
T
I
O
N

d
B
F
S
100
80
60
40
20
0
20
4 6 8
Figure 1c. 8 Interpolating Filter Response
REV. B
AD9775
10
DEFINITIONS OF SPECIFICATIONS
Adjacent Channel Power Ratio (ACPR)
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images are redundant
and have the effect of wasting transmitter power and system
bandwidth. By placing the real part of a second complex modu-
lator in series with the first complex modulator, either the upper
or lower frequency image near the second IF can be rejected.
Complex Modulation
The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = e
jt
=
cost + jsint) and realizing real and imaginary components on
the modulator output.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1, minus the output when all inputs are set to 0.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Group Delay
Number of input clocks between an impulse applied at the
device input and the peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range.
Impulse Response
Response of the device to an impulse applied to the input.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
f
DATA
(interpolation rate), a digital filter can be constructed
with a sharp transition band near f
DATA
/2. Images that would
typically appear around f
DAC
(output data rate) can be greatly
suppressed.
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of 0 is
called offset error. For I
OUTA
, 0 mA output is expected when the
inputs are all 0. For I
OUTB
, 0 mA output is expected when all
inputs are set to 1.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Pass Band
Frequency band in which any input applied therein passes
unattenuated to the DAC output.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Stop-Band Rejection
The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per C. For reference drift, the drift is reported in
ppm per C.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
REV. B 11
AD9775
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
90
0 65 130
80
70
60
50
40
30
20
10
0
10
TPC 1. Single-Tone Spectrum
@ f
DATA
= 65 MSPS with
f
OUT
= f
DATA
/3
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
90
0 50 150
80
70
60
50
40
30
20
10
0
10
100
@ f
DATA
= 78 MSPS with
f
OUT
= f
DATA
/3
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
90
0 100 300
80
70
60
50
40
30
20
10
0
10
200
@ f
DATA
= 160 MSPS with
f
OUT
= f
DATA
/3
FREQUENCY MHz
S
F
D
R

d
B
c
50
0 20 30
55
60
65
70
75
80
85
90
10 15 25 5
12dBFS
6dBFS
0dBFS
TPC 2. In-Band SFDR vs. f
OUT
@ f
DATA
= 65 MSPS
FREQUENCY MHz
S
F
D
R

d
B
c
50
0 20 30
55
60
65
70
75
80
85
90
10 15 25 5
6dBFS
12dBFS
0dBFS
OUT
@ f
DATA
= 78 MSPS
FREQUENCY MHz
S
F
D
R

d
B
c
50
0 20 30
55
60
65
70
75
80
85
90
10
6dBFS
12dBFS
0dBFS
40 50
OUT
@ f
DATA
= 160 MSPS
FREQUENCY MHz
S
F
D
R

d
B
c
50
0 20 30
55
60
65
70
75
80
85
90
10 15 25 5
12dBFS
0dBFS
6dBFS
TPC 3. Out-of-Band SFDR vs.
f
OUT
@ f
DATA
= 65 MSPS
FREQUENCY MHz
S
F
D
R

d
B
c
50
0 20 30
55
60
65
70
75
80
85
90
10 15 25 5
12dBFS
0dBFS
6dBFS
f
OUT
@ f
DATA
= 78 MSPS
FREQUENCY MHz
S
F
D
R

d
B
c
50
0 20 30
55
60
65
70
75
80
85
90
10
6dBFS
12dBFS
0dBFS
40 50
f
OUT
@ f
DATA
= 160 MSPS
(T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I
OUTFS
= 20 mA, Interpolation = 2, Differential Transformer Coupled Output, 50
Doubly Terminated, unless otherwise noted.)
Typical Performance Characteristics
REV. B
AD9775
12
FREQUENCY MHz
I
M
D

d
B
c
50
0 20 30
55
60
65
70
75
80
85
90
10 15 25 5
0dBFS
3dBFS
6dBFS
TPC 10. Third Order IMD Products
vs. f
OUT
@ f
DATA
= 65 MSPS
FREQUENCY MHz
I
M
D

d
B
c
50
0 40 60
55
60
65
70
75
80
85
90
20
8
4
1
2
30 55 10
vs. f
OUT
and Interpolation Rate,
1 f
DATA
= 160 MSPS
2 f
DATA
= 160 MSPS
4 f
DATA
= 80 MSPS
8 f
DATA
= 50 MSPS
AVDD V
S
F
D
R

d
B
c
50
3.5
55
60
65
70
75
80
85
90
0dBFS
3.4 3.3 3.2 3.1
3dBFS
6dBFS
vs. AVDD @ f
OUT
= 10 MHz, f
DAC
=
320 MSPS, f
DATA
= 160 MSPS
FREQUENCY MHz
I
M
D

d
B
c
50
0 20 30
55
60
65
70
75
80
85
90
10 15 25 5
3dBFS
0dBFS
6dBFS
vs. f
OUT
@ f
DATA
= 78 MSPS
A
OUT
dBFS
I
M
D

d
B
c
50
5 0
55
60
65
70
75
80
85
90
10
8
4
1
2
15
vs. A
OUT
and Interpolation Rate f
DATA
= 50 MSPS for All Cases,
1 f
DAC
= 50 MSPS
2 f
DAC
= 100 MSPS
4 f
DAC
= 200 MSPS
8 f
DAC
= 400 MSPS
S
N
R

d
B
55
60
65
70
75
80
85
90
INPUT DATA RATE MSPS
0 50 150 100
50
PLL ON
PLL OFF
TPC 17. SNR vs. Data Rate for
f
OUT
= 5 MHz
FREQUENCY MHz
I
M
D

d
B
c
50
0 40 60
55
60
65
70
75
80
85
90
20 30 50 10
3dBFS
0dBFS
6dBFS
vs. f
OUT
@ f
DATA
= 160 MSPS
AVDD V
S
F
D
R

d
B
c
50
3.5
55
60
65
70
75
80
85
90
0dBFS
3.4 3.3 3.2 3.1
6dBFS 12dBFS
TPC 15. SFDR vs. AVDD @
f
OUT
= 10 MHz, f
DAC
= 320 MSPS,
f
DATA
= 160 MSPS
TEMPERATURE C
S
F
D
R

d
B
c
90
85
50
50 0 100 50
70
65
55
60
80
75
f
DATA
= 65MSPS
160MSPS
78MSPS
TPC 18. SFDR vs. Temperature
@ f
OUT
= f
DATA
/11
REV. B 13
AD9775
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
0
10
100
0 50 150 100
70
90
80
50
60
20
40
30
TPC 19. Single-Tone Spurious
Performance, f
OUT
= 10 MHz,
f
DATA
= 150 MSPS, No Interpolation
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
0
20
100
0 5 50 10 15 20 25 30 35 40 45
40
60
80
10
30
50
40
90
TPC 22. Two-Tone IMD Performance,
f
DATA
= 150 MSPS, Interpolation = 4
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
0
10
100
0 100 400 200 300
60
70
80
90
20
30
40
50
Performance, f
OUT
= 10 MHz,
f
DATA
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
0
20
100
0 10 50 20 30 40
40
60
80
f
DATA
= 150 MSPS, No Interpolation
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
0
100
0 50 300 100 150 200 250
10
60
70
80
90
20
30
50
40
Performance, f
OUT
= 10 MHz,
f
DATA
0
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
120
0 20 80 40 60
40
60
80
100
20
TPC 26. Eight-Tone IMD
Performance, f
DATA
= 160 MSPS,
Interpolation = 8
FREQUENCY MHz
A
M
P
L
I
F
I
E
R

d
B
m
0
100
0 50 300 100 150 200 250
10
60
70
80
90
20
30
50
40
Performance, f
OUT
= 10 MHz,
f
DATA
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
0
20
100
0 5 25 10 15 20
40
60
80
10
30
50
70
90
f
OUT
= 10 MHz, f
DATA
= 50 MSPS,
Interpolation = 8
REV. B
AD9775
14
MODE CONTROL (VIA SPI PORT)
Table I. Mode Control via SPI Port
(Default Values Are Highlighted)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h SDIO LSB, MSB First Software Reset on Sleep Mode Power-Down Mode 1R/2R Mode PLL_LOCK
Bidirectional 0 = MSB Logic 1 Logic 1 shuts down Logic 1 shuts down DAC output current set Indicator
0 = Input 1 = LSB the DAC output all digital and analog by one or two external
1 = I/O currents. functions. resistors.
0 = 2R, 1 = 1R
01h Filter Filter Modulation Modulation Mode 0 = No Zero Stuffing 1 = Real Mix Mode 0 = e
jt
DATACLK/
Interpolation Interpolation Mode (None, f
S
/2, f
S
/4, f
S
/8) on Interpolation 0 = Complex 1 = e
+jt
PLL_LOCK*
Rate Rate (None, f
S
/2, Filters, Logic 1 Mix Mode Select
(1, 2, 4, 8) (1, 2, 4, 8) f
S
/4, f
S
/8) enables zero stuffing. 0 = PLLLOCK
1 = DATACLK
02h 0 = Signed Input 0 = Two Port Mode DATACLK Driver DATACLK Invert ONEPORTCLK Invert IQSEL Invert Q First
Data 1 = One Port Mode Strength 0 = No Invert 0 = No Invert 0 = No Invert 0 = I First
1 = Unsigned 1 = Invert 1 = Invert 1 = Invert 1 = Q First
03h Data Rate PLL Divide PLL Divide
Clock Output* (Prescaler) Ratio (Prescaler) Ratio
04h 0 = PLL OFF* 0 = Automatic PLL Charge Pump PLL Charge Pump PLL Charge Pump
1 = PLL ON Charge Pump Control Control Control Control
1 = Programmable
05h IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain
Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment
06h IDAC Coarse Gain IDAC Coarse Gain IDAC Coarse Gain IDAC Coarse Gain
Adjustment Adjustment Adjustment Adjustment
07h IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset
Adjustment Bit 9 Adjustment Bit 8 Adjustment Bit 7 Adjustment Bit 6 Adjustment Bit 5 Adjustment Bit 4 Adjustment Bit 3 Adjustment Bit 2
08h IDAC I
OFFSET
IDAC Offset IDAC Offset
Direction Adjustment Bit 1 Adjustment Bit 0
0 = I
OFFSET
on I
OUTA
1 = I
OFFSET
on
I
OUTB
09h QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain
Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment
0Ah QDAC Coarse QDAC Coarse QDAC Coarse QDAC Coarse
Gain Adjustment Gain Adjustment Gain Adjustment Gain Adjustment
0Bh QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset
Adjustment Bit 9 Adjustment Bit 8 Adjustment Bit 7 Adjustment Bit 6 Adjustment Bit 5 Adjustment Bit 4 Adjustment Bit 3 Adjustment Bit 2
0Ch QDAC I
OFFSET
QDAC Offset QDAC Offset
Direction Adjustment Bit 1 Adjustment Bit 0
0 = I
OFFSET
on I
OUTA
1 = I
OFFSET
on I
OUTB
0Dh Version Register Version Register Version Register Version Register
*See the Two Port Data Input Mode section.
REV. B
AD9775
15
REGISTER DESCRIPTION
Address 00h
Bit 7 Logic 0 (default). Causes the SDIO pin to act as
an input during the data transfer (Phase 2) of the
communications cycle. When set to 1, SDIO
can act as an input or output, depending on Bit 7 of
the instruction byte.
Bit 6 Logic 0 (default). Determines the direction
(LSB/MSB first) of the communications and data
transfer communications cycles. Refer to the MSB/
LSB Transfers section for a detailed description.
Bit 5 Writing a 1 to this bit resets the registers to their
default values and restarts the chip. The RESET bit
always reads back 0. Register Address 00h bits are
not cleared by this software reset. However, a high
level at the RESET pin forces all registers, including
those in Address 00h, to their default state.
Bit 4 Sleep Mode. A Logic 1 to this bit shuts down the
DAC output currents.
Bit 3 Power-Down. Logic 1 shuts down all analog and
digital functions except for the SPI port.
Bit 2 1R/2R Mode. The default (0) places the AD9775
in two resistor mode. In this mode, the I
REF
currents
for the I and Q DAC references are set separately by
the R
SET
resistors on FSADJ1 and FSADJ2 (Pins
59 and 60). In 2R mode, assuming the coarse
gain setting is full scale and the fine gain setting is
zero, I
FULLSCALE1
= 32 V
REF
/FSADJ1 and
I
FULLSCALE2
= 32 V
REF
/FSADJ2. With this bit set
to 1, the reference currents for both I and Q
DACs are controlled by a single resistor on Pin 60.
I
FULLSCALE
in one resistor mode for both of the I
and Q DACs is half of what it would be in 2R mode,
assuming all other conditions (R
SET
, register settings)
remain unchanged. The full-scale current of each
DAC can still be set to 20 mA by choosing a resistor
of half the value of the R
SET
value used in 2R mode.
Bit 1 PLL_LOCK Indicator. When the PLL is enabled,
reading this bit will give the status of the PLL. A
Logic 1 indicates the PLL is locked. A Logic 0
indicates an unlocked state.
Address 01h
Bits 7, 6 Filter interpolation rate according to the follow-
ing table:
00 1
01 2
10 4
11 8
Bits 5, 4 Modulation mode according to the following table:
00 none
01 f
S
/2
10 f
S
/4
11 f
S
/8
Bit 3 Logic 1 enables zero stuffing mode for interpo-
lation filters.
Bit 2 Default (1) enables the real mix mode. The I and
Q data channels are individually modulated by f
S
/2,
f
S
/4, or f
S
/8 after the interpolation filters. However, no
complex modulation is done. In the complex mix
mode (Logic 0), the digital modulators on the I
and Q data channels are coupled to create a digi-
tal complex modulator. When the AD9775 is
applied in conjunction with an external quadrature
modulator, rejection can be achieved of either the
higher or lower frequency image around the second
IF frequency (i.e., the LO of the analog quadrature
modulator external to the AD9775) according to
the bit value of Register 01h, Bit 1.
Bit 1 Logic 0 (default) causes the complex modulation
to be of the form e
jt
, resulting in the rejection of
the higher frequency image when the AD9775 is used
with an external quadrature modulator. A Logic 1
causes the modulation to be of the form e
+jt
, which
causes rejection of the lower frequency image.
Bit 0 In two port mode, a Logic 0 (default) causes Pin 8
to act as a lock indicator for the internal PLL. A
Logic 1 in this register causes Pin 8 to act as a
DATACLK. For more information, see the Two
Port Data Input Mode section.
Address 02h
Bit 7 Logic 0 (default) causes data to be accepted on
the inputs as twos complement binary. Logic 1
causes data to be accepted as straight binary.
Bit 6 Logic 0 (default) places the AD9775 in two port
mode. I and Q data enters the AD9775 via Ports 1
and 2, respectively. A Logic 1 places the AD9775
in one port mode in which interleaved I and Q data
is applied to Port 1. See the Pin Function Descrip-
tions for DATACLK/PLL_LOCK, IQSEL, and
ONEPORTCLK for detailed information on how
to use these modes.
Bit 5 DATACLK Driver Strength. With the internal PLL
disabled and this bit set to Logic 0, it is recom-
mended that DATACLK be buffered. When this bit
is set to Logic 1, DATACLK acts as a stronger
driver capable of driving small capacitive loads.
Bit 4 Default Logic 0. A value of 1 inverts DATACLK
at Pin 8.
Bit 2 Default Logic 0. A value of 1 inverts
ONEPORTCLK at Pin 32.
Bit 1 The default of Logic 0 causes IQSEL = 0 to
direct input data to the I channel, while IQSEL = 1
directs input data to the Q channel.
Bit 0 The default of Logic 0 defines IQ pairing as IQ,
IQ... while programming a Logic 1 causes the
pair ordering to be QI, QI...
REV. B
AD9775
16
Address 03h
Bit 7 Allows the data rate clock (divided down from the
DAC clock) to be output at either the DATACLK
pin (Pin 8), or at the SPI_SDO pin (Pin 53). The
default of 0 in this register will enable the data rate
clock at DATACLK, while a 1 in this register will
cause the data rate clock to be output at SPI_SDO.
For more information, see the Two Port Data Input
Mode section.
Bits 1, 0 Setting this divide ratio to a higher number allows
the VCO in the PLL to run at a high rate (for best
performance) while the DAC input and output clocks
run substantially slower. The divider ratio is set
according to the following table:
00 1
01 2
10 4
11 8
Address 04h
Bit 7 Logic 0 (default) disables the internal PLL. Logic
1 enables the PLL.
Bit 6 Logic 0 (default) sets the charge pump control to
automatic. In this mode, the charge pump bias
current is controlled by the divider ratio defined in
Address 03h, Bits 1 and 0. Logic 1 allows the
user to manually define the charge pump bias cur-
rent using Address 04h, Bits 2, 1, and 0. Adjusting
the charge pump bias current allows the user to
optimize the noise/settling performance of the PLL.
Bits 2, 1, 0 With the charge pump control set to manual, these
bits define the charge pump bias current according
to the following table:
000 50 A
001 100 A
010 200 A
011 400 A
111 800 A
Address 05h, 09h
Bits 70 These bits represent an 8-bit binary number (Bit 7
MSB) that defines the fine gain adjustment of the I
(05h) and Q (09h) DAC, according to Equation 1.
Address 06h, 0Ah
Bits 30 These bits represent a 4-bit binary number (Bit 3 MSB)
that defines the coarse gain adjustment of the I (06h)
and Q (0Ah) DACs according to Equation 1.
Address 07h, 0Bh
Bits 70 These bits are used in conjunction with address
08h, 0Ch, Bits 1, 0.
Address 08h, 0Ch
Bit 1, 0 The 10 bits from these two address pairs (07h, 08h
and 0Bh, 0Ch) represent a 10-bit binary number
that defines the offset adjustment of the I and Q
DACs according to Equation 1 (07h, 0BhBit 7
MSB/08h, 0ChBit 0 LSB)
Address 08h, 0Ch
Bit 7 This bit determines the direction of the offset of the
I (08h) and Q (0Ch) DACs. A Logic 0 will apply
a positive offset current to I
OUTA
, while a Logic 1
will apply a positive offset current to I
OUTB
. The
magnitude of the offset current is defined by the
bits in Addresses 07h, 0Bh, 08h, and 0Ch accord-
ing to Equation 1.
Equation 1 shows I
OUTA
and I
OUTB
as a function of fine gain,
coarse gain, and offset adjustment when using the 2R mode. In
1R mode, the current I
REF
is created by a single FSADJ resistor
(Pin 60). This current is divided equally into each channel so
that a scaling factor of one-half must be added to these equa-
tions for full-scale currents for both DACs and the offset.

I
I COARSE I FINE DATA
A
I
I COARSE I FINE
OUTA
REF REF
OUTB
REF REF
_
,
_
,
_
,
_
,
1
]
1

_
,
_
,
1
]
1( )
_
,
_
,
_
,
6
8
1
16
3
32 256
1024
24
2
6
8
1
16
3
32
14
256 256
1024
24
2 1
2
4
1024
14
14
_
,
1
]
1

_
,
_
,
1
]
1
1
( )

_
,
( )
DATA
A
I I
OFFSET
A
OFFSET REF
(1)
REV. B
AD9775
17
FUNCTIONAL DESCRIPTION
The AD9775 dual interpolating DAC consists of two data chan-
nels that can be operated completely independently or coupled to
form a complex modulator in an image reject transmit architec-
ture. Each channel includes three FIR filters, making the
AD9775 capable of 2, 4, or 8 interpolation. High speed input
and output data rates can be achieved within the following
limitations.
Interpolation Input Data DAC Sample
Rate (MSPS) Rate (MSPS) Rate (MSPS)
1 160 160
2 160 320
4 100 400
8 50 400
Both data channels contain a digital modulator capable of mix-
ing the data stream with an LO of f
DAC
/2, f
DAC
/4, or f
DAC
/8,
where f
DAC
is the output data rate of DAC. A zero stuffing fea-
ture is also included and can be used to improve pass-band
flatness for signals being attenuated by the SIN(x)/x characteristic
of the DAC output. The speed of the AD9775, combined with
the digital modulation capability, enables direct IF conversion
architectures at 70 MHz and higher.
The digital modulators on the AD9775 can be coupled to form
a complex modulator. By using this feature with an external analog
quadrature modulator, such as Analog Devices AD8345, an
image rejection architecture can be enabled. To optimize the
image rejection capability, as well as LO feedthrough in this
architecture, the AD9775 offers programmable (via the SPI port)
gain and offset adjust for each DAC.
Also included on the AD9775 are a phase-locked loop (PLL)
clock multiplier and a 1.20 V band gap voltage reference. With
the PLL enabled, a clock applied to the CLK+/CLK inputs is
frequency multiplied internally and generates all necessary
internal synchronization clocks. Each 14-bit DAC provides two
complementary current outputs whose full-scale currents can
be determined either from a single external resistor or indepen-
dently from two separate resistors (see the 1R/2R Mode section).
The AD9775 features a low jitter, differential clock input that
provides excellent noise rejection while accepting a sine or
square wave input. Separate voltage supply inputs are provided
for each functional block to ensure optimum noise and distor-
tion performance.
Sleep and power-down modes can be used to turn off the DAC
output current (sleep) or the entire digital and analog sections
(power-down) of the chip. An SPI compliant serial port is used
to program the many features of the AD9775. Note that in
power-down mode, the SPI port is the only section of the chip
still active.
AD9775 SPI PORT
INTERFACE
SCLK (PIN 55)
CSB (PIN 56)
SDIO (PIN 54)
SDO (PIN 53)
Figure 2. SPI Port Interface
SERIAL INTERFACE FOR REGISTER CONTROL
The AD9775 serial port is a flexible, synchronous serial
communications port that allows easy interface to many industry-
standard microcontrollers and microprocessors. The serial I/O
is compatible with most synchronous transfer formats, including
both the Motorola SPI and Intel SSR protocols. The interface
allows read/write access to all registers that configure the AD9775.
Single- or multiple-byte transfers are supported as well as MSB
first or LSB first transfer formats. The AD9775s serial interface
port can be configured as a single pin I/O (SDIO) or two unidi-
rectional pins for I/O (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9775.
Phase 1 is the instruction cycle, which is the writing of an instruc-
tion byte into the AD9775 coincident with the first eight SCLK
rising edges. The instruction byte provides the AD9775 serial
port controller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines whether the upcoming data transfer is
read or write, the number of bytes in the data transfer, and the
starting register address for the first byte of the data transfer.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9775.
A Logic 1 on the CSB pin, followed by a logic low, will reset
the SPI port timing to the initial state of the instruction cycle.
This is true regardless of the present state of the internal regis-
ters or the other signal levels present at the inputs to the SPI
port. If the SPI port is in the middle of an instruction cycle or a
data transfer cycle, none of the present data will be written.
The remaining SCLK edges are for Phase 2 of the communica-
tion cycle. Phase 2 is the actual data transfer between the AD9775
and the system controller. Phase 2 of the communication cycle
is a transfer of one to four data bytes as determined by the instruc-
tion byte. Normally, using one multibyte transfer is the preferred
method. However, single byte data transfers are useful to reduce
CPU overhead when register access requires one byte only.
Registers change immediately upon writing to the last bit of each
transfer byte.
INSTRUCTION BYTE
The instruction byte contains the information shown below.
N1 N0 Description
0 0 Transfer 1 Byte
0 1 Transfer 2 Bytes
R/W
Bit 7 of the instruction byte determines whether a read or a write
data transfer will occur after the instruction byte write. Logic 1
indicates read operation. Logic 0 indicates a write operation.
REV. B
AD9775
18
SDIO (Pin 54)Serial Data I/O
Data is always written into the AD9775 on this pin. However,
this pin can be used as a bidirectional data line. The configura-
tion of this pin is controlled by Bit 7 of Register Address 00h.
The default is Logic 0, which configures the SDIO pin as
unidirectional.
SDO (Pin 53)Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the AD9775
operates in a single bidirectional I/O mode, this pin does not
output data and is set to a high impedance state.
MSB/LSB TRANSFERS
The AD9775 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the LSB first bit in Register 0. The
default is MSB first.
When this bit is set active high, the AD9775 serial port is in
LSB first format. In LSB first mode, the instruction byte and data
bytes must be written from LSB to most significant bit. In LSB
first mode, the serial port internal byte address generator incre-
ments for each byte of the multibyte communication cycle.
When this bit is set default low, the AD9775 serial port is in
MSB first format. In MSB first mode, the instruction byte and
data bytes must be written from most significant bit to least
significant bit. In MSB first mode, the serial port internal byte
address generator decrements for each byte of the multibyte
communication cycle.
When incrementing from 1Fh, the address generator changes to
00h. When decrementing from 00h, the address generator changes
to 1Fh.
CS
SCLK
SDIO
SDO
DATA TRANSFER CYCLE INSTRUCTION CYCLE
R/W D7
N
I4 I3 I2 I1 I0 D6
N
D7
N
D6
N
D0
0
D1
0
D2
0
D0
0
D1
0
D2
0
I6 I5
(N) (N)
Figure 3a. Serial Register Interface Timing MSB First
CS
SCLK
SDIO
SDO
DATA TRANSFER CYCLE INSTRUCTION CYCLE
R/W I6 D7
N
I5 I4 I3 I2 I1 I0 D6
N
D7
N
D6
N
D0
0
D1
0
D2
0
D0
0
D1
0
D2
0
(N) (N)
Figure 3b. Serial Register Interface Timing LSB First
N1, N0
Bits 6 and 5 of the instruction byte determine the number of
bytes to be transferred during the data transfer cycle. The bit
decodes are shown in the following table:
MSB LSB
I7 I6 I5 I4 I3 I2 I1 I0
R/W N1 N0 A4 A3 A2 A1 A0
A4, A3, A2, A1, A0
Bits 4, 3, 2, 1, and 0 of the instruction byte determine which
register is accessed during the data transfer portion of the com-
munications cycle. For multibyte transfers, this address is the
starting byte address. The remaining register addresses are
generated by the AD9775.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK (Pin 55)Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9775 and to run the internal state machines. SCLK maxi-
mum frequency is 15 MHz. All data input to the AD9775 is
registered on the rising edge of SCLK. All data is driven out of
the AD9775 on the falling edge of SCLK.
CSB (Pin 56)Chip Select
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial com-
munications lines. The SDO and SDIO pins will go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
REV. B
AD9775
19
t
DS
t
SCLK
t
PWH
t
PWL
t
DS
t
DH
INSTRUCTION BIT 7 INSTRUCTION BIT 6
CS
SCLK
SDIO
Figure 4. Timing Diagram for Register Write to AD9775
t
DV
DATA BIT N DATA BIT N 1
CS
SCLK
SDIO
SDO
Figure 5. Timing Diagram for Register Read from AD9775
NOTES ON SERIAL PORT OPERATION
The AD9775 serial port configuration bits reside in Bits 6 and 7
of Register Address 00h. It is important to note that the configura-
tion changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register may occur dur-
ing the middle of the communication cycle. Care must be taken
to compensate for this new configuration for the remaining
bytes of the current communication cycle.
The same considerations apply to setting the reset bit in Register
Address 00h. All other registers are set to their default values, but
the software reset doesnt affect the bits in Register Address 00h.
It is recommended to use only single-byte transfers when chang-
ing serial port configurations or initiating a software reset.
A write to Bits 1, 2, and 3 of Address 00h with the same logic
levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary)
allows the user to reprogram a lost serial port configuration and
to reset the registers to their default values. A second write to
Address 00h with reset bit low and serial port configuration as
specified above (XY) reprograms the OSC IN multiplier set-
ting. A changed f
SYSCLK
frequency is stable after a maximum of
200 f
MCLK
cycles (equals wake-up time).
DAC OPERATION
The dual 14-bit DAC output of the AD9775, along with the
reference circuitry, gain, and offset registers, is shown in Figure 6.
Referring to the transfer functions in Equation 1, a reference
current is set by the internal 1.2 V reference, the external R
SET
resistor, and the values in the coarse gain register. The fine gain
DAC subtracts a small amount from this and the result is input
to IDAC and QDAC, where it is scaled by an amount equal
to 1024/24. Figures 7a and 7b show the scaling effect of the
coarse and fine adjust DACs. IDAC and QDAC are PMOS
current source arrays, segmented in a 5-4-5 configuration. The
5 MSB control an array of 31 current sources. The next four bits
consist of 15 current sources whose values are all equal to 1/16
of an MSB current source. The 5 LSBs are binary weighted
fractions of the middle bits current sources. All current sources are
switched to either I
OUTA
or I
OUTB
, depending on the input code.
The fine adjustment of the gain of each channel allows for
improved balance of QAM modulated signals, resulting in
improved modulation accuracy and image rejection. In the
Interfacing the AD9775 with the AD8345 Quadrature Modula-
tor section, the performance data shows to what degree image
rejection can be improved when the AD9775 is used with an
AD8345 quadrature modulator from ADI.
REV. B
AD9775
20
The offset control defines a small current that can be added to
I
OUTA
or I
OUTB
(not both) on the IDAC and QDAC. The selec-
tion of which I
OUT
this offset current is directed toward is
programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch,
Bit 7 (QDAC). Figure 8 shows the scale of the offset current
that can be added to one of the complementary outputs on the
IDAC and QDAC. Offset control can be used for suppression of
LO leakage resulting from modulation of dc signal components.
If the AD9775 is dc-coupled to an external modulator, this
feature can be used to cancel the output offset on the AD9775
as well as the input offset on the modulator. Figure 9 shows a
typical example of the effect that the offset control has on LO
suppression.
OFFSET
DAC
QDAC
IDAC
OFFSET
DAC
REFIO
0.1F
FSADJ1
FSADJ2
RSET1
RSET2
I
OUTA1
I
OUTB1
OFFSET
CONTROL
REGISTERS
I
OUTA2
I
OUTB2
GAIN
CONTROL
REGISTERS
COARSE
GAIN
DAC
COARSE
GAIN
DAC
FINE
GAIN
DAC
FINE
GAIN
DAC
1.2VREF
GAIN
CONTROL
REGISTERS
OFFSET
CONTROL
REGISTERS
Figure 6. DAC Outputs, Reference Current Scaling, and
Gain/Offset Adjust
COARSE GAIN REGISTER CODE Assuming
RSET1, 2 = 1.9k
0 5
C
O
A
R
S
E

R
E
F
E
R
E
N
C
E

C
U
R
R
E
N
T

m
A
0
25
10 15 20
5
10
15
20
2R MODE
1R MODE
Figure 7a. Coarse Gain Effect on I
FULLSCALE
FINE GAIN REGISTER CODE Assuming
RSET1, 2 = 1.9k
0 5
F
I
N
E

R
E
F
E
R
E
N
C
E

C
U
R
R
E
N
T

m
A
3.0
10 15 20
2R MODE
1R MODE
2.5
2.0
1.5
1.0
0.5
0
Figure 7b. Fine Gain Effect on I
FULLSCALE
In Figure 9, the negative scale represents an offset added to
I
OUTB
, while the

positive scale represents an offset added to
I
OUTA
of the respective DAC. Offset Register 1 corresponds to
IDAC, while Offset Register 2 corresponds to QDAC. Figure 9
represents the AD9775 synthesizing a complex signal that is then
dc-coupled to an AD8345 quadrature modulator with an LO of
800 MHz. The dc-coupling allows the input offset of the
AD8345 to be calibrated out as well. The LO suppression at
the AD8345 output was optimized first by adjusting Offset
Register 1 in the AD9775. When an optimal point was found
(roughly Code 54), this code was held in Offset Register 1, and
Offset Register 2 was adjusted. The resulting LO suppression
is 70 dBFS. These are typical numbers and the specific code for
optimization will vary from part to part.
COARSE GAIN REGISTER CODE Assuming
RSET1, 2 = 1.9k
0 200
O
F
F
S
E
T

C
U
R
R
E
N
T

m
A
0
5
400 600 800
1
2
3
4
2R MODE
1R MODE
1000
Figure 8. DAC Output Offset Current
REV. B
AD9775
21
OFFSET REGISTER 1 ADJUSTED
DAC1, DAC2 Offset Register Codes
1024 768
L
O

S
U
P
P
R
E
S
S
I
O
N

d
B
F
S
80
0
1024 512 256 0 256 512 768
70
60
50
40
30
20
10
OFFSET REGISTER 2
ADJUSTED, WITH OFFSET
REGISTER 1 SET
TO OPTIMIZED VALUE
Figure 9. Offset Adjust Control, Effect on LO
Suppression
1R/2R MODE
In 2R mode, the reference current for each channel is set inde-
pendently by the FSADJ resistor on that channel. The AD9775
can be programmed to derive its reference current from a single
resistor on Pin 60 by placing the part into 1R mode. The transfer
functions in Equation 1 are valid for 2R mode. In 1R mode, the
current developed in the single FSADJ resistor is split equally
between the two channels. The result is that in 1R mode, a scale
factor of 1/2 must be applied to the formulas in Equation 1. The
full-scale DAC current in 1R mode can still be set to as high as
20 mA by using the internal 1.2 V reference and a 950 resistor
instead of the 1.9 k resistor typically used in the 2R mode.
CLOCK INPUT CONFIGURATIONS
The clock inputs to the AD9775 can be driven differentially or
single-ended. The internal clock circuitry has supply and ground
(CLKVDD, CLKGND) separate from the other supplies on the
chip to minimize jitter from internal noise sources.
Figure 10 shows the AD9775 driven from a single-ended clock
source. The CLK+/CLK pins form a differential input (CLKIN)
so that the statically terminated input must be dc-biased to the
midswing voltage level of the clock driven input.
R
SERIES
VTHRESHOLD
AD9775
CLK+
CLKVDD
CLK
CLKGND
0.1F
Figure 10. Single-Ended Clock Driving Clock Inputs
A configuration for differentially driving the clock inputs is given
in Figure 11. DC-blocking capacitors can be used to couple a
clock driver output whose voltage swings exceed CLKVDD or
CLKGND. If the driver voltage swings are within the supply
range of the AD9775, the dc-blocking capacitors and bias resistors
are not necessary.
AD9775
CLK+
CLKVDD
CLK
CLKGND
0.1F
1k
ECL/PECL
1k
1k
1k
0.1F
0.1F
Figure 11. Differential Clock Driving Clock Inputs
A transformer, such as the T1-1T from Mini-Circuits, can also be
used to convert a single-ended clock to differential. This method
is used on the AD9775 evaluation board so that an external sine
wave with no dc offset can be used as a differential clock.
PECL/ECL drivers require varying termination networks, the
details of which are left out of Figures 10 and 11 but can be found
in application notes such as AND8020/D from On Semiconduc-
tor. These networks depend on the assumed transmission line
impedance and power supply voltage of the clock driver. Optimum
performance of the AD9775 is achieved when the driver is placed
very close to the AD9775 clock inputs, thereby negating any
transmission line effects such as reflections due to mismatch.
The quality of the clock and data input signals is important in
achieving optimum performance. The external clock driver
circuitry should provide the AD9775 with a low jitter clock
input that meets the min/max logic levels while providing fast
edges. Although fast clock edges help minimize any jitter that
will manifest itself as phase noise on a reconstructed waveform,
the high gain bandwidth product of the AD9775s clock input
comparator can tolerate differential sine wave inputs as low as
0.5 V p-p, with minimal degradation of the output noise floor.
PROGRAMMABLE PLL
CLKIN can function either as an input data rate clock (PLL
enabled) or as a DAC data rate clock (PLL disabled) according
to the state of Address 02h, Bit 7 in the SPI port register. The
internal operation of the AD9775 clock circuitry in these two
modes is illustrated in Figures 12 and 13.
The PLL clock multiplier and distribution circuitry produce the
necessary internal synchronized 1, 2, 4, and 8 clocks for
the rising edge triggered latches, interpolation filters, modula-
tors, and DACs. This circuitry consists of a phase detector,
charge pump, voltage controlled oscillator (VCO), prescaler,
clock distribution, and SPI port control. The charge pump,
VCO, differential clock input buffer, phase detector, prescaler,
and clock distribution are all powered from CLKVDD. PLL
lock status is indicated by the logic signal at the PLL_LOCK pin,
as well as by the status of Bit 1, Register 00h. To ensure optimum
phase noise performance from the PLL clock multiplier and
distribution, CLKVDD should originate from a clean analog
supply. The PLL Optimization table defines minimum input
data rates versus interpolation and PLL divider setting. If the
input data rate drops below the defined minimum under these
conditions, VCO noise may increase significantly. The VCO
speed is a function of the input data rate, the interpolation rate,
and the VCO prescaler, according to the following function:

VCOSpeed MHz
Input Data Rate MHz InterpolationRate escaler
( )
( )
=
Pr
REV. B
AD9775
22

CHARGE
PUMP
PHASE
DETECTOR
CLK+
CLOCK
DISTRIBUTION
CIRCUITRY
VCO
AD9775
CLK
SPI PORT
INTERNAL SPI
CONTROL
REGISTERS
PLL_LOCK
1 = LOCK
0 = NO LOCK
PLLVDD
LPF
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
2 8
INTERPOLATION
RATE
CONTROL
PLL DIVIDER
(PRESCALER)
CONTROL
PLL
CONTROL
(PLL ON)
1
INPUT
DATA
LATCHES
MODULATION
RATE
CONTROL
PRESCALER
4
Figure 12. PLL and Clock Circuitry with PLL Enabled

CHARGE
PUMP
PHASE
DETECTOR
CLK+
CLOCK
DISTRIBUTION
CIRCUITRY
VCO
AD9775
CLK
SPI PORT
INTERNAL SPI
CONTROL
REGISTERS
PLL_LOCK
1 = LOCK
0 = NO LOCK
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
2 8
INTERPOLATION
RATE
CONTROL
PLL DIVIDER
(PRESCALER)
CONTROL
PLL
CONTROL
(PLL ON)
1
INPUT
DATA
LATCHES
MODULATION
RATE
CONTROL
PRESCALER
4
Figure 13. PLL and Clock Circuitry with PLL Disabled
In addition, if the zero stuffing option is enabled, the VCO will
double its speed again. Phase noise may be slightly higher with
the PLL enabled. Figure 14 illustrates typical phase noise per-
formance of the AD9775 with 2 interpolation and various
input data rates. The signal synthesized for the phase noise
measurement was a single carrier at a frequency of f
DATA
/4. The
repetitive nature of this signal eliminates quantization noise and
distortion spurs as a factor in the measurement. Although the
curves blend together in Figure 14, the different conditions are
given for clarity in the table above Figure 14. Figure 14 also
contains a table detailing the maximum and minimum f
DATA
rates for each combination of interpolation rate and PLL divider
setting. These rates are guaranteed over the entire supply and
operating temperature range. Figure 15 shows typical perfor-
mance of the PLL lock signal (Pin 8 or Pin 53) when the PLL is
in the process of locking.
PLL Optimization
Interpolation Divider Minimum Maximum
Rate Setting f
DATA
f
DATA
1 1 32 160
1 2 16 160
1 4 8 112
1 8 4 56
2 1 24 160
2 2 12 112
2 4 6 56
2 8 3 28
4 1 24 100
4 2 12 56
4 4 6 28
4 8 3 14
8 1 24 50
8 2 12 28
8 4 6 14
8 8 3 7
f
DATA
PLL Prescaler Ratio
125 MSPS Disabled
125 MSPS Enabled div1
FREQUENCY OFFSET MHz
P
H
A
S
E

N
O
I
S
E

d
B
F
S
80
0
0
70
60
50
40
30
20
10
90
110
100
1 2 3 4 5
Figure 14. Phase Noise Performance
Figure 15. PLLLOCK Output Signal (Pin 8) in the
Process of Locking (Typical Lock Time)
REV. B
AD9775
23
It is important to note that the resistor/capacitor needed for the
PLL loop filter is internal on the AD9775. This will suffice unless
the input data rate is below 10 MHz, in which case an external
series RC is required between the LPF and PLLVDD pins.
POWER DISSIPATION
The AD9775 has three voltage supplies: DVDD, AVDD, and
CLKVDD. Figures 16, 17, and 18 show the current required
from each of these supplies when each is set to the 3.3 V nominal
specified for the AD9775. Power dissipation (P
D
) can easily be
extracted by multiplying the given curves by 3.3. As Figure 16
shows, I
DVDD
is very dependent on the input data rate, the inter-
polation rate, and the activation of the internal digital modulator.
I
DVDD
, however, is relatively insensitive to the modulation rate
by itself. In Figure 17, I
AVDD
shows the same type of sensitivity
to the data, the interpolation rate, and the modulator function but
to a much lesser degree (<10%). In Figure 18, I
CLKVDD
varies
over a wide range yet is responsible for only a small percentage
of the overall AD9775 supply current requirements.
f
DATA
MHz
0 50
I
D
V
D
D

m
A
0
100 150 200
50
100
150
200
250
300
350
400
8 (MOD. ON) ,
4 (MOD. ON) ,
2 (MOD. ON) ,
8
4
2
1
Figure 16. I
DVDD
vs. f
DATA
vs. Interpolation Rate,
PLL Disabled
f
DATA
MHz
0 50
I
A
V
D
D

m
A
72.0
100 150 200
72.5
8 (MOD. ON) ,
4 (MOD. ON) ,
2 (MOD. ON) ,
8 4
2
1
73.0
73.5
74.0
74.5
75.0
75.5
76.0
Figure 17. I
AVDD
vs. f
DATA
PLL Disabled
f
DATA
MHz
0 50
I
C
L
K
V
D
D

m
A
0
100 150 200
5
10
15
20
25
30
35
8
4 2
1
Figure 18. I
CLKVDD
vs. f
DATA
PLL Disabled
SLEEP/POWER-DOWN MODES
(Control Register 00h, Bits 3 and 4)
The AD9775 provides two methods for programmable reduction
in power savings. The sleep mode, when activated, turns off the
DAC output currents but the rest of the chip remains functioning.
When coming out of sleep mode, the AD9775 will immediately
return to full operation. Power-down mode, on the other hand,
turns off all analog and digital circuitry in the AD9775 except
for the SPI port. When returning from power-down mode, enough
clock cycles must be allowed to flush the digital filters of random
data acquired during the power-down cycle.
TWO PORT DATA INPUT MODE
The digital data input ports can be configured as two independent
ports or as a single (one port mode) port. In two port mode, data
at the two input ports is latched into the AD9775 on every rising
edge of the data rate clock (DATACLK). Also, in the two port
mode, the AD9775 can be programmed to generate an externally
available DATACLK for the purpose of data synchronization.
This data rate clock can be programmed to be available at either
Pin 8 (DATACLK/PLL) or Pin 53 (SPI_SDO). Because Pin 8
can also function as a PLL lock indicator when the PLL is
enabled, there are several options for configuring Pins 8 and 53.
The following table describes the options:
PLL off (Reg 4, Bit 7 = 0)
Reg 3, Bit 7 = 0; DATACLK out of Pin 8
Reg 3, Bit 7 = 1; DATACLK out of Pin 53
PLL on (Reg 4, Bit 7 = 1)
Reg 3, Bit 7 = 0, Reg 1, Bit 0 = 0; PLL lock indicator out of
Pin 8
Reg 3, Bit 7 = 1, Reg 1, Bit 0 = 0; PLL lock indicator out of
Pin 53
Reg 3, Bit 7 = 0, Reg 1, Bit 0 = 1; DATACLK out of Pin 8
Reg 3, Bit 7 = 1, Reg 1, Bit 0 = 1; DATACLK out of Pin 53
In one port mode, P2B14 and P2B15 from input data port two
are redefined as IQSEL and ONEPORTCLK, respectively. The
input data in one port mode is steered to one of the two internal
data channels based on the logic level of IQSEL. A clock signal,
ONEPORTCLK, is generated by the AD9775 in this mode for
REV. B
AD9775
24
the purpose of data synchronization. ONEPORTCLK runs at
the input interleaved data rate, which is 2 the data rate at the
internal input to either channel.
Test configurations showing the various clocks that are required
and generated by the AD9775 with the PLL enabled/disabled
and in the one port/two port modes are given in Figures 56 to
59. Jumper positions needed to operate the AD9775 evaluation
board in these modes are given as well.
PLL ENABLED, TWO PORT MODE
(Control Register 02h, Bits 60 and 04h, Bits 71)
With the phase-locked loop (PLL) enabled and the AD9775 in
two port mode, the speed of CLKIN is inherently that of the input
data rate. In two port mode, Pin 8 (DATACLK/PLL_ LOCK)
can be programmed (Control Register 01h, Bit 0) to function as
either a lock indicator for the internal PLL or as a clock running
at the input data rate. When Pin 8 is used as a clock output
(DATACLK), its frequency is equal to that of CLKIN. Data at
the input ports is latched into the AD9775 on the rising edge of the
CLKIN. Figure 19 shows the delay, t
OD
, inherent between the
rising edge of CLKIN and the rising edge of DATACLK, as well
as the setup and hold requirements for the data at Ports 1 and 2.
The setup and hold times given in Figure 19 are the input data
transitions with respect to CLKIN. Note that in two port mode
(PLL enabled or disabled), the data rate at the interpolation filter
inputs is the same as the input data rate at Ports 1 and 2.
The DAC output sample rate in two port mode is equal to the
clock input rate multiplied by the interpolation rate. If zero
stuffing is used, another factor of 2 must be included to calculate
the DAC sample rate.
DATACLK Inversion
(Control Register 02h, Bit 4)
By programming this bit, the DATACLK signal shown in
Figure 19 can be inverted. With inversion enabled, t
OD
will
refer to the time between the rising edge of CLKIN and the
falling edge of DATACLK. No other effect on timing will occur.
CLKIN
DATACLK
DATA AT PORTS
1 AND 2
t
OD
t
H
t
S
t
S
= 0.0ns (max)
t
H
= 2.5ns (max)
Figure 19. Timing Requirements in Two Port
Input Mode, with PLL Enabled
DATACLK DRIVER STRENGTH
The DATACLK output driver strength is capable of driving
>10 mA into a 330 load while providing a rise time of 3 ns.
Figure 20 shows DATACLK driving a 330 resistive load at a
frequency of 50 MHz. By enabling the drive strength option
(Control Register 02h, Bit 5), the amplitude of DATACLK
under these conditions will be increased by approximately 200 mV.
TIME ns
0 10
A
M
P
L
I
T
U
D
E

V
0.5
20 30 40
0
0.5
1.0
1.5
2.0
2.5
3.0
50
DELTA APPROX. 2.8ns
Figure 20. DATACLK Driver Capability into 330
at 50 MHz
PLL ENABLED, ONE PORT MODE
(Control Register 02h, Bits 61 and 04h, Bits 71)
In one port mode, the I and Q channels receive their data from an
interleaved stream at digital input Port 1. The function of Pin 32
is defined as an output (ONEPORTCLK) that generates a clock at
the interleaved data rate which is 2 the internal input data
rate of the I and Q channels. The frequency of CLKIN is equal
to the internal input data rate of the I and Q channels. The
selection of the data for the I or the Q channel is determined by the
state of the logic level at Pin 31 (IQSEL when the AD9775 is in
one port mode) on the rising edge of ONEPORTCLK. Under
these conditions, IQSEL = 1 will latch the data into the I channel
on the clock rising edge, while IQSEL = 0 will latch the data into
the Q channel. It is possible to invert the I and Q selection by set-
ting Control Register 02h, Bit 1 to the invert state (Logic 1).
Figure 21 illustrates the timing requirements for the data inputs as
well as the IQSEL input. Note that the 1 interpolation rate is
not available in the one port mode.
The DAC output sample rate in one port mode is equal to CLKIN
multiplied by the interpolation rate. If zero stuffing is used, another
factor of two must be included to calculate the DAC sample rate.
ONEPORTCLK INVERSION
By programming this bit, the ONEPORTCLK signal shown in
Figure 21 can be inverted. With inversion enabled, t
OD
refers to
the delay between the rising edge of the external clock and the
falling edge of ONEPORTCLK. The setup and hold times, t
S
and

t
H
,

will be with respect to the falling edge of ONEPORTCLK.
There will be no other effect on timing.
REV. B
AD9775
25
ONEPORTCLK DRIVER STRENGTH
The drive capability of ONEPORTCLK is identical to that of
DATACLK in the two port mode. Refer to Figure 20 for perfor-
mance under load conditions.
t
OD
t
H
t
S
CLKIN
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
ONEPORTCLK
IQSEL
t
IQH
t
IQS
t
OD
= 4.0ns (min)
to 5.5ns (max)
t
S
= 3.0ns (max)
t
H
= 0.5ns (max)
t
IQS
= 3.5ns (max)
t
IQH
= 1.5ns (max)
Figure 21. Timing Requirements in One Port
Input Mode with the PLL Enabled
IQ PAIRING
In one port mode, the interleaved data is latched into the
AD9775 internal I and Q channels in pairs. The order of how
the pairs are latched internally is defined by this control register.
The following is an example of the effect this has on incoming
interleaved data.
Given the following interleaved data stream, where the data
indicates the value with respect to full scale:
I Q I Q I Q I Q I Q
0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5
With the control register set to 0 (I first), the data will appear
at the internal channel inputs in the following order in time:
I Channel 0.5 1 0.5 0 0.5
Q Channel 0.5 1 0.5 0 0.5
With the control register set to 1 (Q first), the data will appear at
the internal channel inputs in the following order in time:
I Channel 0.5 1 0.5 0 0.5 x
Q Channel y 0.5 1 0.5 0 0.5
The values x and y represent the next I value and the previous
Q value in the series.
PLL DISABLED, TWO PORT MODE
With the PLL disabled, a clock at the DAC output rate must be
applied to CLKIN. Internal clock dividers in the AD9775 syn-
thesize the DATACLK signal at Pin 8, which runs at the input
data rate and can be used to synchronize the input data. Data is
latched into input Ports 1 and 2 of the AD9775 on the rising edge
of DATACLK. DATACLK speed is defined as the speed of
CLKIN divided by the interpolation rate. With zero stuffing
enabled, this division increases by a factor of 2. Figure 22
illustrates the delay between the rising edge of CLKIN and the
rising edge of DATACLK, as well as t
S
and

t
H
in this mode.
The programmable modes DATACLK inversion and DATACLK
driver strength described in the previous section (PLL
Enabled, Two Port Mode) have identical functionality with
the PLL disabled.
The data rate clock created by dividing down the DAC clock in
this mode can be programmed (via reg x03h, Bit 7) to be output
from the SPI_SDO pin rather than the DATACLK pin. In some
applications, this may improve complex image rejection. t
OD
will
increase by 1.6 ns when SPI_SDO is used as data rate clock out.
CLKIN
DATACLK
DATA AT PORTS
1 AND 2
t
OD
t
H
t
S
t
OD
= 6.5ns (min) to 8.0ns (max)
t
S
= 5.0ns (max)
t
H
= 3.2ns (max)
Figure 22. Timing Requirements in Two Port
Input Mode with PLL Disabled
PLL DISABLED, ONE PORT MODE
In one port mode, data is received into the AD9775 as an
interleaved stream on Port 1. A clock signal (ONEPORT CLK)
running at the interleaved data rate, which is 2 the input
data rate of the internal I and Q channels, is available for
data synchronization at Pin 32.
With PLL disabled, a clock at the DAC output rate must be applied
to CLKIN. Internal dividers synthesize the ONEPORTCLK
signal at Pin 32. The selection of the data for the I or Q channel
is determined by the state of the logic level applied to Pin 31
(IQSEL when the AD9775 is in one port mode) on the rising
edge of ONEPORTCLK. Under these conditions, IQSEL = 1
will latch the data into the I channel on the clock rising edge,
while IQSEL = 0 will latch the data into the Q channel. It is
possible to invert the I and Q selection by setting control
Register 02h, Bit 1 to the invert state (Logic 1). Figure 23
illustrates the timing requirements for the data inputs as well as
the IQSEL input. Note that the 1 interpolation rate is not
available in the one port mode.
One port mode is very useful when interfacing with devices
such as Analog Devices AD6622 or AD6623 transmit signal
processors, in which two digital data channels have been inter-
leaved (multiplexed).
REV. B
AD9775
26
The programmable modes ONEPORTCLK inversion,
ONEPORTCLK driver strength, and IQ pairing described in
the previous section (PLL Enabled, One Port Mode) have
identical functionality with the PLL disabled.
t
OD
t
H
t
S
CLKIN
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
ONEPORTCLK
IQSEL
t
IQH
t
IQS
t
OD
= 4.0ns (min)
to 5.5ns (max)
t
S
= 3.0ns (max)
t
H
= 1.0ns (max)
t
IQS
= 3.5ns (max)
t
IQH
= 1.5ns (max)
Figure 23. Timing Requirements in One Port
Input Mode with PLL Disabled
DIGITAL FILTER MODES
The I and Q data paths of the AD9775 have their own indepen-
dent half-band FIR filters. Each data path consists of three FIR
filters, providing up to 8 interpolation for each channel. The
rate of interpolation is determined by the state of control register
01h, Bits 7 and 6. Figures 1a to 1c show the response of the
digital filters when the AD9775 is set to 2, 4, and 8 modes.
The frequency axes of these graphs have been normalized to the
input data rate of the DAC. As the graphs show, the digital
filters can provide greater than 75 dB of out-of-band rejection.
An online tool is available for quick and easy analysis of the
AD9775 interpolation filters in the various modes. The link
can be accessed at www.analog.com/techSupport/designTools/
interactiveTools/dac/ad9777image.html.
AMPLITUDE MODULATION
Given two sine waves at the same frequency, but with a 90 phase
difference, a point of view in time can be taken such that the
waveform that leads in phase is cosinusoidal and the waveform
that lags is sinusoidal. Analysis of complex variables states that
the cosine waveform can be defined as having real positive and
negative frequency components, while the sine waveform consists
of imaginary positive and negative frequency images. This is
shown graphically in the frequency domain in Figure 24.
DC
DC
e
jt
/2j
COSINE
SINE
e
jt
/2
e
jt
/2j
e
jt
/2
Figure 24. Real and Imaginary Components of
Sinusoidal and Cosinusoidal Waveforms
Amplitude modulating a baseband signal with a sine or a cosine
convolves the baseband signal with the modulating carrier in the
frequency domain. Amplitude scaling of the modulated signal
reduces the positive and negative frequency images by a factor
of 2. This scaling will be very important in the discussion of the
various modulation modes. The phase relationship of the modu-
lated signals is dependent on whether the modulating carrier is
sinusoidal or cosinusoidal, again with respect to the reference
point of the viewer. Examples of sine and cosine modulation are
given in Figure 25.
SINUSOIDAL
MODULATION
DC
DC
Ae
jt
/2j
Ae
jt
/2 Ae
jt
/2
Ae
jt
/2j
COSINUSOIDAL
MODULATION
Figure 25. Baseband Signal, Amplitude
Modulated with Sine and Cosine Carriers
REV. B
AD9775
27
MODULATION, NO INTERPOLATION
With control register 01h, Bits 7 and 6 set to 00, the interpo-
lation function on the AD9775 is disabled. Figures 26a to 26d
show the DAC output spectral characteristics of the AD9775 in
the various modulation modes, all with the interpolation filters
disabled. The modulation frequency is determined by the state
of control register 01h, Bits 5 and 4. The tall rectangles rep-
resent the digital domain spectrum of a baseband signal of
narrow bandwidth. By comparing the digital domain spectrum
to the DAC SIN(x)/x roll-off, an estimate can be made for the
characteristics required for the DAC reconstruction filter. Note
also, per the previous discussion on amplitude modulation, that
the spectral components (where modulation is set to f
S
/4 or f
S
/8)
are scaled by a factor of 2. In the situation where the modulation
is f
S
/2, the modulated spectral components add constructively, and
there is no scaling effect.
f
OUT
(f
DATA
)
0 0.2
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
0.4 0.6 0.8 1.0
Figure 26a. No Interpolation, Modulation Disabled
f
OUT
(f
DATA
)
0 0.2
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
0.4 0.6 0.8 1.0
Figure 26b. No Interpolation, Modulation = f
DAC
/2
f
OUT
(f
DATA
)
0 0.2
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
0.4 0.6 0.8 1.0
Figure 26c. No Interpolation, Modulation = f
DAC
/4
f
OUT
(f
DATA
)
0 0.2
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
0.4 0.6 0.8 1.0
Figure 26d. No Interpolation, Modulation = f
DAC
/8
Figure 26. Effects of Digital Modulation on DAC Output Spectrum, Interpolation Disabled
REV. B
AD9775
28
MODULATION, INTERPOLATION = 2
lation rate of the AD9775 is 2. Modulation is achieved by
multiplying successive samples at the interpolation filter output
by the sequence (1, 1). Figures 27a to 27d represent the spectral
response of the AD9775 DAC output with 2 interpolation in
the various modulation modes to a narrow band baseband signal
(again, the tall rectangles in the graphic). The advantage of
interpolation becomes clear in Figures 27a to 27d, where it can
be seen that the images that would normally appear in the spec-
trum around the input data rate frequency are suppressed by
>70 dB. Another significant point is that the interpolation filter-
ing is done previous to the digital modulator. For this reason, as
Figures 27a to 27d show, the pass band of the interpolation
filters can be frequency shifted, giving the equivalent of a
high pass digital filter.
Note that when using the f
S
/4 modulation mode, there is no true
stop band as the band edges coincide with each other. In the f
S
/8
modulation mode, amplitude scaling occurs over only a portion of
the digital filter pass band due to constructive addition over just
that section of the band.
Figure 27. Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 2
f
OUT
(f
DATA
)
0 0.5
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
1.0 1.5 2.0
Figure 27a. 2 Interpolation, Modulation = Disabled
f
OUT
(f
DATA
)
0 0.5
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
1.0 1.5 2.0
Figure 27b. 2 Interpolation, Modulation = f
DAC
/2
f
OUT
(f
DATA
)
0 0.5
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
1.0 1.5 2.0
Figure 27c. 2 Interpolation, Modulation = f
DAC
/4
f
OUT
(f
DATA
)
0 0.5
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
1.0 1.5 2.0
Figure 27d. 2 Interpolation, Modulation = f
DAC
/8
REV. B
AD9775
29
f
OUT
(f
DATA
)
0 1
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
2 3 4
Figure 28a. 4 Interpolation, Modulation Disabled
f
OUT
(f
DATA
)
0 1
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
2 3 4
DAC
/2
f
OUT
(f
DATA
)
0 1
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
2 3 4
DAC
/4
f
OUT
(f
DATA
)
0 1
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
2 3 4
DAC
/8
lation rate of the AD9775 is 4. Modulation is achieved by
multiplying successive samples at the interpolation filter output
by the sequence (0, 1, 0, 1). Figures 28a to 28d represent the
spectral response of the AD9775 DAC output with 4 interpo-
lation in the various modulation modes to a narrow band
baseband signal.
REV. B
AD9775
30
f
OUT
(f
DATA
)
0 1
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
2 3 4
Figure 29a. 8 Interpolation, Modulation Disabled
f
OUT
(f
DATA
)
0 1
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
2 3 4
DAC
/2
f
OUT
(f
DATA
)
0 1
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
2 3 4 5 6 7 8
DAC
/4
f
OUT
(f
DATA
)
0 1
A
M
P
L
I
T
U
D
E

d
B
F
S
100
0
80
60
40
20
2 3 4 5 6 7 8
DAC
/8
With control register 01h, Bits 7 and 6 set to 11, the inter-
polation rate of the AD9775 is 8. Modulation is achieved by
multiplying successive samples at the interpolation filter
output by the sequence (0, 0.707, 1, 0.707, 0, 0.707, 1, 0.707).
Figures 29a to 29d represent the spectral response of the AD9775
DAC output with 8 interpolation in the various modulation
modes to a narrow band baseband signal.
Looking at Figures 27 to 30, the user can see how higher interpola-
tion rates reduce the complexity of the reconstruction filter needed
at the DAC output. It also becomes apparent that the ability to
modulate by f
S
/2, f
S
/4, or f
S
/8 adds a degree of flexibility in
frequency planning.
ZERO STUFFING
As shown in Figure 30, a 0 or null in the output frequency
response of the DAC (after interpolation, modulation, and DAC
reconstruction) occurs at the final DAC sample rate (f
DAC
).
This is due to the inherent SIN(x)/x roll-off response in the digital-
to-analog conversion. In applications where the desired frequency
content is below f
DAC
/2, this may not be a problem. Note that at
f
DAC
/2 the loss due to SIN(x)/x is 4 dB. In direct RF applica-
tions, this roll-off may be problematic due to the increased
pass-band amplitude variation as well as the reduced amplitude
of the desired signal.
Consider an application where the digital data into the AD9775
represents a baseband signal around f
DAC
/4 with a pass band of
f
DAC
/10. The reconstructed signal out of the AD9775 would
experience only a 0.75 dB amplitude variation over its pass band.
However, the image of the same signal occurring at 3 f
DAC
/4
will suffer from a pass-band flatness variation of 3.93 dB. This
image may be the desired signal in an IF application using one
of the various modulation modes in the AD9775. This roll-off
of image frequencies can be seen in Figures 26 to 29, where the
effect of the interpolation and modulation rate is apparent as well.
REV. B
AD9775
31
f
OUT
, NORMALIZED TO f
DATA
WITH ZERO STUFFING
DISABLED Hz
S
I
N

(
X
)
/
X

R
O
L
L
-
O
F
F

d
B
F
S
0
0
50
40
30
20
10
0.5
10
1.0 1.5 2.0
ZERO STUFFING
ENABLED
ZERO STUFFING
DISABLED
Figure 30. Effect of Zero Stuffing on DACs
SIN(x)/x Response
To improve upon the pass-band flatness of the desired image,
the zero stuffing mode can be enabled by setting the control
register bit to Logic 1. This option increases the ratio of f
DAC
/
f
DATA
by a factor of 2 by doubling the DAC sample rate and
inserting a midscale sample (i.e., 1000 0000 0000 0000) after
every data sample originating from the interpolation filter. This
is important as it will affect the PLL divider ratio needed to keep
the VCO within its optimum speed range. Note that the zero
stuffing takes place in the digital signal chain at the output of the
digital modulator before the DAC.
The net effect is to increase the DAC output sample rate by a
factor of 2 with the 0 in the SIN(x)/x DAC transfer function
occurring at twice the original frequency. A 6 dB loss in ampli-
tude at low frequencies is also evident, as can be seen in Figure 30.
It is important to realize that the zero stuffing option by itself
does not change the location of the images but rather their ampli-
tude, pass-band flatness, and relative weighting. For instance, in
the previous example, the pass-band amplitude flatness of the
image at 3 f
DATA
/4 is now improved to 0.59 dB while the signal
level has increased slightly from 10.5 dBFS to 8.1 dBFS.
INTERPOLATING (COMPLEX MIX MODE)
In the complex mix mode, the two digital modulators on the
AD9775 are coupled to provide a complex modulation function.
In conjunction with an external quadrature modulator, this
complex modulation can be used to realize a transmit image
rejection architecture. The complex modulation function can be
programmed for e
+jt
or

e
jt
to give upper or lower image rejec-
tion. As in the real modulation mode, the modulation frequency
can be programmed via the SPI port for f
DAC
/2, f
DAC
/4, and
f
DAC
/8, where f
DAC
represents the DAC output rate.
OPERATIONS ON COMPLEX SIGNALS
Truly complex signals cannot be realized outside of a computer
simulation. However, two data channels, both consisting of real
data, can be defined as the real and imaginary components of a
complex signal. I (real) and Q (imaginary) data paths are often
defined this way. By using the architecture defined in Figure 31,
a system can be realized that operates on complex signals,
giving a complex (real and imaginary) output.
If a complex modulation function (e
+jt
) is desired, the real and
imaginary components of the system correspond to the real and
imaginary components of e
+jt
, or cost and sint. As Figure 32
shows, the complex modulation function can be realized by
applying these components to the structure of the complex
system defined in Figure 31.
a(t) INPUT
INPUT OUTPUT
OUTPUT
COMPLEX FILTER
= (c + jd)
IMAGINARY
b(t) b(t) a(t) + c b(t)
c(t) b(t) + d b(t)

Figure 31. Realization of a Complex System
OUTPUT
(IMAGINARY)
OUTPUT
(REAL)
INPUT
(REAL)
INPUT
(IMAGINARY)
e
jt
= COSt + jSINt
90
Figure 32. Implementation of a Complex Modulator

COMPLEX MODULATION AND IMAGE REJECTION OF
BASEBAND SIGNALS
In traditional transmit applications, a two-step upconversion is
done in which a baseband signal is modulated by one carrier to
an IF (intermediate frequency) and then modulated a second
time to the transmit frequency. Although this approach has
several benefits, a major drawback is that two images are cre-
ated near the transmit frequency. Only one image is needed, the
other being an exact duplicate. Unless the unwanted image is
filtered, typically with analog components, transmit power is
wasted and the usable bandwidth available in the system is
reduced.
A more efficient method of suppressing the unwanted image
can be achieved by using a complex modulator followed by a
quadrature modulator. Figure 33 is a block diagram of a
quadrature modulator. Note that it is in fact the real output half
of a complex modulator. The complete upconversion can actu-
ally be referred to as two complex upconversion stages, the real
output of which becomes the transmitted signal.
90
OUTPUT
INPUT
(REAL)
INPUT
(IMAGINARY)
COSt
SINt
Figure 33. Quadrature Modulator

REV. B
AD9775
32
The entire upconversion, from baseband to transmit frequency,
is represented graphically in Figure 34. The resulting spectrum
shown in Figure 34 represents the complex data consisting of
the baseband real and imaginary channels, now modulated onto
orthogonal (cosine and negative sine) carriers at the transmit
frequency. It is important to remember that in this application
(two baseband data channels) the image rejection is not
dependent on the data at either of the AD9775 input channels.
In fact, image rejection will still occur with either one or both of
the AD9775 input channels active. Note that by changing the sign
of the sinusoidal multiplying term in the complex modulator, the
upper sideband image could have been suppressed while passing
the lower one. This is easily done in the AD9775 by selecting
the e
+jt
bit (Register 01h, Bit 1). In purely complex terms,
Figure 34 represents the two-stage upconversion from complex
baseband to carrier.
REAL CHANNEL (IN)
IMAGINARY CHANNEL (IN)
DC
DC
A
B
COMPLEX
MODULATOR
REAL CHANNEL (OUT)
IMAGINARY CHANNEL (OUT)
F
C
1
B/2J B/2J
TO QUADRATURE
MODULATOR
F
C
F
C
F
C
F
C
F
C
F
C
F
C
A/2J A/2J
B/2 B/2
A/2 A/2
REAL
IMAGINARY
QUADRATURE
MODULATOR
OUT
A/4 + B/4J A/4 B/4J
F
Q
F
C
REJECTED IMAGES
A/4 + B/4J A/4 B/4J
A/4 + B/4J A/4 B/4J A/4 B/4J A/4 + B/4J
A/2 + B/2J A/2 B/2J
F
Q
2
F
Q
+ F
C
F
Q
F
C
F
Q
F
Q
+ F
C
F
Q
F
Q
F
Q
F
Q
NOTES
1
F
C
= COMPLEX MODULATION FREQUENCY
2
F
Q
= QUADRATURE MODULATION FREQUENCY
Figure 34. Two-Stage Upconversion and Resulting Image Rejection
REV. B
AD9775
33
OUTPUT = REAL
COMPLEX BASEBAND
SIGNAL
DC
= REAL
e
j(1

+

2)t
FREQUENCY
1 2 1 + 2
1
1/2 1/2
Figure 35. Two-Stage Complex Upconversion

IMAGE REJECTION AND SIDEBAND SUPPRESSION OF
MODULATED CARRIERS
As shown in Figure 34, image rejection can be achieved by applying
baseband data to the AD9775 and following the AD9775 with a
quadrature modulator. To process multiple carriers while still
maintaining image reject capability, each carrier must be complex
modulated. As Figure 35 shows, single or multiple complex
modulators can be used to synthesize complex carriers. These
complex carriers are then summed and applied to the real and
imaginary inputs of the AD9775. A system in which multiple
baseband signals are complex modulated and then applied to
the AD9775 real and imaginary inputs followed by a quadrature
modulator is shown in Figure 37, which also describes the transfer
function of this system and the spectral output. Note the simi-
larity of the transfer functions given in Figure 37 and Figure 35.
Figure 37 adds an additional complex modulator stage for the
purpose of summing multiple carriers at the AD9775 inputs. Also,
as in Figure 34, the image rejection is not dependent on the real
or imaginary baseband data on any channel. Image rejection on
a channel will occur if either the real or imaginary data, or both,
is present on the baseband channel.
It is important to remember that the magnitude of a complex signal
can be 1.414 the magnitude of its real or imaginary components.
Due to this 3 dB increase in signal amplitude, the real and imagi-
nary inputs to the AD9775 must be kept at least 3 dB below full
scale when operating with the complex modulator. Overranging
in the complex modulator will result in severe distortion at the
DAC output.
R(1)
BASEBAND CHANNEL 1
REAL INPUT
IMAGINARY INPUT R(1)
COMPLEX
MODULATOR 1
BASEBAND CHANNEL N
REAL INPUT
IMAGINARY INPUT
COMPLEX
MODULATOR N
R(N)
R(N)
BASEBAND CHANNEL 2
REAL INPUT
IMAGINARY INPUT
R(2)
R(2)
COMPLEX
MODULATOR 2
R(N) = REAL OUTPUT OF N
I(N) = IMAGINARY OUTPUT OF N
MULTICARRIER
REAL OUTPUT =
R(1) + R(2) + ...R(N)
(TO REAL INPUT OF AD9775)
MULTICARRIER
IMAGINARY OUTPUT =
I(1) + I(2) + ...I(N)
(TO IMAGINARY INPUT OF AD9775)
Figure 36. Synthesis of Multicarrier Complex Signal
REAL
IMAGINARY
MULTIPLE
COMPLEX
MODULATORS
FREQUENCY =
1
,
2
...
N

REAL
IMAGINARY
REAL
IMAGINARY
AD9775
COMPLEX
MODULATOR
FREQUENCY =
C

QUADRATURE
MODULATOR
FREQUENCY =
Q

MULTIPLE
BASEBAND
CHANNELS
REAL
REJECTED IMAGES
DC
1

C

Q

1
+
C
+
Q
OUTPUT = REAL
e
j(
N
+

C
+

Q
)t
COMPLEX BASEBAND
SIGNAL
Figure 37. Image Rejection with Multicarrier Signals

REV. B
AD9775
34
The complex carrier synthesized in the AD9775 digital modulator
is accomplished by creating two real digital carriers in quadrature.
Carriers in quadrature cannot be created with the modulator
running at f
DAC
/2. As a result, complex modulation only functions
with modulation rates of f
DAC
/4 and f
DAC
/8.
Regions A and B of Figures 38 to 43 are the result of the com-
plex signal described previously, when complex modulated in
the AD9775 by +e
jt
. Regions C and D are the result of the
complex signal described previously, again with positive
frequency components only, modulated in the AD9775 by e
jt
.
The analog quadrature modulator after the AD9775 inherently
modulates by +e
jt
.
Region A
Region A is a direct result of the upconversion of the complex
signal near baseband. If viewed as a complex signal, only the
images in Region A will remain. The complex Signal A, consisting
of positive frequency components only in the digital domain,
has images in the positive odd Nyquist zones (1, 3, 5...), as well
as images in the negative even Nyquist zones. The appearance
and rejection of images in every other Nyquist zone will become
more apparent at the output of the quadrature modulator. The
A images will appear on the real and the imaginary outputs of
the AD9775, as well as on the output of the quadrature modulator,
where the center of the spectral plot will now represent the
quadrature modulator LO, and the horizontal scale now represents
the frequency offset from this LO.
Region B
Region B is the image (complex conjugate) of Region A. If a spec-
trum analyzer is used to view the real or imaginary DAC outputs
of the AD9775, Region B will appear in the spectrum. However, on
the output of the quadrature modulator, Region B will be rejected.
Region C
Region C is most accurately described as a down conversion, as the
modulating carrier is e
jt
. If viewed as a complex signal, only the
images in Region C will remain. This image will appear on the
real and imaginary outputs of the AD9775, as well as on the
output of the quadrature modulator, where the center of the spec-
tral plot will now represent the quadrature modulator LO and the
horizontal scale will represent the frequency offset from this LO.
Region D
Region D is the image (complex conjugate) of Region C. If a
spectrum analyzer is used to view the real or imaginary DAC
outputs of the AD9775, Region D will appear in the spectrum.
However, on the output of the quadrature modulator, Region D
will be rejected.
Figures 44 to 51 show the measured response of the AD9775 and
AD8345 given the complex input signal to the AD9775 in
Figure 44. The data in these graphs was taken with a data rate
of 12.5 MSPS at the AD9775 inputs. The interpolation rate of 4
or 8 gives a DAC output data rate of 50 MSPS or 100 MSPS. As
a result, the high end of the DAC output spectrum in these graphs
is the first null point for the SIN(x)/x roll-off, and the asymmetry
of the DAC output images is representative of the SIN(x)/x roll-off
over the spectrum. The internal PLL was enabled for these
results. In addition, a 35 MHz third order low-pass filter was
used at the AD9775/AD8345 interface to suppress DAC images.
An important point can be made by looking at Figures 46 and 48.
Figure 46 represents a group of positive frequencies modulated by
complex +f
DAC
/4, while Figure 48 represents a group of negative
frequencies modulated by complex f
DAC
/4. When looking at the
real or imaginary outputs of the AD9775, as shown in Figures 46
and 48, the results look identical. However, the spectrum analyzer
cannot show the phase relationship of these signals. The differ-
ence in phase between the two signals becomes apparent when
they are applied to the AD8345 quadrature modulator, with the
results shown in Figures 47 and 49.
REV. B
AD9775
35
D A B C D A B C
f
OUT
(f
DATA
)
2.0
100
80
60
40
20
0
1.5 1.0 0.5 0 0.5 1.0 1.5 2.0
(LO)
Figure 38. 2 Interpolation, Complex f
DAC
/4 Modulation
D A B C D A B C
f
OUT
(f
DATA
)
4.0
100
80
60
40
20
0
3.0 2.0 1.0 0 1.0 2.0 3.0 4.0
(LO)
DAC
/4 Modulation
D A B C D A B C
f
OUT
(f
DATA
)
8.0
100
80
60
40
20
0
6.0 4.0 2.0 0 2.0 4.0 6.0 8.0
(LO)
DAC
/4 Modulation
A B C D A B
f
OUT
(f
DATA
)
2.0
100
80
60
40
20
0
1.5 1.0 0.5 0 0.5 1.0 1.5 2.0
(LO)
C D
DAC
/8 Modulation
A B C D A B
f
OUT
(f
DATA
)
4.0
100
80
60
40
20
0
3.0 2.0 1.0 0 1.0 2.0 3.0 4.0
(LO)
C D
DAC
/8 Modulation
f
OUT
(f
DATA
)
8.0
100
80
60
40
20
0
6.0 4.0 2.0 0 2.0 4.0 6.0 8.0
(LO)
A D C B A D C B
DAC
/8 Modulation
REV. B
AD9775
36
A
M
P
L
I
T
U
D
E

d
B
m
30
100
0 10 50 20
60
70
90
80
40
50
20
FREQUENCY MHz
10
0
30 40
Figure 44. AD9775, Real DAC Output of Complex
Input Signal Near Baseband (Positive Frequencies
Only), Interpolation = 4, No Modulation in
AD9775
A
M
P
L
I
T
U
D
E

d
B
m
30
100
60
70
90
80
40
50
20
10
0
750
FREQUENCY MHz
760 770 780 790 800 810 820 830 840 850
Figure 45. AD9775 Complex Output from
Figure 44, Now Quadrature Modulated by AD8345
(LO = 800 MHz)
A
M
P
L
I
T
U
D
E

d
B
m
30
100
0 20 40
60
70
90
80
40
50
20
FREQUENCY MHz
10
0
30 50 10
Only), Interpolation = 4, Complex Modulation in
AD9775 = +f
DAC
/4
A
M
P
L
I
T
U
D
E

d
B
m
30
100
60
70
90
80
40
50
20
10
0
750
FREQUENCY MHz
760 770 780 790 800 810 820 830 840 850
Figure 46, Now Quadrature Modulated
by AD8345 (LO = 800 MHz)
REV. B
AD9775
37
A
M
P
L
I
T
U
D
E

d
B
m
30
100
0 20 40
60
70
90
80
40
50
20
FREQUENCY MHz
10
0
30 50 10
Input Signal Near Baseband (Negative Frequencies
AD9775 = f
DAC
/4
A
M
P
L
I
T
U
D
E

d
B
m
30
100
60
70
90
80
40
50
20
10
0
750
FREQUENCY MHz
760 770 780 790 800 810 820 830 840 850
Figure 48, Now Quadrature Modulated by
AD8345 (LO = 800 MHz)
A
M
P
L
I
T
U
D
E

d
B
m
30
100
60
70
90
80
40
50
20
10
0
0 20 80 40
FREQUENCY MHz
60 100
AD9775 = +f
DAC
/8
A
M
P
L
I
T
U
D
E

d
B
m
30
100
60
70
90
80
40
50
20
10
0
700
FREQUENCY MHz
720 740 760 780 800 820 840 860 880 900
Figure 50, Now Quadrature Modulated by
AD8345 (LO = 800 MHz)
REV. B
AD9775
38
APPLYING THE AD9775 OUTPUT CONFIGURATIONS
The following sections illustrate typical output configurations for
the AD9775. Unless otherwise noted, it is assumed that I
OUTFS
is set to a nominal 20 mA. For applications requiring optimum
dynamic performance, a differential output configuration is
suggested. A simple differential output may be achieved by con-
verting I
OUTA
and I
OUTB
to a voltage output by terminating
them to AGND via equal value resistors. This type of configura-
tion may be useful when driving a differential voltage input
device such as a modulator. If a conversion to a single-ended
signal is desired and the application allows for ac-coupling, an RF
transformer may be useful, or if power gain is required, an op amp
may be used. The transformer configuration provides optimum
high frequency noise and distortion performance. The differen-
tial op amp configuration is suitable for applications requiring
dc-coupling, signal gain, and/or level shifting within the band-
width of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage
will result if I
OUTA
and/or I
OUTB
is connected to a load resistor,
R
LOAD
, referred to AGND. This configuration is most suitable
for a single-supply system requiring a dc-coupled, ground
referred output voltage. Alternatively, an amplifier could be
configured as an I-V converter, thus converting I
OUTA
or I
OUTB
into a negative unipolar voltage. This configuration provides the
best DAC dc linearity as I
OUTA
or I
OUTB
are maintained at ground
or virtual ground.
UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT
CIRCUIT
In many applications, it may be necessary to understand the
equivalent DAC output circuit. This is especially useful when
designing output filters or when driving inputs with finite input
impedances. Figure 52 illustrates the output of the AD9775 and
the equivalent circuit. A typical application where this information
may be useful is when designing an interface filter between the
AD9775 and Analog Devices AD8345 quadrature modulator.
I
OUTA
R
A
+ R
B
I
OUTB
V
OUT
(DIFFERENTIAL)
V
SOURCE
=
I
OUTFS
(R
A
+ R
B
)
p-p
V
OUT
+
V
OUT
Figure 52. DAC Output Equivalent Circuit

For the typical situation, where I
OUTFS
= 20 mA and R
A
and R
B
both equal 50 , the equivalent circuit values become:
V
SOURCE
= 2 V p-p
R
OUT
= 100
Note that the output impedance of the AD9775 DAC itself is
greater than 100 k and typically has no effect on the impedance
of the equivalent output circuit.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-
to-single-ended signal conversion, as shown in Figure 53. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformers pass band. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Trans-
formers with different impedance ratios may also be used for
impedance matching purposes.
I
OUTA
I
OUTB
DAC
R
LOAD
MINI-CIRCUITS
T1-1T
Figure 53. Transformer-Coupled Output Circuit
The center tap on the primary side of the transformer must be
connected to AGND to provide the necessary dc current path
for both I
OUTA
and I
OUTB
. The complementary voltages appearing
at I
OUTA
and I
OUTB
(i.e., V
OUTA
and V
OUTB
) swing symmetrically
around AGND and should be maintained within the specified
output compliance range of the AD9775. A differential resistor,
R
DIFF
, may be inserted in applications where the output of the
transformer is connected to the load, R
LOAD
, via a passive recon-
struction filter or cable. R
DIFF
is determined by the transformers
impedance ratio and provides the proper source termination
that results in a low VSWR. Note that approximately half the
signal power will be dissipated across R
DIFF
.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-
ended conversion, as shown in Figure 54. This has the added
benefit of providing signal gain as well. In Figure 54, the AD9775
is configured with two equal load resistors, R
LOAD
, of 25 . The
differential voltage developed across I
OUTA
and I
OUTB
is converted
to a single-ended signal via the differential op amp configura-
tion. An optional capacitor can be installed across I
OUTA
and
I
OUTB
, forming a real pole in a low-pass filter. The addition of
this capacitor also enhances the op amps distortion performance
by preventing the DACs fast slewing output from overloading
the input of the op amp.
I
OUTA
I
OUTB
DAC
25
AD8021
500
C
OPT
225
225
500
R
OPT
225
AVDD
25
Figure 54. Op Amp-Coupled Output Circuit
The common-mode (and second order distortion) rejection of this
configuration is typically determined by the resistor matching.
The op amp used must operate from a dual supply since its
output is approximately 1.0 V. A high speed amplifier, such as
the AD8021, capable of preserving the differential performance
REV. B
AD9775
39
of the AD9775 while meeting other system level objectives (i.e.,
cost, power) is recommended. The op amps differential gain,
its gain setting resistor values, and full-scale output swing capa-
bilities should all be considered when optimizing this circuit. R
OPT
is only necessary if level shifting is required on the op amp out-
put. In Figure 54, AVDD, which is the positive analog supply for
both the AD9775 and the op amp, is also used to level shift the
differential output of the AD9775 to midsupply (i.e., AVDD/2).
INTERFACING THE AD9775 WITH THE AD8345
QUADRATURE MODULATOR
The AD9775 architecture was defined to operate in a transmit
signal chain using an image reject architecture. A quadrature
modulator is also required in this application and should be
designed to meet the output characteristics of the DAC as much
as possible. The AD8345 from Analog Devices meets many of
the requirements for interfacing with the AD9775. As with any
DAC output interface, there are a number of issues that have to
be resolved. Among the major issues are the following.
DAC Compliance Voltage/Input Common-Mode Range
The dynamic range of the AD9775 is optimal when the DAC
outputs swing between 1.0 V. The input common-mode range
of the AD8345, at 0.7 V, allows optimum dynamic range to be
achieved in both components.
Gain/Offset Adjust
The matching of the DAC output to the common-mode input
of the AD8345 allows the two components to be dc-coupled,
with no level shifting necessary. The combined voltage offset of
the two parts can therefore be compensated for via the AD9775
programmable offset adjust. This allows excellent LO cancella-
tion at the AD8345 output. The programmable gain adjust
allows for optimal image rejection as well.
The AD9775 evaluation board includes an AD8345 and recom-
mended interface (Figures 59 and 60). On the output of the
AD9775, R9 and R10 convert the DAC output current to a
voltage. R16 may be used to do a slight common-mode shift if
necessary. The (now voltage) signal is applied to a low-pass
reconstruction filter to reject DAC images. The components
installed on the AD9775 provide a 35 MHz cutoff, but may be
changed to fit the application. A balun (Mini-Circuits ADTL1-12)
is used to cross the ground plane boundary to the AD8345.
Another balun (Mini-Circuits ETC1-1-13) is used to couple
the LO input of the AD8345. The interface requires a low ac
impedance return path from the AD8345, so a single connec-
tion between the AD9775 and AD8345 ground planes is
recommended.
The performance of the AD9775 and AD8345 in an image reject
transmitter, reconstructing three WCDMA carriers, can be seen
in Figure 55. The LO of the AD8345 in this application is 800 MHz.
Image rejection (50 dB) and LO feedthrough (78 dBFS) have
been optimized with the programmable features of the AD9775.
The average output power of the digital waveform for this test
was set to 15 dBFS to account for the peak-to-average ratio of
the WCDMA signal.
FREQUENCY MHz
A
M
P
L
I
T
U
D
E

d
B
m
80
0
762.5
70
60
50
40
30
20
10
90
100
782.5 802.5 822.5 842.5
Figure 55. AD9775/AD8345 Synthesizing a Three-
Carrier WCDMA Signal at an LO of 800 MHz
EVALUATION BOARD
The AD9775 evaluation board allows easy configuration of the
various modes, programmable via the SPI port. Software is
available for programming the SPI port from Windows
95,
Windows 98, or WindowsNT
/2000. The evaluation board also

contains an AD8345 quadrature modulator and support circuitry
that allows the user to optimally configure the AD9775 in an
image reject transmit signal chain.
Figures 56 to 59 describe how to configure the evaluation board
in the one and two port input modes with the PLL enabled
and disabled. Refer to Figures 60 to 69, the schematics, and the
layout for the AD9775 evaluation board for the jumper locations
described below. The AD9775 outputs can be configured for
various applications by referring to the following instructions.
DAC Single-Ended Outputs
Remove transformers T2 and T3. Solder jumper links JP4 or
JP28 to look at the DAC1 outputs. Solder jumper links JP29 or
JP30 to look at the DAC2 outputs. Jumpers 8 and 1317 should
remain unsoldered. Jumpers JP35JP38 may be used to ground
one of the DAC outputs while the other is measured single-ended.
Optimum single-ended distortion performance is typically
achieved in this manner. The outputs are taken from S3 and S4.
DAC Differential Outputs
Transformers T2 and T3 should be in place. Note that the lower
band of operation for these transformers is 300 kHz to 500 kHz.
Jumpers 4, 8, 1317, and 2830 should remain unsoldered. The
outputs are taken from S3 and S4.
Using the AD8345
Remove transformers T2 and T3. Jumpers JP4 and 2830 should
remain unsoldered. Jumpers 1316 should be soldered. The
desired components for the low-pass interface filter L6, L7, C55,
and C81 should be in place. The LO drive is connected to the
AD8345 via J10 and the balun T4; and the AD8345 output is
taken from J9.
REV. B
AD9775
40
SIGNAL GENERATOR
CLK+/CLK DATACLK
LECROY
PULSE
GENERATOR
TRIG
INP
AWG2021
OR
DG2020
INPUT CLOCK
DAC1, DB13DB0
AD9775
DAC2, DB13DB0
40-PIN RIBBON CABLE
JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON
SOLDERED/IN UNSOLDERED/OUT
JP1
JP2
JP3
JP5
JP6
JP12
JP24
JP25
JP26
JP27
JP31
JP32
JP33
Figure 56
1
. Test Configuration for AD9775 in Two Port Mode with PLL Enabled, Signal Generator
Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency Interpolation Rate
2
SIGNAL GENERATOR
CLK+/CLK ONEPORTCLK
LECROY
PULSE
GENERATOR
TRIG
INP
AWG2021
OR
DG2020
INPUT CLOCK
DAC1, DB13DB0
AD9775
DAC2, DB13DB0
JUMPER CONFIGURATION FOR ONE PORT MODE PLL ON
JP1
JP2
JP3
JP5
JP6
JP12
JP24
JP25
JP26
JP27
JP31
JP32
JP33
Figure 57
1
. Test Configuration for AD9775 in One Port Mode with PLL Enabled, Signal Generator
Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output
Data Rate = Signal Generator Frequency Interpolation Rate
NOTES
1
To use PECL clock driver, solder JP41 and JP42 and remove transformer T1.
2
In two port mode, if DATACLK/PLL is programmed to output Pin 8, JP25 and JP39 should be soldered. If DATACLK/PLL is programmed to
output Pin 53, JP46 and JP47 should be soldered. See the Two Port Data Input Mode section for more information.
REV. B
AD9775
41
SIGNAL GENERATOR
CLK+/CLK DATACLK
LECROY
PULSE
GENERATOR
TRIG
INP
AWG2021
OR
DG2020
INPUT CLOCK
DAC1, DB13DB0
AD9775
DAC2, DB13DB0
40-PIN RIBBON CABLE
JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF
JP1
JP2
JP3
JP5
JP6
JP12
JP24
JP25
JP26
JP27
JP31
JP32
JP33
Figure 58
1
. Test Configuration for AD9775 in Two Port Mode with PLL Disabled, DAC Output Data Rate = Signal
Generator Frequency, DATACLK = Signal Generator Frequency/Interpolation Rate
2
SIGNAL GENERATOR
CLK+/CLK ONEPORTCLK
LECROY
PULSE
GENERATOR
TRIG
INP
AWG2021
OR
DG2020
INPUT CLOCK
DAC1, DB13DB0
AD9775
DAC2, DB13DB0
JUMPER CONFIGURATION FOR ONE PORT MODE PLL OFF
JP1
JP2
JP3
JP5
JP6
JP12
JP24
JP25
JP26
JP27
JP31
JP32
JP33
Figure 59
1
. Test Configuration for AD9775 in One Port Mode with PLL Disabled, DAC Output Data Rate =
Signal Generator Frequency, ONEPORTCLK = Interleaved Input Data Rate = 2 Signal Generator
Frequency/Interpolation Rate
NOTES
1
To use PECL clock driver, solder JP41 and JP42 and remove transformer T1.
2
In two port mode, if DATACLK/PLL is programmed to output Pin 8, JP25 and JP39 should be soldered. If DATACLK/PLL is programmed to
output Pin 53, JP46 and JP47 should be soldered. See the Two Port Data Input Mode section for more information.
REV. B
AD9775
42
J
P
4
5
J
P
2
1
J
P
7
C
5
5
D
N
P
C
8
1
D
N
P
C
5
4
D
N
P
W
1
2
1
6
V
2
2
F
C
2
8
0
.
1
F
C
3
2
R
2
8
0
1
k
R
2
6
D
N
P
C
8
0
R
3
5

5
1
5
1
R
3
6
J
P
2
0
D
N
P
C
7
9
R
3
2

5
1
R
3
4

D
N
P
0
.
1
F
C
6
9
C
6
8
0
.
1
F
0
.
1
F
C
6
7
J
P
1
1
J
P
1
0
J
P
9
1
6
V
2
2
F
C
6
3
C
6
4
2
2
F
1
6
V
1
6
V
2
2
F
C
6
5
D
V
D
D
_
I
N
A
V
D
D
_
I
N
C
L
K
V
D
D
_
I
N
J
4
J
5
J
7
B
L
K
R
E
D
B
L
K
R
E
D
B
L
K
J
8
C
6
2
2
2
F
1
6
V
1
6
V
2
2
F
C
6
1
D
V
D
D
A
V
D
D
C
L
K
V
D
D
F
E
R
R
I
T
E
L
1
F
E
R
R
I
T
E
L
2
5
1
R
3
3
C
7
8
0
.
1
F
J
P
1
8
V
D
D
M
F
E
R
R
I
T
E
L
3
1
0
V
1
0
F
C
7
2
C
6
6
2
2
F
1
6
V
0
.
1
F
C
7
5
R
E
D
V
D
D
M
I
N
W
1
1
O
2
N
O
2
P
O
1
N
O
1
P
J
6
J
P
1
9
V
D
D
M
1
0
0
p
F
C
7
4
C
3
5
1
0
0
p
F
V
D
D
M
T 5
6 1
C
7
6
1
0
0
p
F
C
7
7
R
3
0
D
N
P
T
4
5 4
31
J
1
0
D
G
N
D
2
;
3
,
4
,
5
J
9
D
G
N
D
2
;
3
,
4
,
5
J
3
C
G
N
D
A
G
N
D
D
G
N
D
D
G
N
D
2
A
D
8
3
4
5
U
2
5
1 52
1
1 0
1 1
1 6
1 4
1 3
1 2
6
4
3
7
8 9
J
P
4
3
L
8
F
E
R
R
I
T
E
2
2
2
2
2
2
C
C
0
8
0
5
C
C
0
8
0
5
D
C
A
S
E
C
C
0
8
0
5
R
C
0
6
0
3
R C 0 6 0 3
R
C
0
6
0
3
C C 0 6 0 3
R
C
0
6
0
3
R
C
0
6
0
3
R
C
0
6
0
3
C C 0 6 0 3
R
C
0
6
0
3
R
C
0
6
0
3
C
C
0
8
0
5
C
C
0
8
0
5
D
C
A
S
E
D
C
A
S
E
L
C
1
2
1
0
L
C
1
2
1
0
R
C
0
6
0
3
C
C
0
6
0
3
L
C
1
2
1
0
B
C
A
S
E
D
C
A
S
E
C C 0 6 0 3
C
C
0
6
0
3
A D T L 1 - 1 2
PS
C C 0 6 0 3C C 0 6 0 3
R C 0 6 0 3
E
T
C
1
-
1
-
1
3
S
P
G 2E N B L
V P S 1
G 1 A
G 1 B
L O I P
V P S 2
G 4 A
G 4 B
Q B B P
V O U T
G 3
I B B P
I B B N
L O I N
C
L
C
1
2
1
0
L
O
C
A
L

O
S
C

I
N
P
U
T
M
O
D
U
L
A
T
E
D

O
U
T
P
U
T
P
O
W
E
R

I
N
P
U
T

F
I
L
T
E
R
S
L
C
0
8
0
5
L
6

D
N
P
L
C
0
8
0
5
L
7

D
N
P
L
4

D
N
P
L
5

D
N
P
J
P
4
4
+
D
C
A
S
E
+
+
T
P
2
T
P
3
T
P
4
+
+
T
P
5
T
P
6
T
P
7
+
C
C
0
8
0
5
D
C
A
S
E
+
C
D
C
A
S
E
C
C
0
8
0
5
4 3
T 6
A D T L 1 - 1 2
P S
3
2
2
R
3
7

D
N
P
C
C
0
8
0
5
L
C
0
8
0
5
L
C
0
8
0
5
+2
C
C
0
6
0
3
Q B B N
1
0
0
p
F
R
2
3
0
D
N
P
C
7
3
1
4
6
Figure 60. AD8345 Circuitry on AD9775 Evaluation Board
REV. B
AD9775
43
T
P
1
4
W
H
T
B
D
0
8
B
D
0
9
B
D
1
0
B
D
1
1
B
D
1
2
B
D
1
3
A
D
0
0
A
D
0
1
A
D
0
3
A
D
0
4
A
D
0
5
A
D
0
7
A
D
0
8
A
D
0
9
A
D
1
0
A
D
1
1
A
D
1
2
A
D
1
3
A
D
1
4
A
D
1
5
A
D
0
6
A
D
0
2
O
1
N
O
1
P
O
2
N
O
2
P
U
1
A
D
9
7
7
5
+
T
S
P
C
L
K
N
C
L
K
P
D
C
L
K
-
P
L
L
L
F
S
A
D
J
1
F
S
A
D
J
2
I
O
U
T
1
N
I
O
U
T
1
P
I
O
U
T
2
N
I
O
U
T
2
P
P
1
D
0
P
1
D
1
P
1
D
1
0
P
1
D
1
1
P
1
D
1
2
P
1
D
1
3
P
1
D
1
4
P
1
D
1
5
P
1
D
2
P
1
D
3
P
1
D
4
P
1
D
5
P
1
D
6
P
1
D
7
P
1
D
8
P
1
D
9
P
2
D
0
P
2
D
1
P
2
D
1
0
P
2
D
1
1
P
2
D
1
2
P
2
D
1
3
P
2
D
1
4
-
O
P
C
L
K
P
2
D
1
5
-
I
Q
S
E
L
P
2
D
2
P
2
D
3
P
2
D
4
P
2
D
5
P
2
D
6
P
2
D
7
P
2
D
8
P
2
D
9
R
E
F
O
U
T
R
E
S
E
T
S
P
-
C
L
K
S
P
-
C
S
B
S
P
-
S
D
O
S
P
-
S
D
I
V
D
D
A
1
V
D
D
A
2
V
D
D
A
3
V
D
D
A
4
V
D
D
A
5
V
D
D
A
6
V
D
D
C
1
V
D
D
C
2
V
D
D
D
1
V
S
S
D
2
V
D
D
D
3
V
D
D
D
4
V
D
D
D
5
V
D
D
D
6
V
S
S
A
1
V
S
S
A
1
0
V
S
S
A
2
V
S
S
A
3
V
S
S
A
4
V
S
S
A
5
V
S
S
A
6
V
S
S
A
7
V
S
S
A
8
V
S
S
A
9
V
S
S
C
1
V
S
S
C
2
V
S
S
D
1
V
D
D
D
2
V
S
S
D
3
V
S
S
D
4
V
S
S
D
5
V
S
S
D
6
123456789
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
8
0
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
7
0
6
9
6
8
6
7
6
6
6
5
6
4
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
L
F
C
5
9

D
N
P
C
5
7

D
N
P
S
P
S
D
O
S
P
S
D
I
S
P
C
L
K
S
P
C
S
P
B
D
0
3
B
D
0
2
B
D
0
1
B
D
0
0
B
D
0
4
B
D
0
5
B
D
0
6
B
D
0
7
R
6
1
k
C
2
1
0
.
0
0
1
F
C
5
1
0
F
6
.
3
V
D
V
D
D
C
2
2
0
.
0
0
1
F
C
6
1
0
F
6
.
3
V
D
V
D
D
T
P
1
1
W
H
T
T
P
1
0
W
H
T
T
P
9
W
H
T
T
P
8
W
H
T
C
1
6
0
.
1
F
C
4
1
0
F
6
.
3
V
R
7
2
k
0
.
0
1
%
C
1
8
0
.
1
F
R
8
1
k
0
.
0
1
%
C
1
7
0
.
1
F
C
1
5
0
.
1
F
C
3
1
0
F
6
.
3
V
C
5
8

D
N
P
A
V
D
D
C
5
8

D
N
P
C
2
0
0
.
1
F
C
1
9
0
.
1
F
C
1
4
0
.
1
F
C
2
1
0
F
6
.
3
V
A
V
D
D
321
456
J
3
7
J
3
5
J
P
3
6
J
P
3
8
J
P
1
3
J
P
1
5
J
P
1
6
J
P
1
4
J
P
2
8
T
2
T
1
-
1
T
J
P
4
R
9

5
1
R
1
0

5
1
J
P
8
C
7
0

0
.
1
F
R
1
6

1
0
R
4
2
4
9
.
9
S
3
321
456
J
P
3
0
T
3
T
1
-
1
T
J
P
2
9
R
4
3
4
9
.
9
S
4
O
U
T
1
O
U
T
2
R
1
1

5
1
R
1
2

5
1
J
P
1
7
C
7
0

0
.
1
F
R
1
7

1
0
A
G
N
D
;
3
,
4
,
5
A
G
N
D
;
3
,
4
,
5
C
3
6
0
.
1
F
C
3
7
0
.
1
F
C
3
8
0
.
1
F
C
3
9
0
.
1
F
C
4
0
0
.
1
F
C
4
1
0
.
1
F
D
V
D
D
0
.
1
F
C
1
2
0
.
1
F
C
1
1
0
.
1
F
C
4
2
C
1
1
0
F
6
.
3
V
C
L
K
V
D
D
C
2
6
0
.
0
0
1
F
C
1
0
1
0
F
6
.
3
V
D
V
D
D
C
2
5
0
.
0
0
1
F
C
9
1
0
F
6
.
3
V
D
V
D
D
C
2
4
0
.
0
0
1
F
C
8
1
0
F
6
.
3
V
D
V
D
D
C
2
3
0
.
0
0
1
F
C
7
1
0
F
6
.
3
V
D
V
D
D
3 2 1
4 5 6
T
1
T
1
-
1
T
R
1
2
0
0
J
P
2
3
J
P
2
2
R
2
C
1
3
0
.
1
F
R
3
8

1
0
k
J
P
3
3
J
P
2
4
J
P
2
5
1
1 C
X
3
4
9
.
9
D
V
D
D
;

1
4
D
G
N
D
;

7
1
2
1
3
C
X
2
C
X
1
J
P
1
2
D
V
D
D
R
4
0
5
k
J
P
1
A
D
C
L
K
C
L
K
I
N
T
P
1
5
W
H
T
J
P
2
J
P
3
D
A
T
A
C
L
K
S
2
C
2
9

0
.
1
F
J
P
5
D
G
N
D
;
3
,
4
,
5
B
D
1
5
J
P
4
0
O
P
C
L
K
_
3
J
P
2
7
S
6
D
G
N
D
;
3
,
4
,
5
I
Q
S
5
O
P
C
L
K
A
G
N
D
;
3
,
4
,
5
C
4
5 J
P
3
4
O
P
C
L
K
1
1
J
P
3
1
J
P
2
6
J
P
3
2
B
D
1
4
R
3
9
1
k
1
2
1
3
7
4
V
C
X
8
6
7
4
V
C
X
8
6
S
1
C
G
N
D
;
3
,
4
,
5
R
C
0
6
0
3
C C 0 6 0 3 1
k
R
3
1
k
R
C
0
6
0
3
c
c
A
C
L
K
X
R C 0 6 0 3
1
p
F
C
2
7
C
L
K
N
C
L
K
P
C
C
0
6
0
3
C
C
0
6
0
3
C
C
0
6
0
3
C
C
0
6
0
3
B
C
A
S
E
c
J
P
3
9
R
5
RC0603
R
C
0
6
0
3
C
C
0
6
0
3
B
C
A
S
E
B
C
A
S
E
C
C
0
6
0
3
B
C
A
S
E
C
C
0
6
0
3
0
.
0
1
F
CC0805
D
V
D
D
;
1
4
D
G
N
;
7
CC0805
B
C
A
S
E
C
C
0
6
0
3
c
C
C
0
6
0
3
C
C
0
6
0
3
B
C
A
S
E
B
C
A
S
E
RC1206
J
P
4
6
8
J
P
4
7
9
1
0
7
4
V
C
X
8
6
D
V
D
D
;
1
4
D
G
N
;
7
I
Q
C
C
0
6
0
3
B
C
A
S
E
C
C
0
6
0
3
C
C
0
6
0
3
C
C
0
8
0
5
B
C
A
S
E
C
C
0
6
0
3
C
C
0
6
0
3
C
C
0
6
0
3
B
C
A
S
E
C
C
0
6
0
3
CC0603
CC0603
C
C
0
6
0
3
C
C
0
8
0
5
C
C
0
8
0
5
C
C
0
8
0
5
C
C
0
8
0
5
C
C
0
8
0
5
R
C
0
6
0
3
R
C
0
6
0
3
R
C
0
6
0
3
C
C
0
6
0
3
R
C
1
2
0
6
R
C
0
6
0
3
C
C
0
8
0
5
C
C
0
6
0
3
R
C
0
6
0
3
R
C
0
6
0
3
S
P
S
D
O
U
4
U
4
U
3
I
Q
Figure 61. AD9775 Clock, Power Supplies, and Output Circuitry
REV. B
AD9775
44
R
P
1

2
2
A
D
1
5
A
D
1
4
A
D
1
3
A
D
1
2
A
D
1
1
A
D
1
0
A
D
0
9
A
D
0
8
A
D
0
7
A
D
0
6
A
D
0
5
A
D
0
4
A
D
0
3
A
D
0
2
A
D
0
1
A
D
0
0
2468
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
2
6
2
8
3
0
3
2
3
4
3
6
3
8
4
0
135791
1
1
3
1
5
1
7
1
9
2
1
2
3
2
5
2
7
2
9
3
1
3
3
3
5
3
7
3
9
1
1
6
R
P
1

2
2
2
1
5
R
I
B
B
O
N
R
2
2
1
R
3
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
R
9
9
1
0
R
1
R
C
O
M
R
1
1
R
2
2
R
3
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
9
R
9
1
0
R
C
O
M
R
P
5
5
0
R
P
1

2
2
3
1
4
R
P
1

2
2
4
1
3
R
P
1

2
2
5
1
2
R
P
1

2
2
6
1
1
R
P
1

2
2
7
1
0
R
P
2

2
2
8
9
R
P
2

2
2
1
1
6
R
P
2

2
2
2
1
5
R
P
2

2
2
3
1
4
R
P
2

2
2
4
1
3
R
P
2

2
2
5
1
2
R
P
2

2
2
6
1
1
R
P
2

2
2
7
1
0
R
P
2

2
2
8
9
R
2
2
1
R
3
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
R
9
9
1
0
R
1
R
C
O
M
R
1
1
R
2
2
R
3
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
9
R
9
1
0
R
C
O
M
D
A
T
A
-
A
J
1
A
D
C
L
K
R
1
5
2
2
0
R
P
6
5
0
R
P
7
D
N
P
R
P
8
D
N
P
3
2
1
7
4
V
C
X
8
6
JC
L
K
K
C
L
R
P
R
E
Q
_
Q
312
O
P
C
L
K
_
3
D
V
D
D
O
P
C
L
K
_
2D
V
D
D
;

1
4
A
G
N
D
;

7
U
4
7
4
L
C
X
1
1
2
U
7
5
6
4
1
5
O
P
C
L
K
3
2
1
7
4
V
C
X
8
6
D
V
D
D
;

1
4
A
G
N
D
;

7
U
3
6
5
4
7
4
V
C
X
8
6
D
V
D
D
;

1
4
A
G
N
D
;

7
U
3
8
1
0
9
7
4
V
C
X
8
6
D
V
D
D
;

1
4
A
G
N
D
;

7
U
3
C
X
2
C
X
1
C
X
3
C
3
3
0
.
1
F
C
3
0
4
.
7
F
6
.
3
V
D
V
D
D
6
5 4
7
4
V
C
X
8
6
D
V
D
D
;

1
4
A
G
N
D
;

7
U
4
C
3
4
0
.
1
F
C
3
1
4
.
7
F
6
.
3
V
D
V
D
D
JC
L
K
K
C
L
R
P
R
E
Q
_
Q
1
1
1
2
1
3
7
4
L
C
X
1
1
2
U
7
97
1
0
1
4
A
G
N
D
;

8
D
V
D
D
;

1
6
C
5
3
0
.
1
F
C
5
2
4
.
7
F
6
.
3
V
D
V
D
D
C
C
0
8
0
5
A
C
A
S
E
C
C
0
8
0
5
A
C
A
S
E
C
C
0
8
0
5
A
C
A
S
E
R
C
1
2
0
6
Figure 62. AD9775 Evaluation Board Input (A Channel) and Clock Buffer Circuitry
REV. B
AD9775
45
R
2
1
D
N
P
C
L
K
V
D
D
C
G
N
D
;
5
C
L
K
V
D
D
;
8
A
C
L
K
X
1
2
0
R
1
3
C
4
7
1
n
F
1
2
0
R
4
R
1
8
2
0
0
R
1
4
2
0
0
R
C
0
8
0
5
M
C
1
0
0
E
P
T
2
2
R C 0 8 0 5
R C 0 8 0 5
R
C
0
8
0
5
C
5
0
0
.
1
F
C
4
3
4
.
7
F
6
.
3
V
D
V
D
D
C
5
1
0
.
1
F
C
4
4
4
.
7
F
6
.
3
V
D
V
D
D
D
G
N
D
;

7
D
V
D
D
;

1
4
U
5
7
4
A
C
1
4
1
2
D
G
N
D
;

7
D
V
D
D
;

1
4
U
5
7
4
A
C
1
4
1
2
1
3
D
G
N
D
;

7
D
V
D
D
;

1
4
U
5
7
4
A
C
1
4
4
3
D
G
N
D
;

7
D
V
D
D
;

1
4
U
5
7
4
A
C
1
4
1
0
1
1
D
G
N
D
;

7
D
V
D
D
;

1
4
U
5
7
4
A
C
1
4
6
5
D
G
N
D
;

7
D
V
D
D
;

1
4
U
5
7
4
A
C
1
4
8
9
123456
P
1
S
P
I

P
O
R
T
S
P
C
S
B
S
P
C
L
K
S
P
S
D
I
S
P
S
D
O
D
G
N
D
;

7
D
V
D
D
;

1
4
U
6
7
4
A
C
1
4
1
2
D
G
N
D
;

7
D
V
D
D
;

1
4
U
6
7
4
A
C
1
4
1
3
1
2
D
G
N
D
;

7
D
V
D
D
;

1
4
U
6
7
4
A
C
1
4
3
4
D
G
N
D
;

7
D
V
D
D
;

1
4
U
6
7
4
A
C
1
4
1
1
1
0
D
G
N
D
;

7
D
V
D
D
;

1
4
U
6
7
4
A
C
1
4
5
6
D
G
N
D
;

7
D
V
D
D
;

1
4
U
6
7
4
A
C
1
4
9
8
R
5
0
9
k
R
4
8
9
k
R
4
5
9
k
R
C
0
8
0
5
R
C
0
8
0
5
R
C
0
8
0
5
A
C
A
S
E
C
C
8
0
5
A
C
A
S
E
C
C
8
0
5
C
6
0
0
.
1
F
C
4
9
4
.
7
F
6
.
3
V
C
L
K
D
D
A
C
A
S
E
C
C
8
0
5
C
C
4 3
6
U
8
2
1
7
U
8
C
C
C
CC805
CC805 CC805
C C
J
P
4
1
J
P
4
2
C
4
6
0
.
1
F
R
2
0
D
N
PR
C
0
8
0
5
R
2
2
D
N
P
R
2
4
D
N
P
R
C
0
8
0
5
R
C
0
8
0
5
R
C
0
8
0
5
C
4
8
1
n
F
C
L
K
V
D
D
;
8
C
G
N
D
;
5
M
C
1
0
0
E
P
T
2
2
R
P
3

2
2
B
D
1
5
B
D
1
4
B
D
1
3
B
D
1
2
B
D
1
1
B
D
1
0
B
D
0
9
B
D
0
8
B
D
0
7
B
D
0
6
B
D
0
5
B
D
0
4
B
D
0
3
B
D
0
2
B
D
0
1
B
D
0
0
2468
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
2
6
2
8
3
0
3
2
3
4
3
6
3
8
4
0
135791
1
1
3
1
5
1
7
1
9
2
1
2
3
2
5
2
7
2
9
3
1
3
3
3
5
3
7
3
9
1
1
6
R
P
3

2
2
2
1
5
R
I
B
B
O
N
R
2
2
1
R
3
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
R
9
9
1
0
R
1
R
C
O
M
R
1
1
R
2
2
R
3
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
9
R
9
1
0
R
C
O
M
R
P
1
2
5
0
R
P
3

2
2
3
1
4
R
P
3

2
2
4
1
3
R
P
3

2
2
5
1
2
R
P
3

2
2
6
1
1
R
P
3

2
2
7
1
0
R
P
4

2
2
8
9
R
P
4

2
2
1
1
6
R
P
4

2
2
2
1
5
R
P
4

2
2
3
1
4
R
P
4

2
2
4
1
3
R
P
4

2
2
5
1
2
R
P
4

2
2
6
1
1
R
P
4

2
2
7
1
0
R
P
4

2
2
8
9
R
2
2
1
R
3
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
R
9
9
1
0
R
1
R
C
O
M
R
1
1
R
2
2
R
3
3
R
4
4
R
5
5
R
6
6
R
7
7
R
8
8
9
R
9
1
0
R
C
O
M
D
A
T
A
-
B
J
2
R
P
1
1
5
0
R
P
9
D
N
P
R
P
1
0
D
N
P
C
L
K
V
D
D
C
L
K
V
D
D
C
L
K
N
C
L
K
P
Figure 63. AD9775 Evaluation Board Input (B Channel) and SPI Port Circuitry
REV. B
AD9775
46
Figure 64. AD9775 Evaluation Board Components, Top Side
Figure 65. AD9775 Evaluation Board Components, Bottom Side
REV. B
AD9775
47
Figure 66. AD9775 Evaluation Board Layout, Layer One (Top)
Figure 67. AD9775 Evaluation Board Layout, Layer Two (Ground Plane)
REV. B
AD9775
48
Figure 68. AD9775 Evaluation Board Layout, Layer Three (Power Plane)
Figure 69. AD9775 Evaluation Board Layout, Layer Four (Bottom)
REV. B
AD9775
49
OUTLINE DIMENSIONS
80-Lead, Thermally Enhanced, Thin Plastic Quad Flat Package [TQFP]
(SV-80)
Dimensions shown in millimeters
0.15
0.05
0.27
0.22
0.17
0.20
0.09
0.50 BSC
GAGE PLANE
0.25
7
3.5
0
1.05
1.00
0.95
1
20
21
41
40
60
80 61
PIN 1
TOP VIEW
(PINS DOWN)
14.00 SQ
12.00 SQ
SEATING
PLANE
1.20
MAX 0.75
0.60
0.45
1
20
21
41
40
60
80 61
6.00 SQ
BOTTOM
VIEW
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-026-ADD-HD
REV. B
AD9775
50
Revision History
Location Page
3/03Data Sheet changed from REV. A to REV. B.
Changes to REGISTER DESCRIPTIONAddress 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Changes to Equation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Changes to Figure 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/03Data Sheet changed from REV. 0 to REV. A.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Edits to REGISTER DESCRIPTIONADDRESS 02h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Edits to REGISTER DESCRIPTIONADDRESS 03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Edits to REGISTER DESCRIPTIONADDRESS 07h, 0Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Edits to Equation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Edits to MSB/LSB TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Edits to PROGRAMMABLE PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Added new Figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Renumbered Figures 1569 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Added TWO PORT DATA INPUT MODE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Edits to PLL ENABLED, TWO PORT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Edits to Figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Edits to Figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Edits to PLL DISABLED, TWO PORT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Edits to Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Edits to Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Edits to Figure 26a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Edits to COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . 31
Edits to EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Edits to Figures 5659 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Replaced Figures 6069. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
51
52
C
0
2
8
5
8
3
/
0
3
(
B
)

14-Bit, 160 Msps 2 Interpolating Dual Txdac+: Ⴛ/4Ⴛ/8Ⴛ D/A Converter

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

14-Bit, 160 Msps 2 Interpolating Dual Txdac+: Ⴛ/4Ⴛ/8Ⴛ D/A Converter

Uploaded by

Copyright:

Available Formats

AD9775

Figure 32. Implementation of a Complex Modulator

Figure 33. Quadrature Modulator

Figure 35. Two-Stage Complex Upconversion

Figure 37. Image Rejection with Multicarrier Signals

Figure 52. DAC Output Equivalent Circuit

/2000. The evaluation board also

You might also like