FX/MX128

CML Microcircuits
COMMUNICATION SEMICONDUCTORS
D/128/3 April 2005

Audio Band Scrambler

Provisional Information

Features
Full-Duplex Audio Processing On-Chip Filters Carrier Rejection >55dB Uses IF (10.24 MHz) Clock Excellent Audio Quality Low Power Operation (3.0V) Battery Powered Portability

Applications
Cordless Telephones Wireless PBX Two-Way Radio Leisure Radio (FRS, GMRS, MURS, PMR446)

1.1 Brief Description The FX/MX128 is a full-duplex frequency inversion scrambler designed to provide secure conversations. The Rx and Tx audio paths consist of the following: 1. A switched-capacitor balanced modulator with high baseband and carrier rejection. 2. A 3.3 kHz inversion carrier (injection tone). 3. A 3100 Hz lowpass filter. 4. Input op-amps with externally adjustable gain. The FX/MX128 uses mixed signal CMOS switched-capacitor filter technology and operates from a single supply in the range of 3.0 to 5.5 volts. The inversion carrier's frequency and filter switching clock are generated on-chip using an external 10.24 MHz or 3.58/3.6864 MHz crystal or clock input (selectable). This device is available in the following package styles: 16-pin SOIC,TSSOP and PDIP.

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CONTENTS
Section 1.2 1.3 1.4 1.5 1.6 1.7 Page

Block Diagram ..........................................................................................................3 Signal List .................................................................................................................4 External Components ..............................................................................................5 Application ................................................................................................................6 Application Notes .....................................................................................................6 Performance Specification ......................................................................................7
1.7.1 1.7.2 Electrical Performance ................................................................................................7 Packaging..................................................................................................................10

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1.2

Block Diagram

Figure 1: Block Diagram

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1.3
Pin No. 1 2 3 4 5

Signal List
Signal Name XTALN XTAL/CLOCK TXOUT TX GAIN AMP OUT TXIN VSS VBIAS RXIN RX GAIN AMP OUT RXOUT CLR CLOCK SELECT VDD I/P O/P N/C = = = Type O/P I/P N/C O/P O/P Description

All Packages

6 7 8 9 10 11 12 13 14 15 16 Notes:

I/P N/C Power O/P N/C I/P O/P O/P I/P I/P Power Input Output

This is the output of the clock oscillator inverter. 10.24 MHz, 3.58/3.6864 MHz, or an externally derived clock is injected at this pin. See Figure 1. No connection should be made to this pin. This is the analogue output of the transmit channel. It is internally biased at VDD/2. This is the output pin of the transmit channel gain adjusting opamp. See Figure 3 for gain setting components. This is the analogue signal input to the transmit channel. This input goes to a gain adjusting op-amp whose gain is set by external components. See Figure 3. No connection should be made to this pin. Negative supply (GND) This is an internally generated bias voltage output (VDD/2). It should NOT be decoupled with a capacitor. No connection should be made to this pin. This is the analogue signal input to the receive channel. This input goes to a gain adjusting op-amp whose gain is set by external components. See Figure 3. This is the output pin of the receive channel gain adjusting opamp. See Figure 3 for gain setting components. This is the analogue output of the receive channel. It is internally biased at VDD/2. A logic 1 on this input selects the invert mode. A logic 0 selects the clear (not inverted) mode. Selects either 10.24 or 3.58/3.6864 MHz clock frequency. A logic 1 selects 10.24 MHz, and a logic 0 selects 3.58/3.6864 MHz. This input is internally pulled high. Positive supply of 3.0V to 5.5 V

No Connection

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External Components

Components X1 R1 C1 C2 C3

Value 10.24MHz 1.0M 0.47F 22.0pF 22.0pF

Value 3.58/3.6864 MHz 1.0M 0.47F 33.0pF 47.0pF

Note: Xtal circuitry shown is in accordance with CMLs Xtal Application Note.

Figure 2: Recommended External Components

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1.5

Application

Figure 3: Block Diagram of a Typical Application of the FX/MX128 (Cordless Phone)

1.6

Application Notes
Carrier Frequency Upper Cutoff Frequency Lower Cutoff Frequency = = = (3.2995kHz / 10.24MHz) * XTAL frequency (2.800kHz / 10.24MHz) * XTAL frequency (400Hz / 10.24MHz) * XTAL frequency

Formulae for calculating the carrier frequency, upper cutoff frequency and lower cutoff frequency with clock select pin high are as follows:

Formulae for calculating the carrier frequency, upper cutoff frequency and lower cutoff frequency with clock select pin low are as follows: Carrier Frequency Upper Cutoff Frequency Lower Cutoff Frequency = = = (3.2995kHz / 3.415MHz) * XTAL frequency (2.800kHz / 3.415MHz) * XTAL frequency (400Hz / 3.415MHz) * XTAL frequency

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1.7

Performance Specification

1.7.1 Electrical Performance

Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. General Supply (VDD - VSS) Voltage on any pin to VSS Current in or out VDD and VSS pins Current in or out of any other pin E4/P3/D4 Packages Total Device Dissipation (P3 and D4) at TAMB = 25C ...Derating (P3 and D4) Total Device Dissipation (E4) at TAMB = 25C ...Derating (E4) Storage Temperature Operating Temperature Min. -0.3 -0.3 -30 -20 Min. -55 -40 Max. 7.0 VDD + 0.3 +30 +20 Max. 1000 13 400 5.3 +125 +85 Units V V mA mA Units mW mW/C mW mW/C C C

Operating Limits Correct operation of the device outside these limits is not implied. Min. Supply (VDD - VSS) Operating Temperature Clock Frequency 3.0 -40 Max. 5.5 +85 10.24 Units V C MHz

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Operating Characteristics For the following conditions unless otherwise specified: VDD = 3.3V at TAMB = 25C Clock Frequency = 10.24MHz Audio Level 0dB ref. at 1kHz = (VDD-1) x 150mVRMS e.g. VDD = 3.3V 0dB = 345mVRMS. Notes Static Values Supply Current Input Impedance Digital Amplifiers Output Impedance (RXOUT, TXOUT) Input Logic 1 Voltage Input Logic 0 Voltage Dynamic Values General Analogue Signal Input Levels Analogue Output Noise Clear Mode Passband -3dB Cutoff Frequencies Low High Passband Ripple (300-3000Hz) Rx Channel Tx Channel Passband Ripple (500-2750Hz) Rx Channel Tx Channel Filter Attenuation at 3.3 kHz Rx and Tx Channel Filter Attenuation at 3.6 kHz Rx and Tx Channel 3 30 dB 3 3 3000 300 Hz Hz 3 3,4 -16.0 2.5 3 5.0 dB mVRMS 1 1 2 2 100 1.0 70% 10.0 1.0 30% k M k VDD VDD 2.0 3.0 mA Min. Typ. Max Units

3 3

0 0

3.6 2.9

dB dB

3 3

0 0

2.2 2.0

dB dB

45

dB

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Notes Passband Gain (@1kHz ref.) Rx and Tx Channel Switched-Capacitor Filter Sampling Carrier Frequency Invert Mode Combined Tx and Rx Response Passband -3dB Cutoff Frequencies Low High Passband Gain Distortion (@1kHz) Passband Gain (@1kHz ref.) Low Frequency Roll-off (<200 Hz) Invert Mode Single Channel Response Unwanted Modulation Products Rx and Tx Channel Carrier Breakthrough Rx and Tx Channel Baseband Breakthrough Rx and Tx Channel Operating Characteristics Notes: 1. 2. 3. Batch sampled only By characterisation only 3 3 3 3 3,5 3 3

Min. -1.5

Typ. 211.066 3298

Max 0.5

Units dB kHz Hz

2800 -3 -2.5 12

1.75 -1.5

400 0.5 2.75 0

Hz Hz dB % dB dB/oct.

2 2 2 -40 dB -55 dB -40 dB

Includes the combined effects of an external single pole anti-alias (low pass) input filter and an external single pole reconstruction (low pass) output filter, each having a corner frequency of 10kHz. See Figure 3 for an example circuit. Short circuit Rx or Tx input, measure noise at corresponding analogue output, in 30kHz bandwidth Op Amp gain 0dB Clear mode only

4. 5. 6.

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1.7.2 Packaging

Figure 4: 16-pin SOIC Mechanical Outline: Order as part no. FX128D4 or MX128DW

Figure 5: 16-pin PDIP Mechanical Outline: Order as part no. FX128P3 or MX128P

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Figure 6: 16-pin TSSOP Mechanical Outline: Order as part no. FX128E4 or MX128E4

Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.

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