Agilent HMMC-5038 38 GHZ Lna: Data Sheet
Agilent HMMC-5038 38 GHZ Lna: Data Sheet
Data Sheet
Features
Low Noise Figure: 4.8 dB Frequency Range: 37 - 40 GHz High Gain (Adjustable): 3 v, 120 mA @ 23 dB Gain 3 v, 80 mA @ 20 dB Gain 50 Input/Output Matching Chip Size: Chip Size Tolerance: Chip Thickness: Pad Dimensions: 1630 760 m (64.2 29.9 mils) 10 m (0.4 mils) 127 15 m (5.0 0.6 mils) 80 80 m (3.1 3.1 mils)
Description
The HMMC-5038 MMIC is a highgain low-noise amplifier (LNA) designed for communication receivers that operate from 37 GHz to 40 GHz. The gain of this four stage LNA can be adjusted by altering the gate bias of the output two, or three, stages while maintaining optimum noise figure bias for the input stage(s). Large FETs provide high power handing capability to avoid power compression. The backside of the chip is both RF and DC ground. This helps simplify the assembly process and reduce assembly related performance variations and costs. The HMMC-5038 is fabricated using a PHEMT integrated circuit structure that provides good noise and gain performance.
VD1,2-3-4
VG1,2,3-4 IDD Pin Tch TA Tst Tmax
[1]Absolute [2]
maximum ratings for continuous operation unless otherwise noted. Refer to DC Specifications / Physical Properties table for derating information.
1-9
DC Specifications/Physical Properties[1]
Symbol Parameters/Conditions Low Noise Drain Supply Operating Voltages First Stage Drain Supply Current (VDD = 3 V, VG1 -0.8 V) Drain Supply Current for Stage 2, 3, and 4 Combined (VDD = 3 V, VGG -0.8 V) Gate Supply Operating Voltages (IDD 120 mA) Pinch-off Voltage (VDD = 3 V, IDD 10 mA) Thermal Resistance (Channel-to-Backside at Tch = 160C) Channel Temperature[3] (TA = 125C, MTTF > 106 hrs, V DD = 3 V, IDD = 120 mA)
[2]
Min. 2
Typ. 3 22 98 -0.8
Max. 5
-2
-1.2 62 150
-0.8
Volts C/Watt C
Backside ambient operating temperature TA = 25C unless otherwise noted. resistance (C/Watt) at a channel temperature T(C) can be estimated using the equation: (T) 62 [T(C)+273] / [160C+273]. [3] De-rate MTTF by a factor of two for every 8C above Tch.
RF Specifications
(TA = 25C, VDD = 3 V, IDD = 120 mA, Z0 = 50)
Symbol BW Gain Gain S21/T (RLin)MIN (RLout)MIN Isolation P-1dB NF NF/T
[1]Gain [2]
Min. 37 20
Typ.
Max. 40
23 0.5 -.04
Small Signal Gain Flatness Temperature Coefficient of Gain Minimum Input Return Loss w/o external capacitive matching[2] Minimum Output Return Loss Reverse Isolation Output Power at 1dB Gain Compression Noise Figure[3] 8 12
dB dB/C
Temperature Coefficient of NF
may be reduced by biasing for lower I DD. Increasing IDD will increase Gain. Minimum input return may be improved by approximately 3 dB by including a small capacitive (30 fF) stub on the input transmission line. [3]Noise Figure may be further reduced by optimizing DC bias conditions.
1-10
HMMC-5038/rev.3.3
Applications
The HMMC-5038 low noise amplifier (LNA) is designed for use in digital radio communication systems and point-to-multipoint links that operate within the 37 GHz to 40 GHz frequency band. High gain and low noise temperature make it ideally suited as a front-end gain stage in the receiver. The MMIC solution is a cost effective alternative to hybrid assemblies.
transmission line. This capacitance complements the bond wire inductance to complete the input matching network. No ground wires are needed because ground connections are made with plated through-holes to the backside of the device.
Assembly Techniques
It is recommended that the RF input and RF output connections be made using either 500 line/ inch (or equivalent) gold wire mesh, or dual 0.7 mil diameter gold wire. The RF wires should be kept as short as possible to minimize inductance. The bias supply wires can be a 0.7 mil diameter gold. GaAs MMICs are ESD sensitive. ESD preventive measures must be employed in all aspects of storage, handling, and assembly. MMIC ESD precautions, handling considerations, die attach and bonding methods are critical factors in successful GaAs MMIC performance and reliability. Agilent application note #54, "GaAs MMIC ESD, Die Attach and Bonding Guidelines" provides basic information on these subjects.
1-11
40
4 8 12 16 20 24
4 8 12 16 Output 20 24
30
20 Isolation 10
Spec Range
(37 - 40 GHz)
50
Input
36
37
38
Frequency (GHz)
39
40
41
42
43
100
36
37
38
Frequency (GHz)
39
40
41
42
43
10 8
6 4 2 0 36
37
38
Frequency (GHz)
39
40
41
42
43
VDD=3V
30
20
VDD=4V, ID1=25 mA
SS Gain
30
25
15
25
Pout (dBm)
Gain (dB)
20
10
P-1
20
15
15
3 40
60
80
IDS (mA)
100
120
140
10 160
0 40
60
80
100
120
10 140
ID2,3,4 (mA)
1-12
HMMC-5038/rev.3.3
Gain (dB)
Gain
Gain
(@100 pF)
Cb
VD1
VG2
VD2-3-4
RF INPUT
IN
RF OUTPUT
VG1 VG3-4
Cb
(@100 pF)
Cb
RF INPUT
IN
RF OUTPUT
Cb
(@100 pF)
Cb
(b) Separate first-stage gate bias supply. This diagram shows an optional variation to the VG2 jumper-wire bonding scheme presented in (a).
Figure 6. Common Assembly Diagrams (Note: To assure stable operation, bias supply feeds should be bypassed to ground with a capacitor, Cb > 100 nF typical.)
80 350 620 820 1070 1360 660 500 330 80 0 0 120 600 1090 0 760
HMMC-5038/rev.3.3
0 1550 1630
Notes:
1-14
HMMC-5038/rev.3.3