IEEE Transactions on Power Apparatus and Systems, Vol. PAS-101, No.

2 February 1982 A PROTOTYPE OF MULTIPROCESSOR BASED DISTANCE RELAY J.C. BASTIDE, Non Member, IEEE P. BORNARD, Member, IEEE Electricite de France Clamart, France

491

Abstract - This paper concerns the design and realization of a digital relay for EHV systems. It describes the algorithm which has been used and the main principles of operation. Then it shows how a prototype has been built with four 16-bit microprocessors, to allow the simultaneous real-time computation of three apparent impedances. The hardware and software architecture are described. The paper also presents the results of the tests carried out on the relay: a tripping signal is sent within one period of 50 Hz for all faults (half a period for near-by short-circuits). Furthermore, single-phase tripping, directional discrimination and power-swing detection are provided. INTRODUCTION
The development of a digital distance relay is part of a large EDF scheme, the PANDOR project, the aim of which is to improve fault clearance times by increasing the speed of relays and circuit-breakers. On the other hand, an assessment of the digitalization of most of EHV substation equipments (protections, communications, automation devices...) is included in the scope of this project. The choice of a distance protection was made according to the present EDF's policy. In this respect, studies of digital differential relays are currently in progress for some particular problems such as multiple-end lines. Without reviewing the classical discussion about the pros and cons of digital relays [I] , [2] , it is useful to emphasize their main advantages which have guided us for the design of a prototype: - flexibility (which means a possibility of changing algorithms and logic), - fau lt-tolerance (which leads to a multiprocessor structure because of the present lack of fault-tolerant chips) - reduction of costs when included in an homogeneous design of all EHV substation equipments (which at the moment implies the use of microprocessors). The aim was to follow these three directions to realize a prototype giving a tripping signal within a 50 Hz period for all faults, within half a period for severe short-circuits, computing impedances with enough accuracy to allow a first zone of 80 % of the protected line, and providing single-phase tripping, directional discrimination and power-swing detection.

with R =a + a2 and L=-a2 T

(3)

Writing equation (2) for m successive samples gives a relationship of the form:
M.

la]

[vi +

[e]

(4)

where M is the matrix

I(t)

(t)

[a
[e]
=

al
-e (t )
It

and

[v]

Il=

1I I
Lv

v(t

)]-

(tm)

L-

(t M)i

If we denote by AT the transpose of matrix A: m T 2

j I
=

(t) =[e] .[e] = F (a)

F (a) = [la]T. MT. M .

a] - 2 [af . MT.[vi +viT . [vJ

[a*], the value of [a] which minimizes F (a), is such that

3F

(a*)= 0 a

which implies MT. M. [a] = MT. [vi

The relay solves equation (5) denoting MT. m
m -I -ml
=

(5)

(P..)
iI
m

j =0

A1 i (t-jT)

7 i(t-jT).i[t-(j+l)T] j =O0
(6)
m

(Pij)

ALGORITHM FOR FAULT MEASUREMENT

The algorithm which has been implemented is based on a mean-square-error minimisation : the resistance R and inductance L of the line at time t are linked to the current i (t) and voltage v (t) by the equation
-

m -I

j=0
=

7 i(t-jT). i [t-(j+l)TI

2, 7j=l i2(t-jT)

and M

lyv
[
m

(bi)
-

(t) + e (t) = R i (t) +L i (t) - Ti (t - T) () where T is the sampling period and e (t) represents the difference between the model of the line and the actual phenomena (noise, shunt capacitance, measurement errors). Equation (l) can be written:
v v

(b)

j =0
-

i(t-jT).v(t-jT)

(7)

(t) + e (t) = ali (t) + a2 i (t - T)

(2)

j =

0 itt-(j+l)TI.v(t-jT)J
P22 b1 - P12b2
2

[ails given by a1 =P1 P22 81 SM 384-7 A paper recommended and approved by the IEEE Power System Relaying Committee of the IEEE Power Engineering Society for presentation at the IEEE PES Summer Meeting, Portland, Oregon, July 26-31, 1981. Manuscript submitted January 30, 1981; made available for printing April 22, 1981.

and

a2 X -

Pl

P12 2 1 12 ll 22
b2
-

R and L are obtained through equations (3). In steady-state conditions, R and L computed with the above

1982 IEEE

492
formula
are:

i R =R

Lo tg2

wT

O)T L =Lo sinwT

where
R
0

(8)
the

inductance,cothe system pulsation. When v (t) = Vm sin (wt +q) + V sin (at +f) ~~~p and i (t) = Im sinwt, it can be shown that the maximum
m

and

Lo

are

actual

values

o'f

resistance

and

sonable, and well suited to a microprocessor implementation.

good speed-accuracy compromise large convergence speed for high current faults due to the use of squared values, and the lack of singularities the insensibility of the computed distance of a fault versus the system frequency shifts the smallness of errors induced by a saturation of the analog to digital converters, used to limit the range of currents. However, the number of arithmetical operations is rea-

the mean-square minimization algorithm

a a

were

relative
AR

errors on

R and L

are

given by
L
=

MAIN PRINCIPLES OF OPERATION

V

=max

Vp
Vm

IV kR and p cos ad

sin?

kL

kL, which is very similar to kR, is illustrated by figure 1.

To detect and trip correctly all the types of fault on an EHV network, it was decided to build a relay computing simultaneously 3 apparent line-impedances, from either the 3 phase - to - phase or the 3 phase - to - ground potential/current pairs. This solution allows a fast tripping decision to be taken due to the rapid choice of the pairs to be processed. A simplified flow-chart of the relay is given on figure 2.
I
I

1.2

1.0

Voltage and current sampling on the 3 phases

no

06

zero-sequence detection

kes
currents

04

Computation of phase- to-phase

v and i
F in Hz

Computation of
compens ated

02

100

200

300

400

500

600

Figure

1:

kL coefficient

versus

Computation of the 3 phase-phase apparent impedances

no/

Computation of

ground

the 3

phase-to->

apparent impedance

with T = 0,83 ms and mT = 15 ms For more complex input signal spectra, analytical studies become almost impossible, because of the non-linearity of the algorithm. It can be shown that the sensitivity of L to current harmonics increases slightly with their frequency. However, when comparing these performances to other algorithms, it must be beared in mind that this sort of spectrum studies implicitly assume the stationnarity of voltages and currents, which is not very realistic (in particular in the case of fault on an overloaded line).

One or more impedance is \ inside the tripping characteris tic

yes

Phase- selection|

directional

discriminatio
-

zone de termination

|power-swing detection
dispatch of tripping signals and/or information

Choice of window length and sampling frequency

A window length (mT) of three quarters of a cycle (15 ms) has been chosen as a good compromise between accuracy (quality of digital filtering) and speed, in accordance to the targets described above. The sampling frequency, fe' is theoretically limited on its high values by the quantization noise : the effect of a finite word-length for data acquisition is very severe over 2 kHz for algorithms using current differenciation with 12-bit samples (it induces a large decrease in the signal/noise ratio). On the other hand, the 50 Hz delay due to the use of an anti-aliasing analog filter gives a low boundary to f (although it should be emphasized that the aim of a digital ,e relay is not the original signal reconstruction, and that a slight aliasing effect can be tolerated). But in fact, the decisive criteria in the choice of f are: the need for a sufficient number of samples in tRe window for correct digital filtering (i.e. f .>1 kHz) - and of course the computation etime which must be less than a sampling period for continuous real-time impedance relay-

Figure 2 : simplified flow-chart of the relay

Zero-sequence detection
In steady-state conditions, the relay computes the 3 impedances from phase-phase data. After each new set of samples, it reckons zero-sequence quantities, 3 I and 3- VO. If one of these two values exceeds a threshold cPuring two contiguoussets of samples, the 3 distance-units are commuted on phaseto-ground data (phase voltages and compensated currents i hae+ K IO). The threshold for 3 1 is in fact equal to the uar er of the maximum value of any phase current during the last 50 Hz period (with a minimum step to avoid commutation during no-load conditions).
This characteristic is shown on figure 3 in the (R, X) plan. It is a parallelogram to simplify the tripping criteria. The 82.50 angle is due to the use of a comparison between the computed absolute-value of R and the maximum fault-resis-

ing.
(24

Tripping characteristic

That is why a sampling frequency of 1200 Hz was chosen data in a 50 Hz period, 18 in the window). In conclusion, the main advantages which were found for

493
tance

RD, according to equation (8).

the relay settings, one of the three downstream zones or the upstream zone (zone 4) is chosen.

Power-swing detection To prevent incorrect tripping during out-of-synchronism conditions or power-swings, the rate of change of the resistance is calculated whenever there is a presumption of phase to - phase or three-phase short-circuit. If this rate is not sufficient, the tripping signals are blocked, and a power-swing alarm is sent. This function is suppressed in the case of grounded faults.

Dispatch of tripping signals

The fall back speed of a relay, after short-circuit clearance, is sometimes nearly as important as the tripping speed (in case of breaker failure for example). Thus, the 3 phase orders to the circuit-breaker and their associated information are stopped as soon as all the impedances come out the tripping characteristic, or when the currents of the phases to be opened drop below a very low threshold (which means that the breaker has worked correctly). HARDWARE AND SOFTWARE ARCHITECTURE Figure 3 : tripping characteristic
When an impedance enters the characteristic, a corresponding counter is initialized and will be incremented at every next sampling period. The result qf the computation is considered capable of initiating a tripping signal either when the impedance has converged (i.e. is stable for 2.5 ms in a rectangle of RD/4 on the eighth of the limit inductance of zone 1) or the counter is equal to eighteen (number of data in the sampling window).

Phase selection

The relay must provide single-phase tripping. In addition, in case of polyphase faults, it has to decide which of the three potential/current processed 'pairs is/are to be considered for direction and zone determination. When the distance units are fed with phase to - ground data, the P 1 matrix element (equation 6) is used. The reason for this is the ratio of P11 for a faulted phase on P11 for an healthy phase can be shown fo be always exceeding 4., whereas this ratio does not exceed 1.5 if it concerns two faulted phases.Finally, the criterion for phase selection between distance elements which have their impedance inside the tripping characteristic is: there is a single phase -to - ground fault on phase x if P11 of phase x is more terms are than 2.5 times P11 of the other phases (P calculated with compensated currents). In the case of polyphase faults, the potential/current pair used for directional and zone determination is the one which has the higher P11 (higher current).

The digital processing of distance relaying algorithms requires at least a 16 - bit CPU. As no 16 - bit currently available microprocessor was powerful enough to be used alone when the prototype studies started in 1979, and, on the other hand, to reach the targets set out in the introduction, a parallel processing approach was taken up. That is why the three-distance-unit relay is built from four INTEL SBC 86/12 A boards using the 8086 microprocessor. The different tasks are dispatched in order to minimize exchanges on the common bus (Intel's Multibus) and to avoid contention in sharing ressources. The general architecture is illustrated by figure 4. One master CPU synchonizes the whole relay, and processes the problems which concern several distance-elements: reading of the settings, sampling and preprocessing of data, phase selection, power-swing detection, sending of tripping orders and information. Three slave processors which are identical (same hardware and software) process the specific problems of one unit each (they compute impedances, direction, zone).

Directional discrimination
The direction of the fault (busbar-side or line-side) is computed as the sign of the inductance obtained from the following data: - the current of the selected phase - the corresponding memorized pre-fault voltage, shifted by two samples so that the directional reverse line in the (R, X) plan has a -30 angle with the R axis (see figure 3) to deal with the near resistive short-circuits. In the case of a fault appearing during a line energization (no pre-fault voltage), the short-circuit is always detected
as line-side

Figure 4 : General architecture of the digital relay

This simple structure induces a fairly good sharing of the tasks, since the master CPU is busy about 60 % of the 0.833 ms sampling period, and the slaves always less than 90 %, according to the programm branch they execute.
Current and voltage sampling

(downstream).
to the

Zone determination

According

value

of the computed

inductance of

the selected distance-unit, to

the direction of the fault and to

The data acquisition system has six channels for the potentials and voltage-converted currents of the three phases. There is no galvanic coupling between the transducers and the relay owing to the use of optoelectronic linear isolation

494

amplifiers with their isolated DC to DC converting powersupplies (the whole tolerate 5kV surges). Adjustable gains give the six analog signals their correct output levels: the voltages saturate when the phase potentials overstep the lumped peak rated voltage, the currents saturate over 40 kA to limit their dynamic range. Then, there are six -monochip anti-aliasing filters (3 pole Butterworth type) with a cut-off frequency of 550 Hz, and a 0.7 ms delay at 50 Hz. The filters are followed by six sample-holds. The sampling operation is initiated by one of the programmable timers of the master CPU's board, which delivers a "start conversion" command every 0.833 ms. This output is sent to six hybrid 12-bit analog-to-digital converters (ADC), whose status information at once triggers the sample-holds. Less than 25us later, an "end-of-conversion" signal is sent as an interrupt to the master CPU which can read the sampled values through the parallel l/O ports directly connected to its
-

Communication between processors Specialized buses between the CPU's and their specific units greatly simplify the communication problems: the slaves don't have to access the common bus, and are hardwareprevented to do so, avoiding priority resolution schemes. Only the master processor uses the common bus, to write the next data in the slaves' double-port RAMs and to read the results of the calculations. The synchronization of the 4 CPUs is achieved by means of a command sent by the master as soon as the new data are ready in the slaves' memories. This signal, comparable to an interrupt, is driven to the TEST input of the 3 slave 8086's, causing the reactivation of these processors, previously stopped by a wait instruction at the end of the last processing loop. On the other hand, any slave can interrupt the master in the case of hardware breakdown (this function is described below).

extended data bus. Twelve-bit ADC are at present the most accurate that can be reasonably used in the severe environment of an EHV substation relaying-house. Thus, to solve the problem of the dynamic range of currents (from a few hundred amperes to about 180 kA for asymmetrical faults in a 63 kA substation), it was decided to saturate these signals for the values exceeding 40 kA. By that way, the quantization step is about 20 A (for the EHV line), and enough accuracy during steady-state conditions is kept. This solution has been found to be better than

Settings and orders The settings of the relay are provided by thumb-wheels inserted into the front-plane of the device. This type of settings has been kept to maintain a "classical" man-machine interface. Six parameters are available: the limits of the 3 downstream zones and the upstream zone, the maximum resistance of the detected faults and the earth coefficient

two parallel ADC on each channel (one for the low values and one for the large), because the algorithm correctly copes with electronically saturated currents.

(zo-zd)/3 zd

Distance units
Each of the 3 slave processors has to compute an impedance every 0.833 ms, with in particular a large number of signed multiplications and additions. The 8086 is too slow to perform all of them during the sampling period. So, to each slave board, a fast arithmetic element was added. This unit is designed from a monochip TRW hardware multiplier-accumulator, which reckons a 16 x 16 bit multiplication and may accumulate the result to a 35-bit register in less than 155 ns. All the decoding and control circuitry is provided, so that the use of the arithmetic unit is very easy for the programmer: the decoders recognize the type of operation which has to be performed (multiplication or preload of a 32bit value in the accumulation register) and the control circuits operate the multiplier and the interface chips (parallel l/O devices, drivers and latches). The command which causes accumulation to a previous result is software generated. For the communications between the slave CPU's and their arithmetic units, the common bus could not be used: the requests to access it would have been much too frequent, with wait times downgrading the multiplier's performances. Thus, a private bus was created for each unit by extending the onboard data bus and by slightly modifying the address decode logic of the.SBC 86/12 A boards. As a result, a signed 16 x 16 bit multiplication of two CPU registers, with the result stored in other CPU registers, is performed in 8.8ys. When the accumulation command is used, this time asymptotically decreases to 4.4,us. The resistance and inductance are obtained by processing terms of the form (ab cd)/(ef gh), where the different elements are 32-bit numbers, and that may induce computing accuracy problems. To avoid this, terms like ab-cd are calculated as 64-bit fixed-point numbers, then converted into pseudofloatting-point values with hexadecimal exponent (multiple of 4) and 28-bit (for numerators) or 16-bit (for denominator) mantissa. The only operations on these floatting-point numbers are the last two divisions, which can be done easily by an 8086's instruction without overflow problems because of the length of the mantissas and the fact impedance is assumed to be infinite (and his computation stopped) whenever the denominator has an exponent less or equal to 4 (which means a line-current RMS value less than about 300 A).
-

Twelve orders and information are issued by the protection: starting of the relay, 3 phase-tripping signals, 4 zones, 2 direction information, power-swing detection and an autotest output described below. They are transmitted to the other equipment through optoelectronic decoupling relays (2,5 kV insulation voltage, 5is commutation time).
Rack and power supply

The relay is made of 8 INTEL SBC's format boards: 4 CPU's, 2 boards for the 3 arithmetic units, one for the analog filters and one for data sampling and acquisition. The input isolation amplifiers and the output relays are on the back of the device, for evident dielectric reasons. Figure 5 shows the ecuipment without its front-olane.

rigure

View oi

1.e

relay kwitnouu1

irrint-pidile)

495

The
DC
to

different

supply voltages
a

necessary

are

obtained

by

DC converters from

24 V
A for

D~C supply
15 V.

with batteries:

currents

35 A for 5 V, 1.2 A for

12

V,

Hardware failure detection

fault inception can be chosen, and the phase sequentially interrupted by the breakers on zerocrossing. One of the used network configuration is show, on figure 6 (the protection was settled in P or P9).
of
are

The

angle

Figures
Future
tolerant the

7,

and

show

some

short-circuits
a
:

on

this

studies

will

be

conducted

to

obtain

fault-

simulated busbar

400

kV

performances)
out these
are

relay, which could operate (may be with downgraded even in the case of -major hardware faults, and multiprocessor structure is a good starting point to carry
concepts. As
a

system.
behind
ins.

fault at Bl

Figure 7 displays the P relaying point

three-phase the tripping

time is about 17.5

This rather slow order is due to the low

level of the short-circuit currents

(about 1.5 time the preload

limited first step, many on-line tests

was

current).

performed by

the processors. The main idea

to

to

use

part of the available CPU time

known methods to
same

implement
the

easy and wellat

detect

most

of

failures, while

the

time

requiring only
not

very few additional

chips.
them

All these
we can

LI- jl6kA

--711

methods
outline
:

will

be

listed

here,

but

among

every processor has

if not

watchdog

which delivers

an

interrupt
rt

retriggered by
are

1.5 millisecond

.known values

stored and checked in the different RAM

of known

chips multiplications (with accumulation) perf ormed

most

operands
redundant

are

of

output information and orders

so

are

or

mutually exclusive,
output
2.2
x

that

the

probability

f or is

random

nfssage
expect

to

be taken

into consideration

less than

Z1.3Ii7 11 .zI-_Vb
pha.eBt.p____

______

10

The data

acquisition subsystem
to

has rather poor

as

check-up

tests,

as we

replace

it in the future

part of digital

autotestable mesurement transducers.

An autotest

output is permanently driven high when the

failure is

equipment general

is safe.
a

Whenever
reset

detected, it is driven low, and

equipment is issued, the disfuctionning element is checked again, and, if still incorrect, the supply of the output opto relays is completely switched off (till the protection is repared) to prevent hazardous tripping. This "two stage?? failure processing avoids having to disconnect the relay
of the for transient faults.

L..2
Figure
Figure
much
7
:

3-phase
an

fault at BI with the

relay

in P

8 shows

a-c

phases

fault

on

the measurement

transducers of the

Thus, with a minimum additional hardware (7 including the watchdogs), most of failure problems
dealt with. About has occured

chips
can

PI protection.
the

In this

case

the currents

are

be

higher,

but
on

large asymmetry
time:

has

still

an

unfavouare

rable effect

the clearance
ins.

the

tripping

orders

issued in about 12

reliability,
since

it should be noted
of

that

no

breakdown in

the, construction

the

prototype

December 1979.

TESTS ON THE PROTOTYPE After the steady-state tests carried out for a software debugging purpose, two kinds of data were used to try the simulations on an analog model of EHV systems, and relay records of real faults on 400 kV lines and busbars (from digital fault recorders or analog magnetic tapes).

_~~~~~~~~"V

Analog simulation
An

analog model,

EDF's

Microre'seau
and

at

Clamart,

was

used to create

hundreds of faults of various

types, including

sequentially developping
tions. This model
and the lines
are

short-circuits and losses of

structures

synchro-

nism, with different network

uses

load flow condisome

'I; O;r

actual

rotating
a

machines of

kVA,

simulated

by

number of

pi-cells.

S cc -14 100MVA

T3
1.32

111lkm)

CQ
2

laL
(infinite bus)

Figure
On

: a

phases

fault at

PI relaying point

3/5

of the

figure 9, we can see a double line-to-earth fault at length of line T5 : the tripping time is 13 ms in this

IP
Figure
6
:

T5 (103km)I
of simulated network

case.

example

496

--,16kA~~~~~~~~~~~~~~~~N

record was reportered from the healthy circuit. During the first 4 cycles, the current-flow has the same direction than on the faulted circuit (which induces a "zone 2" tripping decision).
I'

;;z;

=4
.V"

-Zi

AK1 XW a..V' - \./ .Z/ 'NY = \J 2.'

Figure 9

:a

b phases grounded fault on line T5

different type of short-circuits in various conditions

tripping signals finish less than 4 ms after fault clearance. Table I gives the maximum tripping times mesured for
Table I

For all these short-circuits, it should be noted that the

fault-inception, preload etc).

Relaying
Point
P P P p P P P P P P P P pi pi PI pi

(angle of

line

Figure 10 :actual phase c-to-ground fault

on a double-circuit

Type of
faulIt
1 phase earth 2P 2 P.E. 3p P 1 P. E. 2P 2 P.E. 1 P. E. 2P 2 P.E. 3P I P.E. 2P 2 P.E. 3P

Place of fault bus BI "

time (ins)

Tripping

3~ P

18 15 "12.5 18 19 bus B2 of 18 "17 19 14 4/5 of line T5

PI (line side)

Then the remote breaker opens, and the current-flow reverses for 1.5 cycle, before the short-circuit clearance. At that time, the relay finds that impedance and direction do not converge any longer, and latches its orders and information. Next, 17 ms later, it sends a "zone 4"1 (upstream) tripping order which is latched for 25 ms after fault clearance, since the protected line is not switched out. Figure 11 has been chosen to illustrate the necessity for a relay not only to trip actual faults, but also to keep quite during transient conditions when it is not directly concerned.

??16

??13.5 "13.5

I?9

?9.5
"9.5
.-....--.-...-

10

As that could have been foreseen, it has been established that the two major parameters influencing the tripping time are the level of the short-circuit current (the speed of convergence increases with it) and the importance of the zerosequence quantities in the case of earthed faults (the commutation time to change phase-phase impedance-elements into phase-to-ground units has to be added to convergence time).

Actual fault records

A library of over 50 fault records was made up during the past two years :single phase-to-ground and polyphase staged short-circuits on lines and busbars, including arcresistive faults. Several types of normal switching operations, such as line energizing or disconnecting and load shif ts have also been reportered. All these records, f rom either magnetic tapes or digital permanent equipments, have a minimum bandwidth of 2 kHz and have been used to test the relay, the performances of which were beared out. Figure 10 shows a phase c-to-ground short-circuit on a 400 kV, 33 km double-circuit line near the Fessenheim nuclear power-plant :it happened at the remote end and this
at its remote end

Figure 11: 3-phase busbar fault with the protected line opened

A 3-phase busbar short-circuit was initiated at Bayet 400 kV substation just behind the protected circuit, with the 110 km line opened at its remote end. Transient currents of over 1.5 kA peak at 580 Hz appeared, associated to a full drop of voltages :as required, no tripping order was issued. As a last stage in the relay tests, the prototype is beeing permanently installed (during the first term of 1981) in a relaying house of a 400 kV EDF's substation.

497

CONCLUSION
The used algorithm has given satisfactory results in the fields of speed, accuracy and ability to be implemented. It has allowed to achieve the aimed performances, but it must be beared in mind that it is only a part of a digital relay software. In particular, whether the speed of the protection is limited by the time required for the algorithm to compute the right impedance values, plus the delay to make sure that they are actually the right values (convergence tests), it is restricted as well by the choice of the data to be processed (commutation between phase-to-phase and phase-to-ground quantities). The prototype built to implement the software is a powerful machine, and its 4-processor architecture is well suited to relaying computation for 3-phase systems, but versatile enough to insure a good flexibility. Besides, the simple task distribution provides a fairly easy software debugging, and allows to expect successful developments in the field of hardware-fault tolerance. Furthermore, the cost of the equipment, if not yet economically competitive, is quite reasonable, despite of the fact it has been designed on the basis of hardware available in 1978. The permanent tests on the EDF's 400 kV system will permit to corroborate the good behaviour of the protection in a relaying-house environment.

REFERENCES

[Ii J.G. GILBERT, E.A. UDREN, and M. SACKIN "The development and selection of algorithms for relaying of transmission lines by digital computers".Power System Control and Protection.New-York: Academic Press, 1978, pp 83 - 126.

[21 B.J. CORY, G. DROMEY, and B.E. MURRAY "Systemes numeriques pour les protections". CIGRE 1976, report 34-08.

Chamb6ry (France) on May 1953.In 1975 he obtained the degree of Ing6nieur Diplomt from the Ecole Superieure
diesand Research Department Clamart, near Paris. P. Bornard is a CIGRE (1978) and IEEE (1981) member.
at

Pierre Bornard was born in

ying techniques at EDF's Stu-

Since 1976, he works on rela-

Jean-Claude Bastide was born in Paris (France) in 1936. He joined EDF in 1956. He is since 1964with the Studiesand Research Department, where he works on relays and automation devices.
zone to 80% of the line. Present practice is to set first zone for 90%. Do the authors have plans and techniques to improve the accuracy in order to meet this requirement?

Discussion W. D. Breingan, and M. M. Chen (General Electric Company, King of Prussia, PA): We would like to congratulate the authors on their paper describing their work with a digital relay. The presentation of the hardware and software aspects, which used a multiprocessing concept, is especially a welcome addition to the digital relaying literature. There are. several quesions concerning this paper: 1. We also used an algorithm based on the difference equation representation of the protected circuit. (See references below.) However, our algorithm is computationally simpler in that we solved the difference equation directly for resistance and inductance, rather than using matrix methods. This simpler algorithm gives steady state estimates of: R =Ro wt and T L = Lo tan Wt
As a whole, they give a better result than those given by the authors' equation (8). Would the authors comment on why the more complicated matrix algorithm results in more error than our simpler

7. In the test procesure, the authors state that the analog model was used to create hundreds of faults; a library of 50 actual faults is available. In Table I, there are only 16 tests listed. Do the authors have more complete results showing the ranges of test conditions, as well as the ranges of trip times for a wide range of

system conditions? 8. The authors use 3 sets of processing hardware to perform 3 identical R, L. determination for the 3 phases. Why did the authors choose this approach instead of preselecting (classifying) the fault type and doing one calculation? Also, did the authors study the effects of using data from the unfaulted phases on the calculation?
REFERENCES

algorithm? 2. There is some confusion on our part concerning the window size and its content. It is stated in the paper that the window uses 18 sample points which is 15 milliseconds for the given sampling frequency. Yet the test data indicates tripping times which include values from 9.0 to 14 milliseconds. This suggests that the authors may be using some pre-fault data in the matrix calculations. Is this the technique to obtain these shorter trip times? 3. We are intrigued by the technique for handling the range of fault currents. It appears to us, however, this approach may have computational problems. With the use of saturating analog to ditital converters, the incoming current signals will be constant (the saturated value). For constant currents, the Ps of the authors' equation (6) will be zero. This will lead to division by zero in the calculation of the a's. How do the authors handle this situation? 4. The authors' point of view on the aliasing filter is very interesting. We found in our work that the conventional requirement on antialiasing is not applicable. Have the authors done work on the effect of aliasing on the algorithm to justify their point of view? 5. Did the authors incorporate any special technique to handle the problem of high fault resistance and load flow? This situation results in severe alteration of apparent R and L, and may cause misoperation of the protection scheme using the algorithm. 6. The authors stated that they have enough accuracy to set the first

1. W. D. Breingan, M. M. Chen, and T. F. Gallen: "The Laboratory Investigation of a Digital System for the Protection of Transmission Lines". IEEE Transactions on Power Apparatus and Systems, Vol. PAS-98, No. 2, March/April 1979, pp. 350-368. 2. T. F. Gallen, W. D. Breingan, and M. M. Chen: "A Digital System for Directional-Comparison Relaying". IEEE Transactions on PAS - Vol. PAS-98, No. 3, May/June 1979, pp. 948-956. 3. M. M. Chen, W. D. Breingan, and T. F. Gallen: "Field Experience with a Digital System for Transmission Line Protection". IEEE Transactions on PAS - Vol. PAS-98, No. 5, September/October 1979, pp. 1796-1805.

Manuscript received August 17, 1981.

P. Bornard and J. C. Bastide: We should like first to thank the Discussors for their questions and the interest shown in this paper. We will answer the different points in the order they were raised. I- It must be clear that there is no "error" in the computation of R and L according to equations (8). From these equations, it is obvious that the actual values R. and L. can be easily extracted, as tg (w t/2) and wt/sinwT are fixed quantities. But this extraction is unnecessary: the constant factor wt/sinw T is taken into account by the relay by multiplying the settings chosen for the different zones, and the expression of R allows an improved tripping characteristic, the shape of which is better than a rectangle. The equations of the oblique lines of this parallelogram are:

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R L'tg (wT/2) = RD These considerations show that the "error" factors (which come from the time quantization (T for dt) and from the cross products like i (t). i[t- T]) improve the relay characteristics. In fact, the interest of the matrix algorithm is to provide a better digital filtering, as well as a fast convergence speed. The impedances are computed at every sample (during any steadystate or fault.condition), with mobile sampling windows shifted by T. Of course, when a fault occurs, some pre-fault data are used in the matrix calculations. In case of a severe short-circuit, the convergence of the computed values is fast (it is checked as explained in the paper paragraph "Tripping characteristic") and a tripping order may be issued in times as short as 8 ms (0.4 cycle). To bring out difficulties due to the converter saturation, the current should be constant at the saturated value (i.e. greater than 40 KA) for 18 successive sample (/4 of a cycle). This is fortunately impossible on our system. An advantage of the mean-square algorithm is its ability to cope with saturated signals, so long as some samples have a different value. With practical signals, the algorithm avoids the problem of singularities. Yet, for obvious reasons related to software reliability, every denominator is checked before a division to prevent any overflow problem. The algorithm is a digital filter used to extract quantities at the system frequency (50 Hz). It is consequently important to avoid confusion between this frequency and its images near fe/2' and this implies an analog anti-aliasing filtering. But, for the other frequencies of the [0, fe/2] band, nothing should have to be requested if the algorithm was perfect (i.e. providing a perfect rejection). As actually these frequencies may induce some errors in the impedance computations, it would not be reasonnable to allow a large aliasing effect. An ideal design of the analog filters must include a study of the primary signal spectra and the effect of t-ransducers, as well as the algorithm response to non-fondamental frequencies. The problem of high resistance fault and load flow is generally a problem of discrimination between normal steady-state and fault conditions, especially in case of a bilateral supply of the shortcircuit. A possible future evolution of the relay could include a dynamically computed tripping characteristic, according to the load. But there is a limit inherent to impedance relaying, and the solution of this problem is probably the use of other devices such as zero-sequence or differential relays.
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6 - The present practice on the French network for the setting of the first zone is 80Wo of the line, and that explains our choice. The improvement of the accuracy is not only a relay problem, but implies as well a good knowledge of the transducers performance during electromagnetic transients. This point is presently being investigated. 7 - The 16 tests appearing in Table I are the ones which have given the longest tripping time during short-circuits on the network illustrated by figure 6 in the following conditions: fault inception angle varying from 00 to 3600 (by 100), and loads from + 1200 MW to - 200 MW and + 600 MVar to - 600 MVar on the protected line. The minimum tripping time is 0.4 cycle and it is reached for severe short-circuits. In all cases, the tripping time is always less than 1 cycle. A full report will be published on the relay performance, including the real faults it has tripped in the Albertville 400 KV substation where it was installed on June 1981 (on 15 Sept. 1981, 25 short-circuits have been correctly detected). 8 - Several considerations have led to the choice of 3 sets of processing hardware to perform 3 identical R and L determination (notwithstanding the fact that the prototype does not aim at an industrialization of the very same architecture): First, classifying the fault before the beginning of any impedance computation induces delay of the tripping signal: this delay is the time needed to process the previous samples of the chosen phase, plus the time to check the convergence of the computed values (the classification of the fault in our case needs about 6 ms). This problem is still sharper in case of a developing short-circuit. Then, 3 impedance computations allow to check the results coherence, according to the relay autotest procedures. The meaning of the last part of the question does not appear very clear to us. As far as we understand it, we should answer that the data from unfaulted phases are not used to trip the relay, since, after the phase selection, only the quantities related to the faulty phase(s) are considered.
Manuscript received September 25, 1981.