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    40174

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    Merényi Oszkár
    This document provides a data sheet for the HEF40174B MSI Hex D-type flip-flop integrated circuit from Philips Semiconductors. The summary includes: The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs, a clock input, a master reset input, and six buffered outputs. Information is transferred from the data inputs to outputs on the rising edge of the clock input when the reset input is high. When low, the reset input resets all flip-flops independently of the clock and data inputs.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    40174

    Uploaded by

    Merényi Oszkár
    133 views5 pages
    This document provides a data sheet for the HEF40174B MSI Hex D-type flip-flop integrated circuit from Philips Semiconductors. The summary includes: The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs, a clock input, a master reset input, and six buffered outputs. Information is transferred from the data inputs to outputs on the rising edge of the clock input when the reset input is high. When low, the reset input resets all flip-flops independently of the clock and data inputs.

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    This document provides a data sheet for the HEF40174B MSI Hex D-type flip-flop integrated circuit from Philips Semiconductors. The summary includes: The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs, a clock input, a master reset input, and six buffered outputs. Information is transferred from the data inputs to outputs on the rising edge of the clock input when the reset input is high. When low, the reset input resets all flip-flops independently of the clock and data inputs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    133 views5 pages

    40174

    Uploaded by

    Merényi Oszkár
    This document provides a data sheet for the HEF40174B MSI Hex D-type flip-flop integrated circuit from Philips Semiconductors. The summary includes: The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs, a clock input, a master reset input, and six buffered outputs. Information is transferred from the data inputs to outputs on the rising edge of the clock input when the reset input is high. When low, the reset input resets all flip-flops independently of the clock and data inputs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    INTEGRATED CIRCUITS

    DATA SHEET
    For a complete data sheet, please also download:
    The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

    HEF40174B MSI Hex D-type flip-flop


    Product specication File under Integrated Circuits, IC04 January 1995

    Philips Semiconductors

    Product specication

    Hex D-type ip-op


    DESCRIPTION The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs (D0 to D5), a clock input (CP), an overriding asynchronous master reset input (MR), and six

    HEF40174B MSI
    buffered outputs (O0 to O5). Information on D0 to D5 is transferred to O0 to O5 on the LOW to HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (O0 to O5 = LOW) independent of CP and D0 to D5.

    Fig.1 Functional diagram.

    PINNING D0 to D5 CP MR O0 to O5 data inputs clock input (LOW to HIGH; edge-triggered) master reset input (active LOW) buffered outputs

    FUNCTION TABLE Fig.2 Pinning diagram. CP HEF40174BP(N): 16-lead DIL; plastic (SOT38-1) HEF40174BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF40174BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition X INPUTS D H L X X MR H H H L OUTPUT O H L no change L

    This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 3 Fig.3 Logic diagram. Philips Semiconductors

    Hex D-type ip-op HEF40174B MSI

    Product specication

    Philips Semiconductors

    Product specication

    Hex D-type ip-op


    AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 LOW to HIGH Set-up time Dn CP Hold time Dn CP Minimum clock pulse width; LOW Minimum MR pulse width; LOW Recovery time for MR Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRMR tWMRL tWCPL thold tsu 20 10 10 10 5 5 70 30 20 70 35 25 45 20 15 5 15 20 tTLH tTHL tPHL tPLH tPHL 75 30 20 75 30 20 85 35 25 60 30 20 60 30 20 10 5 5 0 0 0 35 15 10 35 15 10 25 10 5 11 30 45 155 ns 65 ns 45 ns 155 ns 65 ns 45 ns 175 ns 70 ns 50 ns 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz SYMBOL MIN. TYP. MAX.

    HEF40174B MSI

    TYPICAL EXTRAPOLATION FORMULA 48 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 48 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 58 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL

    see also waveforms Fig.4

    January 1995

    Philips Semiconductors

    Product specication

    Hex D-type ip-op

    HEF40174B MSI

    VDD V Dynamic power dissipation per package (P) 5 10 15

    TYPICAL FORMULA FOR P(W) 3500 fi + (foCL) VDD2 16 000 fi + (foCL) VDD 42 000 fi + (foCL) VDD
    2 2

    where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)

    Fig.4

    Waveforms showing minimum pulse widths for CP and MR, MR to CP recovery time, and set-up time and hold time for Dn to CP. Set-up and hold times are shown as positive values but may be specified as negative values.

    APPLICATION INFORMATION Some examples of applications for the HEF40174B are: Shift registers Buffer/storage register Pattern generator

    January 1995

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