Data Sheet: HEF4013B Flip-Flops Dual D-Type Flip-Flop

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4013B
flip-flops
Dual D-type flip-flop
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
HEF4013B
flip-flops

DESCRIPTION
FUNCTION TABLES
The HEF4013B is a dual D-type flip-flop which features

independent set direct (SD), clear direct (CD), clock inputs (CP)
and outputs (O, O). Data is accepted when CP is LOW and
transferred to the output on the positive-going edge of the
clock. The active HIGH asynchronous
clear-direct (CD) and set-direct (SD) are independent and
override the D or CP inputs. The outputs are buffered for best
system performance. Schmitt-trigger action in the clock input
makes the circuit highly tolerant to slower clock rise and fall
times.
INPUTS
OUTPUTS
SD
CD
CP
INPUTS
OUTPUTS
D
On 1
On1
SD
CD
L
L
CP
Notes
1. H = HIGH state (the more positive voltage)
L=LOW state (the less positive voltage)
X=state is immaterial
= positive-going transition
On 1 = state after clock positive transition
PINNING
D
data inputs
CP
clock input (L to H edge-triggered)
SD
asynchronous set-direct input (active HIGH) CD
asynchronous clear-direct input (active HIGH) O
true
output
O
Fig.1 Functional diagram.
complement output
HEF4013BP(N):
14-lead DIL; plastic

(SOT27-1)
HEF4013BD(F):
14-lead DIL; ceramic (cerdip)
HEF4013BT(D):
14-lead SO; plastic
(SOT73)
(SOT108-1)
( ): Package Designator North America
FAMILY DATA, I DD LIMITS category FLIP-FLOPS See
Fig.2 Pinning diagram.
January 1995
Family Specifications
HEF4013B
flip-flops
January 1995
HEF4013B
flip-flops

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25
C; CL = 50 pF; input transition times 20 ns

VDD
V
SYMBOL
MIN.
TYPICAL EXTRAPOLATION
FORMULA
TYP.
MAX.
110
220
ns
83 ns
(0,55 ns/pF) CL
Propagation delays
CP O, O
HIGH to LOW
LOW to HIGH
SD O
HIGH to LOW
SD O
LOW to HIGH
45
90
ns
34 ns
(0,23 ns/pF) CL
15
30
60
ns
22 ns
(0,16 ns/pF) CL
95
190
ns
68 ns
(0,55 ns/pF) CL
10
tPHL
40
80
ns
29 ns
(0,23 ns/pF) CL
15
30
60
ns
22 ns
(0,16 ns/pF) CL
5
10
100
40
200
80
ns
ns
73 ns
29 ns
(0,55 ns/pF) CL
(0,23 ns/pF) CL
15
30
60
ns
22 ns
(0,16 ns/pF) CL
5
10
75
35
150
70
ns
ns
48 ns
24 ns
(0,55 ns/pF) CL
(0,23 ns/pF) CL
25
50
ns
17 ns
(0,16 ns/pF) CL
100
40
200
80
ns
ns
73 ns
29 ns
(0,55 ns/pF) CL
(0,23 ns/pF) CL
30
60
ns
22 ns
(0,16 ns/pF) CL
60
30
120
60
ns
ns
33 ns
19 ns
(0,55 ns/pF) CL
(0,23 ns/pF) CL
15
20
40
ns
12 ns
(0,16 ns/pF) CL
60
120
ns
10 ns
(1,0 ns/pF) CL
10
tPLH
tPHL
tPLH
15
CD O
HIGH to LOW
5
10
tPHL
15
CD O
LOW to HIGH
Output transition times

HIGH to LOW
LOW to HIGH
5
10
tPLH
30
60
ns
9 ns
(0,42 ns/pF) CL
15
20
40
ns
6 ns
(0,28 ns/pF) CL
60
120
ns
10 ns
30
60
ns
9 ns
(0,42 ns/pF) CL
20
40
ns
6 ns
(0,28 ns/pF) CL
10
10
tTHL
tTLH
15
January 1995
(1,0 ns/pF) CL
HEF4013B
flip-flops

AC CHARACTERISTI CS
VSS = 0 V; Tamb = 25C; CL
= 50 pF; input transition times 20

VDD
V
Set-up time
D CP
10
Hold time
D CP
Minimum clock
pulse width; LOW
Minimum SD pulse
width; HIGH
Minimum CD pulse
width; HIGH
Recovery time
for SD
Recovery time
for CD
Maximum clock
pulse frequency
SYMBOL
MIN.
ns
TYP.
40
20
ns
25
10
ns
15
15
ns
20
ns
10
20
ns
15
15
ns
60
30
ns
10
30
15
ns
15
20
10
ns
50
25
ns
24
12
ns
15
20
10
ns
50
25
ns
10
10
tsu
thold
tWCPL
tWSDH
24
12
ns
15
20
10
ns
15
ns
10
tWCDH
15
ns
15
15
ns
40
25
ns
10
tRSD
25
10
ns
25
10
ns
14
MHz
14
28
MHz
20
40
MHz
10
VDD
V
tRCD
see also waveforms

Figs 4 and 5
15
15
fmax
TYPICAL FORMULA FOR P (W)
850 fi (foCL) VDD 2
dissipation per
10
3 600 fi (foCL) VDD 2
package (P)
15
9 000 fi (foCL) VDD 2
Dynamic power
MAX.
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = total load cap. (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
HEF4013B
flip-flops
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.
January 1995
HEF4013B
flip-flops

APPLICATION INFORMATION
Some examples of applications for the HEF4013B are:
Counters/dividers
Registers
Toggle flip-flops
Fig.6 Typical application of the HEF4013B in an n-stage shift register.
Fig.7 Typical application of the HEF4013B in a binary ripple up-counter; divide-by-2n.
Fig.8 Typical application of the HEF4013B in a modified ring counter; divide-by-(n + 1).
January 1995
This datasheet has been download from:

www.datasheetcatalog.com
Datasheets for electronics components.

Data Sheet: HEF4013B Flip-Flops Dual D-Type Flip-Flop

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INTEGRATED CIRCUITS

Dual D-type flip-flop

The HEF4013B is a dual D-type flip-flop which features

clock input (L to H edge-triggered)

asynchronous set-direct input (active HIGH) CD

asynchronous clear-direct input (active HIGH) O

Fig.1 Functional diagram.

14-lead DIL; plastic

14-lead DIL; ceramic (cerdip)

14-lead SO; plastic

Dual D-type flip-flop

Dual D-type flip-flop

C; CL = 50 pF; input transition times 20 ns

Output transition times

Dual D-type flip-flop

= 50 pF; input transition times 20

see also waveforms

TYPICAL FORMULA FOR P (W)

850 fi (foCL) VDD 2

3 600 fi (foCL) VDD 2

9 000 fi (foCL) VDD 2

Dual D-type flip-flop

Dual D-type flip-flop

Fig.6 Typical application of the HEF4013B in an n-stage shift register.

Fig.7 Typical application of the HEF4013B in a binary ripple up-counter; divide-by-2n.

This datasheet has been download from:

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