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    Ffe Dfe Excerpt

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    Saujal Vaishnav
    This document discusses equalization techniques used in high-speed communication links, including transmitter FIR equalization, receiver CTLE equalization, and receiver decision feedback equalization (DFE). DFE is a nonlinear equalization technique that subtracts past decisions from the incoming signal to cancel inter-symbol interference. It has advantages over linear equalization in that it can boost high frequencies without amplifying noise and adaptively tune filter coefficients. However, it cannot cancel precursor interference and risks error propagation. Examples of DFE implementations discuss critical timing paths and methods to improve summer performance.

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    Ffe Dfe Excerpt

    Uploaded by

    Saujal Vaishnav
    167 views14 pages
    This document discusses equalization techniques used in high-speed communication links, including transmitter FIR equalization, receiver CTLE equalization, and receiver decision feedback equalization (DFE). DFE is a nonlinear equalization technique that subtracts past decisions from the incoming signal to cancel inter-symbol interference. It has advantages over linear equalization in that it can boost high frequencies without amplifying noise and adaptively tune filter coefficients. However, it cannot cancel precursor interference and risks error propagation. Examples of DFE implementations discuss critical timing paths and methods to improve summer performance.

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    This document discusses equalization techniques used in high-speed communication links, including transmitter FIR equalization, receiver CTLE equalization, and receiver decision feedback equalization (DFE). DFE is a nonlinear equalization technique that subtracts past decisions from the incoming signal to cancel inter-symbol interference. It has advantages over linear equalization in that it can boost high frequencies without amplifying noise and adaptively tune filter coefficients. However, it cannot cancel precursor interference and risks error propagation. Examples of DFE implementations discuss critical timing paths and methods to improve summer performance.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    167 views14 pages

    Ffe Dfe Excerpt

    Uploaded by

    Saujal Vaishnav
    This document discusses equalization techniques used in high-speed communication links, including transmitter FIR equalization, receiver CTLE equalization, and receiver decision feedback equalization (DFE). DFE is a nonlinear equalization technique that subtracts past decisions from the incoming signal to cancel inter-symbol interference. It has advantages over linear equalization in that it can boost high frequencies without amplifying noise and adaptively tune filter coefficients. However, it cannot cancel precursor interference and risks error propagation. Examples of DFE implementations discuss critical timing paths and methods to improve summer performance.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 14

    ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010

    Lecture 19: RX DFE Equalization

    Sam Palermo Analog & Mixed-Signal Center Texas A&M University

    Link with Equalization


    TX FIR Equalization RX CTLE + DFE Equalization Channel

    DTX[N:0]

    Deserializer

    Serializer

    DRX[N:0]

    TX Clk Generation (PLL)

    RX Clk Recovery (CDR/Fwd Clk)

    TX FIR Equalization
    TX FIR filter pre-distorts transmitted pulse in order to invert channel distortion at the cost of attenuated transmit signal (de-emphasis)
    w-1

    TX data

    z-1

    w0 w1 w2

    z-1 z-1

    z-1

    wn

    RX FIR Equalization
    Delay analog input signal and multiply by equalization coefficients Pros
    With sufficient dynamic range, can amplify high frequency content (rather than attenuate low frequencies) Can cancel ISI in pre-cursor and beyond filter span Filter tap coefficients can be adaptively tuned without any back-channel

    Cons
    Amplifies noise/crosstalk Implementation of analog delays Tap precision

    [Hall]

    RX CTLE Equalization

    Vo+ Din-

    VoDin+

    Pros

    Provides gain and equalization with low power and area overhead Can cancel both precursor and long-tail ISI Generally limited to 1st order compensation Amplifies noise/crosstalk PVT sensitivity Can be hard to tune
    7

    Cons

    RX Decision Feedback Equalization (DFE)


    DFE is a non-linear equalizer Slicer makes a symbol decision, i.e. quantizes input ISI is then directly subtracted from the incoming signal via a feedback FIR filter
    z k = yk w1 d k 1 wn 1 d k (n 1) wn d k n
    ~ ~ ~

    RX Decision Feedback Equalization (DFE)


    Pros
    Can boost high frequency content without noise and crosstalk amplification Filter tap coefficients can be adaptively tuned without any back-channel

    z k = yk w1 d k 1 wn 1 d k (n 1) wn d k n

    Cons
    Cannot cancel pre-cursor ISI Chance for error propagation
    Low in practical links (BER=10-12)

    Critical feedback timing path Timing of ISI subtraction complicates CDR phase detection

    [Payne]
    9

    DFE Example
    If only DFE equalization, DFE tap coefficients should equal the unequalized channel pulse response values [a1 a2 an] With other equalization, DFE tap coefficients should equal the pre-DFE pulse response values
    [w1 w2]=[a1 a2]

    a1 a2

    10

    Direct Feedback DFE Example (TI)


    rate architecture Adaptive tap algorithm Closes timing on 1st tap in UI for convergence of both adaptive equalization tap values and CDR
    CLK0/180

    to demux

    6.25Gb/s 4-tap DFE

    TAP1: 5 bits TAP2: 4 bits + sign TAP3,4: 3 bits + sign

    A2 A2
    VDD RXIN

    DFECLK
    Latch Latch Latch

    A1

    RXEQ

    TAP1

    TAP2

    TAP3

    CLK90/270

    Latch

    Latch

    Feedback tap mux

    R. Payne et al, A 6.25-Gb/s Binary Transceiver in 0.13-um CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels, JSSC, vol. 40, no. 12, Dec. 2005, pp. 2646-2657

    TAP4

    Latch

    to demux

    11

    Direct Feedback DFE Critical Path


    RXIN tPROPA2 RXEQ tCLK
    QSA

    D0

    A1

    A2

    TIME <1UI
    CLK90 t PROPMUX
    RXEQ CLK90 1UI

    [Payne]

    tCLK QSA + t PROPMUX + t PROPA2 1UI

    Must resolve data and feedback in 1 bit period


    TI design actually does this in UI for CDR
    12

    DFE Loop Unrolling


    dk|dk-1=1 yk dk|dk-1=-1 dk-1

    [Stojanovic]

    Instead of feeding back and subtracting ISI in 1UI Unroll loop and pre-compute 2 possibilities (1-tap DFE) with adjustable slicer threshold

    dk|dk-1=1

    With increasing tap number, comparator number grows as 2#taps

    =w1
    ~

    dk|dk-1=-1

    ~ sgn ( yk w1 ) " if" d k 1 = 1 dk = ~ sgn ( yk + w1 ) " if" d k 1 = 1

    13

    DFE Resistive-Load Summer

    [Park]
    Summer Swing = IR, = RC

    Summer performance is critical for DFE operation Summer must settle within a certain level of accuracy (>95%) for ISI cancellation Trade-off between summer output swing and settling time Can result in large bias currents for input and taps
    14

    DFE Integrating Summer

    [Park ISSCC 2007]

    Integrating current onto load capacitances eliminates RC settling time Since T/C > R, bias current can be reduced for a given output swing
    Typically a 3x bias current reduction
    15

    Digital RX FIR & DFE Equalization Example

    [Harwood ISSCC 2007] 12.5GS/s 4.5-bit Flash ADC in 65nm CMOS 2-tap FFE & 5-tap DFE XCVR power (inc. TX) = 330mW, Analog = 245mW, Digital = 85mW
    16

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